[ANN][BLC] Blakecoin Blake-256 for GPU/FPGA With Merged Mined Pools Stable Net

[kramble]

maybe they got programmed by edge connector?

Yep, the JTAG signals are brought out to the DIMM connector (page 2 of the schematic). It should be possible to check signal continuity between the JTAG cable and the edge connector pins using a multimeter (expect 200 ohm resistance due to two sets of series protection resistors, though the ESD protection diodes on the FPGA chips may confuse the issue). I'd probably do this as a last resort though, as there is no knowing what sort of voltages a random multimeter would apply to the board.

[loaded101]

Hi Kramble,

Thanks for the info re. Lancelot WU etc. I am using 195MHz clock and Icarus Timing 1.0 = 20 so looks like it's doing OK.

Currently trying to get an Icarus working. I am using a bunch of chopped off resistor ends as a Jtag connector, will let you know if it works. I am assuming I can use the same .mcs file as for the Lancelot board.

If it's any help to the others trying to program these, the GND lines appear to be on the top row of the Jtag connector when viewed with the writing facing the correct way. This makes VREF the bottom right pin.

[kramble]

Thanks for the info re. Lancelot WU etc. I am using 195MHz clock and Icarus Timing 1.0 = 20 so looks like it's doing OK.

Currently trying to get an Icarus working. I am using a bunch of chopped off resistor ends as a Jtag connector, will let you know if it works. I am assuming I can use the same .mcs file as for the Lancelot board.

If it's any help to the others trying to program these, the GND lines appear to be on the top row of the Jtag connector when viewed with the writing facing the correct way. This makes VREF the bottom right pin.

I guess that could work, though the resulting pins might be a bit too thin. It's a bit unfortunate that the standard connector is 2mm pitch as 0.1 inch header strips are much easier to get hold of. You don't need to connect all 14 pins, just the 6 VREF,GND,TMS,TCK,TDO,TDI (see the schematic I linked in the post above).

The lancelot bitfile should work on icarus (that was the original intention), and you can easily convert the bit file to mcs using impact, the procedure is documented somewhere on the forums but just FYI these are my crib notes (the 45 minutes is for my homebrew parallel port JTAG programmer, the USB one should be a lot faster, 15 minutes ISTR from bluedragon)

Code:

Power cycled the Lancelot (so now has bitcoin bitstream)
Assigned blakefourbufce-2core-ucf146-fmax154.bit (probably unnecessary)
Double click on left-pane "Create PROM FILE (PROM File Formatter)"
Step1: SPI Flash/Configure Single FPGA and press green arrow
Step2: Select 64M / Add Storage Device and press green arrow
Step3: Browse to C:\Blakecoin and set name blakefourbufce-2core-ucf146-fmax154.MCS (paste it in)
Leave rest at defaults (Fill FF, MCS, No).
Press OK. Dialog box opens "Start adding", press OK the browse to blakefourbufce-2core-ucf146-fmax154.bit
At "Add another" press NO.
HMM, it has NOT created a MCS file!! Aha, need to do... Operations/GenerateFile
Creates MCS, PRM, CFI files (the last two are tiny)
Return to Boundary Scan tab
Right click on 1st FPGA, Add SPI/BPI, select the MCS file, SPI PROM, "W25Q64BV/CV", 1
Now we have a "FLASH" button
Repeat for 2nd FPGA
Click on the 1st FPGA FLASH, Right Click and Program, Takes approx 45 mins (Erase/Program/Readback) 46% on progress bar.
NB FPGA is in programmed state on completion.
Repeat for 2nd FPGA
Power cycled ... HMM, takes around 12 seconds to initialize, a LOT SLOWER then bitcoin did! But its OK.
Perhaps this is because I specified a 1 bit PROM (from Ngzhang on Icarus), maybe Lancelot allows more?
Tested with "./blakeminer.py 195" ... working OK on both devices (0..3 and 8..b MSB nonces).

You might want to try bluedragon's tri-core bitstream (it's on the previous page) which only clocks at 160MHz, but is around 25% faster due to the additional core.

[loaded101]

Bzyzny,

I have the Icarus initialising Jtag chain successfully. I'm using 13.1 64 bit - which worked to program a Lancelot previously.

I haven't needed to reset anything on the Icarus to get this far.

However, after programming, I get an error as follows:

"Configuration data download to FPGA was not successful. DONE did not go high, please check your configuration setup and mode settings.
INFO:iMPACT - '1': Flash was not programmed successfully."

Currently stuck at this point.

Kramble,

I am using the .mcs file which you posted earlier in this thread, which works on my Lancelot board. I will try a .bit file and see if I have any more success.

[loaded101]

Working with Bluedragon's .bit file!

Getting WU of 13.7 after 5 mins.

[kramble]

Working with Bluedragon's .bit file!

Great. The only problem is the need to reprogram each time you power up the board

What stage did the MCS programming fail at? There are several distinct steps, AFAIR

1. It downloads a special programming bitstream to the FPGA
2. Erasure of the ROM
3. Program the ROM
4. Verify the ROM
5. Initialize bitstream from ROM

Did you set the SPI PROM device to "W25Q64BV/CV", 1bit ?

[loaded101]

Hi,

Was just posting re. the data width, I have selected 4 which works with Lancelot (was following instructions here: http://www.cardreaderfactory.com/lancelot-firmware-update.html?sl=en)

I will try again with 1 and see what happens.

It seems to be failing after verification so presumably at the initialisation stage.

Thanks.

[kramble]

OK, that explains why it loaded so much slower on my lancelot than the original bitcoin bitstream.

Ngzhang's instructions for the Icarus (link) (scroll down a bit) specified 1 bit and I just used the same for the lancelot.

It's also worth power cycling the board and seeing if the bitstream loads anyway, since it could just be a quirk with the final initialization step.

[coutts]

I can't find a mining calculator, so here's a fun experiment. I am mining BLC with a small R9 270 rig (4 cards), ~6.6 GH/s. For the past 6 days I had consistent mining (no disconnects / extended periods of not mining). I've graphed my results here:

https://i.imgur.com/Uj9ggQD.png

Note: i just realized that's not an accurate BLC/day figure in the graph itself, I set the pool to pay out 50 BLC at a time and theres about 4 payouts per day so each mini bar is just a payout from the pool. I should update the label to not say blc/day (too lazy now that it's made).

Anyways, according to the Bitcoin mining calculator with current BLC figures, I'm supposed to mine 283.3909 BLC/day. If you factor in that BLC is 30% more efficient than bitcoin: 283.4 - (283.4 * 0.30) = 198.38 -- very close to my observed ~200 BLC/day.


Is there a mining calculator out there I just don't know about?


Also, is there any p2pool setup yet? The network seems very centralized on blakecoin.org servers at the moment.



EDIT

Okay, fixed the graph:

https://i.imgur.com/luJH8nh.png

[loaded101]

Still failing on 1 bit - see pastebin for output.

http://pastebin.com/rQB8PYWm

I'm going to try using your instructions to convert the 3 core .bit file to a .mcs and see if this works.

[Calhil]

@coutts
What difficulty did you use in your calculations? Right now blakecoin difficulty can have really big spikes, so you should try to average it to get the right results.

At the current price level imo its better to mine other coins and just buy BLC.

[kramble]

Still failing on 1 bit - see pastebin for output.
http://pastebin.com/rQB8PYWm
I'm going to try using your instructions to convert the 3 core .bit file to a .mcs and see if this works.

It's complaining about a missing .cfi file, doing the conversion yourself will fix that, and it's a faster bitstream anyway, so it's the one you'll want to have programmed into the ROMs.

I had a look at the xilinx spartan 6 configuration guide (ug380), fiendishly complicated. It seems to say that 1 bit is the default for SPI, and that the 4 bit option needs to be enabled by a bitgen parameter spi_buswidth:4 (which is done during the build process, and I certainly didn't set it). Except that you've got it to work on the lancelot anyway, so impact must be overriding that setting. Anyway the lancelot and icarus are using the same ROMs, so if it works on one, it ought to work on the other too.
EDIT: Actually there is a slight difference, a missing pullup resistor on the Icarus CSO_B pin, which might possibly affect it.

Did you try power cycling it after programming? The fact that the ROM verified OK seems to suggest it ought to work even though it failed to initialize after programming.

[loaded101]

Built the new .mcs and it does not work with Icarus. Currently trying it on the Lancelot to compare the log outputs.

>>>> Lancelot failed with the 3 core .mcs file, so I must be doing something wrong in the build process. Now retrying Lancelot with the older .mcs file which did work. I have noticed that trying to program my .mcs file (created with 1 bit selection) choosing 4 bit for lancelot generates a warning. However, using your file there is no warning - possible something to do with the missing .cfi file?

Contents of .cfi file:

# PROMGEN: Xilinx Prom Generator O.40d
# Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

SOFTWARE_VERSION O.40d
DATE            04/08/2014 - 18:14
SOURCE          C:\blake\blakeminer_FourGatexClk_3core_fmax-102.mcs
DEVICE          8192K
DATA_WIDTH      1
FILL_DATA       0xFF
SIGNATURE       0x45C1113A
START_ADDRESS   0x00000000 END_ADDRESS 0x00406533 DIRECTION_UP   "C:/blake/blakeminer_FourGatexClk_3core_fmax-102.bit" 6slx150fgg484


Tried power cycling after programming but it did not work.

It flagged the missing cfi file previously when I programmed Lancelot but it still worked.

[BlueDragon747]

Still failing on 1 bit - see pastebin for output.

http://pastebin.com/rQB8PYWm

I'm going to try using your instructions to convert the 3 core .bit file to a .mcs and see if this works.

Right click save as
http://blakecoin.org/blakeminer_FourGatexClk_3core_fmax-102.mcs

[kramble]

Right click save as
http://blakecoin.org/blakeminer_FourGatexClk_3core_fmax-102.mcs

Great, saves me uploading my mcs to dropbox (different PC, so involves a bit more effort).

I'm at a bit of a loss here as to what's going wrong. One thought was that the Icarus might need a slower configrate in the bitgen parameters, but that's just clutching at straws really. What do you make of the SPI configuration chapter in ug380?

Unfortunately I've just reorganised things in my "workshop" (aka bedroom), so my lancelot is now running standalone with the raspi and putting it back together for programming is going to be a bit of a pain. I'll have a look at it tomorrow (perhaps I'll try out the USB programmer instead of my parallel-port one).

PS

Tried power cycling after programming but it did not work.

Do you mean that the done LED's (white on lancelot, not sure what they are on icarus) failed to light?

[loaded101]

Just downloading ug380, will take a look.

Could either of you post the contents of your .cfi / .prm files so I can compare to the ones I am generating please?

[kramble]

Just downloading ug380, will take a look.

xapp586-spi-flash.pdf is useful too (google it, I won't copy the google link here). It's for Artix/Kinetix 7 but is pretty much the same as Spartan-6.

Could either of you post the contents of your .cfi / .prm files so I can compare to the ones I am generating please?

Will take a little while as I moved stuff and the PC needs reassembling.

[loaded101]

Looks like the pullup resistor on the Icarus CSO_B pin is there, it's just shown separately on the Icarus schematic - look down from U4, below RN3 there are 3 pullup resistors - the bottom one R25 connects to FPGA2_CS which is also connected to U4 pin 1.

[kramble]

CFI/PRM files for the two and three core bitstreams (no pastebin sorry so I've cat'd them together here)

Code:

# PROMGEN: Xilinx Prom Generator P.49d
# Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

SOFTWARE_VERSION P.49d
DATE            01/02/2014 - 14:05
SOURCE          C:\blakecoin\USETHIS_blakefourbufce-2core-ucf146-fmax154.mcs
DEVICE          8192K
DATA_WIDTH      1
FILL_DATA       0xFF
SIGNATURE       0x43FC3925
START_ADDRESS   0x00000000 END_ADDRESS 0x00406533 DIRECTION_UP   "C:/blakecoin/USETHIS_blakefourbufce-2core-ucf146-fmax154.bit" 6slx150fgg484

====== snip =========

PROMGEN: Xilinx Prom Generator P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

promgen -w -p mcs -c FF -o C:\blakecoin//USETHIS_blakefourbufce-2core-ucf146-fmax154.mcs -s 8192 -u 0000 C:/blakecoin/USETHIS_blakefourbufce-2core-ucf146-fmax154.bit -spi 

PROM C:\blakecoin\USETHIS_blakefourbufce-2core-ucf146-fmax154.prm map: Thu Jan 02 14:05:44 2014

Calculating PROM checksum with fill value ff

Format        Mcs86 (32-bit)
Size          8192K
PROM start    0000:0000
PROM end      007f:ffff
PROM checksum 43fc3925

        Addr1        Addr2                     Date File(s)
    0000:0000    0040:6533     Oct 27 12:01:13 2013 C:/blakecoin/USETHIS_blakefourbufce-2core-ucf146-fmax154.bit

====== snip =========

# PROMGEN: Xilinx Prom Generator P.49d
# Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

SOFTWARE_VERSION P.49d
DATE            04/07/2014 - 11:26
SOURCE          C:\blakecoin\Untitled.mcs
DEVICE          8192K
DATA_WIDTH      1
FILL_DATA       0xFF
SIGNATURE       0x45C1113A
START_ADDRESS   0x00000000 END_ADDRESS 0x00406533 DIRECTION_UP   "C:/blakecoin/blakeminer_FourGatexClk_3core_fmax-102.bit" 6slx150fgg484

====== snip =========

PROMGEN: Xilinx Prom Generator P.49d
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

promgen -w -p mcs -c FF -o C:\blakecoin//Untitled -s 8192 -u 0000 C:/blakecoin/blakeminer_FourGatexClk_3core_fmax-102.bit -spi 

PROM C:\blakecoin\Untitled.prm map: Mon Apr 07 11:26:34 2014

Calculating PROM checksum with fill value ff

Format        Mcs86 (32-bit)
Size          8192K
PROM start    0000:0000
PROM end      007f:ffff
PROM checksum 45c1113a

        Addr1        Addr2                     Date File(s)
    0000:0000    0040:6533     Apr 04 13:12:08 2014 C:/blakecoin/blakeminer_FourGatexClk_3core_fmax-102.bit

You're on an older software version O.40d while mine is P.49d (ISE 14.4). I don't know if that matters though.

[loaded101]

Success!

I rebuilt the .mcs file from scratch - tried it on Lancelot and it worked. Then tried it on Icarus (with 4 bit) still got the failed message as before but when I rebooted it worked!

I will now try it with Bluedragon's .mcs to see if this works.

I have ordered a 2mm header and will report back if this fits.

Thank you both for all your assistance.