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Author Topic: Butterfly Labs - Bitforce Single and Mini Rig Box  (Read 176581 times)
P_Shep
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June 07, 2012, 09:20:19 PM
 #1481


Yeah, I read that earlier. Fun and games!
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O_Shovah
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June 08, 2012, 06:54:18 AM
 #1482

Hello everybody.

As this thread features all BFL devices i wanted to spread some pictures of my recent developments here.
Nameingly i havedesigned and build water cooling blocks for the BFL single versions in for BFL.
But as this project has been agreed to be delayed to the next generation of boards for volume production, i wanted to show my prototypes here at least.
Some pixels:


My water cooled rig at work  2.4 Gh/s.


High density per heith.


Two of the prototype coolers coupled.

I created also coolers for the x6500 board and wil do so for the lancelot.

Questions, critique, and ideas are welcome Smiley

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June 08, 2012, 09:40:55 AM
 #1483

Very interesting, what's the possible price ?
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June 08, 2012, 12:44:06 PM
 #1484

What number of coupled units do you think will be the max before pressure issues abound?

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June 08, 2012, 01:14:42 PM
 #1485

Will you be selling the coolers, or at least licensing the design to BFL? They show them on their website, after all. I thought it was them that created them, but I guess it was you.

What are the approximate flow restriction and pressure numbers for each block? Does it work on an unmodified rev2 or rev3 single PCB?

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June 08, 2012, 03:46:34 PM
 #1486

Anyway, the change relates to 3 issues, the 3rd one I haven't confirmed if it fixes it yet or not.
1) BFL doesn't display an ERR (only a DEBUG message) if it fails to open a device (so you don't know unless you have debug on)


Here had a problem with scanhash() and disabling of BFL device.  Nothing to do with opening device.
LOG_ERR is used.

static uint64_t bitforce_scanhash(struct thr_info *thr, struct work *work, uint64_t __maybe_unused max_nonce)
{
   struct cgpu_info *bitforce = thr->cgpu;
   int fdDev = bitforce->device_fd;

   char pdevbuf[0x100];
   unsigned char ob[61] = ">>>>>>>>12345678901234567890123456789012123456789012>>>>>>>>";
   int i;
   char *pnoncebuf;
   char *s;
   uint32_t nonce;

   BFwrite(fdDev, "ZDX", 3);
   BFgets(pdevbuf, sizeof(pdevbuf), fdDev);
   if (unlikely(!pdevbuf[0])) {
      applog(LOG_ERR, "Error reading from BitForce (ZDX)");
      return 0;
   }
   if (unlikely(pdevbuf[0] != 'O' || pdevbuf[1] != 'K')) {
      applog(LOG_ERR, "BitForce ZDX reports: %s", pdevbuf);
      return 0;
   }

   memcpy(ob + 8, work->midstate, 32);
   memcpy(ob + 8 + 32, work->data + 64, 12);
   BFwrite(fdDev, ob, 60);
   if (opt_debug) {
      s = bin2hex(ob + 8, 44);
      applog(LOG_DEBUG, "BitForce block data: %s", s);
      free(s);
   }

   BFgets(pdevbuf, sizeof(pdevbuf), fdDev);
   if (unlikely(!pdevbuf[0])) {
      applog(LOG_ERR, "Error reading from BitForce (block data)");
      return 0;
   }
   if (unlikely(pdevbuf[0] != 'O' || pdevbuf[1] != 'K')) {
      applog(LOG_ERR, "BitForce block data reports: %s", pdevbuf);
      return 0;
   }

   BFwrite(fdDev, "ZLX", 3);
   BFgets(pdevbuf, sizeof(pdevbuf), fdDev);
   if (unlikely(!pdevbuf[0])) {
      applog(LOG_ERR, "Error reading from BitForce (ZKX)");
      return 0;
   }
   if ((!strncasecmp(pdevbuf, "TEMP", 4)) && (s = strchr(pdevbuf + 4, ':'))) {
      float temp = strtof(s + 1, NULL);
      if (temp > 0) {
         bitforce->temp = temp;
         if (temp > bitforce->cutofftemp) {
            applog(LOG_WARNING, "Hit thermal cutoff limit on %s %d, disabling!", bitforce->api->name, bitforce->device_id);
            bitforce->deven = DEV_RECOVER;

            bitforce->device_last_not_well = time(NULL);
            bitforce->device_not_well_reason = REASON_DEV_THERMAL_CUTOFF;
            bitforce->dev_thermal_cutoff_count++;
         }
      }
   }

   usleep(4500000);
   i = 4500;
   while (1) {
      BFwrite(fdDev, "ZFX", 3);
      BFgets(pdevbuf, sizeof(pdevbuf), fdDev);
      if (unlikely(!pdevbuf[0])) {
         applog(LOG_ERR, "Error reading from BitForce (ZFX)");
         return 0;
      }
      if (pdevbuf[0] != 'B')
          break;
      usleep(10000);
      i += 10;
   }
   applog(LOG_DEBUG, "BitForce waited %dms until %s\n", i, pdevbuf);
   work->blk.nonce = 0xffffffff;
   if (pdevbuf[2] == '-')
      return 0xffffffff;
   else if (strncasecmp(pdevbuf, "NONCE-FOUND", 11)) {
      applog(LOG_ERR, "BitForce result reports: %s", pdevbuf);
      return 0;
   }

   pnoncebuf = &pdevbuf[12];

   while (1) {
      hex2bin((void*)&nonce, pnoncebuf, 4);
#ifndef __BIG_ENDIAN__
      nonce = swab32(nonce);
#endif

      submit_nonce(thr, work, nonce);
      if (pnoncebuf[8] != ',')
         break;
      pnoncebuf += 9;
   }

   return 0xffffffff;
}


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June 08, 2012, 05:31:47 PM
 #1487

Very interesting, what's the possible price ?

We had targeted ~15-30$ for high numbers ( 1000pcs) but single parts will be more pricy.

If anyone is seriously interested i could produce them on my little milling mashine but thats gonna be a significant higher price.

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June 08, 2012, 05:33:26 PM
 #1488

What number of coupled units do you think will be the max before pressure issues abound?
I have tested the units up to 5 bar with no leaking. If big stackings were interesting for the customer the next gen would feature bigger pipelines.
Maybe  1/2" instead of 1/4".

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June 08, 2012, 05:43:55 PM
 #1489

Very interesting, what's the possible price ?

We had targeted ~15-30$ for high numbers ( 1000pcs) but single parts will be more pricy.

If anyone is seriously interested i could produce them on my little milling mashine but thats gonna be a significant higher price.


What price can be for 10 pcs?

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June 08, 2012, 05:48:59 PM
 #1490

Will you be selling the coolers, or at least licensing the design to BFL? They show them on their website, after all. I thought it was them that created them, but I guess it was you.

What are the approximate flow restriction and pressure numbers for each block? Does it work on an unmodified rev2 or rev3 single PCB?

I would do so but not before August (university  exams upcoming). The development was in cooperation with BFL i had the idea, did the design and produced the prototypes you see above.
And they wanted to sell them as a package to customers interested.
But due to the upcoming next gen with 1,4 gh/s the additional cooling became obsolete and we canceled the project.
Its intended for me to come back with the ASIC generation, as there overclocking by good temperatures becomes interesting again.

Maybe i also have to relativate the effect of the water cooling. On the upper board ( revision 01) i used just top cooling wich is just sufficient for keeping
the core at the temperatures it had with air cooling.
The lower one (revision 03) including two side cooling gave air cooling temps minus 8 °C and i have revised that design further to become better, but that is yet to be build( i have no additional bitforce singles Wink)

So rev 01 and rev 03 are avaidable out of the box for now.

I did no pressure delta measurements as they did not seem nessesary yet.

I can also do other custom designs if somebody is interested.
Did so for the x6500 and wil for the lancelot.

Edit:
The rev 03 single will need to have the front fan connector desoldered or cut off !!

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June 08, 2012, 05:54:32 PM
 #1491

Very interesting, what's the possible price ?

We had targeted ~15-30$ for high numbers ( 1000pcs) but single parts will be more pricy.

If anyone is seriously interested i could produce them on my little milling mashine but thats gonna be a significant higher price.


What price can be for 10 pcs?
Depends on your revision. It would take a few day to have serious number for the price.
And they will not be manufactured before august.

As price negotiation seems a bit offtopic here i would like to ask you to pm me so we can dicuss this further.

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June 08, 2012, 07:38:27 PM
 #1492

It looks like once again BFL lied about shipments going out.  No one has received any shipping confirmations.  I wonder what they would do if 200 or more single orders were canceled.
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June 08, 2012, 07:50:55 PM
 #1493

But due to the upcoming next gen with1,4 gh/s the additional cooling became obsolete and we canceled the project.
Its intended for me to come back with the ASIC generation, as there overclocking by good temperatures becomes interesting again.

Do we know more info about this? Is the ASIC the 4th gen, or is there another FPGA Single that's going to be faster before they release the ASIC?

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O_Shovah
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June 08, 2012, 07:53:22 PM
 #1494

But due to the upcoming next gen with1,4 gh/s the additional cooling became obsolete and we canceled the project.
Its intended for me to come back with the ASIC generation, as there overclocking by good temperatures becomes interesting again.

Do we know more info about this? Is the ASIC the 4th gen, or is there another FPGA Single that's going to be faster before they release the ASIC?
The Mini Rig contains an improved version of the  single.

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June 08, 2012, 07:57:40 PM
 #1495

But due to the upcoming next gen with1,4 gh/s the additional cooling became obsolete and we canceled the project.
Its intended for me to come back with the ASIC generation, as there overclocking by good temperatures becomes interesting again.

Do we know more info about this? Is the ASIC the 4th gen, or is there another FPGA Single that's going to be faster before they release the ASIC?
The Mini Rig contains an improved version of the  single.

17 cards at 1.5GH/s, right? Are these improved versions going to be in rev4 of the Single?

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rjk
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June 08, 2012, 08:11:49 PM
 #1496

17 cards at 1.5GH/s, right? Are these improved versions going to be in rev4 of the Single?
As far as I know, BFL doesn't plan to offer those cards as Singles.

Mining Rig Extraordinaire - the Trenton BPX6806 18-slot PCIe backplane [PICS] Dead project is dead, all hail the coming of the mighty ASIC!
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June 08, 2012, 08:16:48 PM
 #1497

17 cards at 1.5GH/s, right? Are these improved versions going to be in rev4 of the Single?
As far as I know, BFL doesn't plan to offer those cards as Singles.

Well they should... and in time for them to mail me mine, too! Tongue

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June 08, 2012, 08:18:12 PM
 #1498

"Please note:  Until we’re through initial Mini Rig shipments, you may find communications with anyone outside of customer service to be difficult.  Please be patient and reach out to Jody for the time being.  Announcements regarding abbreviated shipping schedules and future product (BitForce SC) release will be made on June 15th.  Until then we will be focusing purely on Mini Rig shipments."

http://www.butterflylabs.com/production-update/
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June 09, 2012, 12:47:35 AM
 #1499

Anyway, the change relates to 3 issues, the 3rd one I haven't confirmed if it fixes it yet or not.
1) BFL doesn't display an ERR (only a DEBUG message) if it fails to open a device (so you don't know unless you have debug on)


...

My change included modifying the initial detection so that both the Icarus and BFL code report the same.
i.e. attempt as DEBUG then failure as ERR
(P.S. there isn't much point posting that long code here)

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June 09, 2012, 03:48:33 AM
 #1500

Anyway, the change relates to 3 issues, the 3rd one I haven't confirmed if it fixes it yet or not.
1) BFL doesn't display an ERR (only a DEBUG message) if it fails to open a device (so you don't know unless you have debug on)


...

My change included modifying the initial detection so that both the Icarus and BFL code report the same.
i.e. attempt as DEBUG then failure as ERR
(P.S. there isn't much point posting that long code here)

Good for you  Wink
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