Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)

[kramble]

Hi, that's not the DE-115 or even other official dev board.

In may/june I was able to get 4 of these http://www.taylorkillian.com/2013/04/using-fpga-of-eecolor-color3.html for $15/each. I just had time to unpack them, 3 weeks ago, then I ordered two cables (form different ebayers to avoid a problematic batch)..

OK, I was just confused by the DE2_115_50MHash_20110601a.sof in your earlier post. Looking closer I can see its detected a EP3C40/EP4CE(30|40) which makes sense for that board (strangely enough I was reading that very article just yesterday!)

Its strange as quartus_stp is clearly reading the device ID off the scan chain, but not managing to successfully complete the programming. Perhaps its a noise or voltage level problem with the jtag header? I can see you've posted on Taylor Killian's blog, so meybe you'll get some help there.

[1713238478]

1713238478

[vpereira]

yes, I've got little confused. because the boards arrived without power source. I just read under the eecolor, that it requires 1A, 5V. I just got one with the same voltage and current. But reading the documentation, I've got the impression that it actually needs a 3.3V.. then it would explain this unexpected behavior. I would like to let it mine some other altcoin, like namecoins..

[kramble]

yes, I've got little confused. because the boards arrived without power source. I just read under the eecolor, that it requires 1A, 5V. I just got one with the same voltage and current. But reading the documentation, I've got the impression that it actually needs a 3.3V.. then it would explain this unexpected behavior. I would like to let it mine some other altcoin, like namecoins..

This comment seems to suggest 5V (why would there be a 5V label on a board if it's PSU is only 3.3V?), but you're probably best waiting for a response from someone on the blog. The only other thing I can think of is multiple devices in the scan chain, but you say it programs OK from within Quartus, so that rules it out. Or maybe the linux drivers are buggy, can you try on a windows box? Anyway grasping at straws here, hope you get it working.

Shameless plug, you could mine litecoin at around 1kHash/sec https://github.com/kramble/FPGA-Litecoin-Miner 

[vpereira]

haha actually pretty awesome that you managed to push scrypt to FPGA.. this line really caught my eyes "A Xilinx LX150 port for ngzhang's Icarus board is in development"

Windows is not discarded, but the logistic is hard (full disclosure: ask my wife to use her laptop, will end up in endless inquisition) but possible.

btw, I'm able to program it with Quartus, but I must after every action, to remove and insert back the usb cable. Like if I call two times jtagconfig, I get an answer but after that, a next jtagconfig will fail. To compile my code on Quartus. I must first search for a device, remove and insert USB and then ask to program the device.. then it works. With the test chain option happens the same..  anyway related to scrypt I sent you a PM that maybe would be great

[kramble]

haha actually pretty awesome that you managed to push scrypt to FPGA.. this line really caught my eyes "A Xilinx LX150 port for ngzhang's Icarus board is in development"

Don't get too excited, its just a toy implementation really. I reckon for around 10kHash/sec on an LX150 (possibly a bit more once I get the salsa-mix properly pipelined and I can get the clock speed up a bit).

[vpereira]

sure, but it goes in the right direction

[kramble]

Hi I've got a board with Altera  EP4CE40F23I7N, so 40K LE. With CONFIG_LOOP_LOG2 = 3, I was able to compile the code. But I see that there is a lot of free LE. It is just being used 61% of all LE. based on that scenario I have 3 questions:

1) How can I simulate/calculate how many mh/s does this boad?
2) I have to set the correct to PIN to my board. The vendor gave me a PIN table and I have to ajust the clock PIN. looking to the table, It looks to be the PIN under CLK_INPUT more specifically the  50M   PIN_AB11. Does it make sense? I've got this 50M to believe that it is a 50MHZ..
3) What should I look into to try to optimize the code? My goal would be to be able to compile with CONFIG_LOOP_LOG2 = 2 and be able to fit my code into the board..

thank you, awesome stuff

In case you're still looking for answers on this, I found Makomk's code (on his git repository, not fpgaminer's) to perform best on my DE0-Nano (EP4CE22 - 22K LE), I'm getting 35MHash/sec at 140MHz (it needs a PSU hack else you'll fry the board). My code is here with links to Makomk's original github (don't use mine as it uses a serial comms driver for my Raspberry PI GPIOs instead of the default JTAG one). You may be able to tweak CONFIG_LOOP_LOG2 to fit a larger core on, or perhaps multicore with a second smaller one.

[vpereira]

It's running and giving me 20 MH/s... I wanted to play with that, I did some optimization hinted by Quantus, but well it's mining

[_dex_]

Hello to all,

Just few questions...
Is there somebody with experience on spartan 6? How much dissipation is allowed with heat-sink and cooler?
Is there some hidden - non documented SYSMON on spartan 6 or any way to read temperature of substrate?  

B.R.
Dex

[BTC-engineer]

In the current Xilinx Xcell Journal: Issue 84 is an article about "Efficient Bitcoin Miner System Implemented on Zynq SoC" which is also mentioning this project.

The magazin can be downloaded here:
http://www.xilinx.com/publications/archives/xcell/Xcell84.pdf

[goxed]

In the current Xilinx Xcell Journal: Issue 84 is an article about "Efficient Bitcoin Miner System Implemented on Zynq SoC" which is also mentioning this project.

The magazin can be downloaded here:
http://www.xilinx.com/publications/archives/xcell/Xcell84.pdf

2 students + 2 professor to port already available code

[asjfdlksfd]

In the current Xilinx Xcell Journal: Issue 84 is an article about "Efficient Bitcoin Miner System Implemented on Zynq SoC" which is also mentioning this project.

The magazin can be downloaded here:
http://www.xilinx.com/publications/archives/xcell/Xcell84.pdf

I read them, but I didn't really can find any rates for comparing.
Does anybody knows rate and power calculations?

Cheers...

[kramble]

http://www.xilinx.com/publications/archives/xcell/Xcell84.pdf

I read them, but I didn't really can find any rates for comparing.
Does anybody knows rate and power calculations?

They didn't give them. Its a student project, and to give credit its a fair analysis and implementation, but useless for mining bitcoins. They did not specify which Spartan-6 development platform they were using (but it certainly wasn't an LX150), and their results were fairly pathetic (3.8MHash/sec, I've done better on an LX9!!). They then went on to try multiple cores (bitfury might be flattered, but its not the approach taken by our commercial LX150 mining boards), and finally a port to the Zedboard, which with 85KLE should have given them a performance in the 100s of MHash/sec, if they did it properly. But rather than giving the performance figures they rabbited on about the Cortex A9 cores and embedded linux.

TL;DR just ignore it. They did a bitcoin miner on a Zedboard. Good for them (nice student project). If you happen to have one lying around then you may want to repeat their work and port the open source miner, but don't expect much return. Or if you want a real challenge, write a scrypt litecoin miner. I've got some code on my github to start you off (shameless plug), then you might look at utilizing the board's SDRAM for additional performance.

PS For some unfathomable reason they decided to run bincoind on their Zedboard A9 linux cores (ie solo mining, WTF???). Maybe so they could back their claim of an "efficient and complete Bitcoin mining system", well IMHO its neither efficient nor complete (OK, no need for a pool if solo mining, but they are never going to mine a block). Who are they kidding (other than their professors )?

[kingcoin]

Seems like it was more an exercise in HLS rather than creating a more optimal implementation.

[kramble]

Seems like it was more an exercise in HLS rather than creating a more optimal implementation.

High Level Synthesis? I had to look the acronym up, I rather liked Hysterical Laughter Syndrome myself

I probably came over too critical. Its a student project after all, so I shouldn't be too hard on them. The entire issue of the magazine was pretty much devoted to the Zedboard (it is a Xlinx in house publication), and it takes more than just the mining core get get a working system running on one of those. Anyway I'm going to look up some more issues of the mag, should be some nice reading material to keep me occupied.

[kingcoin]

High Level Synthesis? I had to look the acronym up, I rather liked Hysterical Laughter Syndrome myself

Yes. The code shown in the table uses C syntax. Not being a fan of C based synthesis I liked your definition better too 

[kingcoin]

Did the student project include networking SW for mining on the embedded ARM CPU?

[kramble]

Did the student project include networking SW for mining on the embedded ARM CPU?

They solo mined using bitcoind ...

Testing Bitcoind was a simple matter. We ran the daemon, waited for the sizable block chain to download and then used the line command to start Bitcoind’s built-in CPU mining software
...
The final component of our system is a small relay program to pass work from Bitcoind to the mining core through the driver, and return results

As I said earlier, student project showing off the features of the zedboard. Not really relevant to actually using it for real mining.

PS Terasic/Arrow/Rocket's new SoCKit board looks to be a very interesting competitor to the zedboard. Altera Cyclone V 85kLE plus dual core A9. $249  

[kingcoin]

OK. Thanks. So they just wrote a small driver then. Did anybody port bfgminer or similar to Zync or Altera SoC? I know it has been done for the RPi, but it would be fun to try to use the low latency FPGA fabric to ARM interconnect.

[kramble]

OK. Thanks. So they just wrote a small driver then. Did anybody port bfgminer or similar to Zync or Altera SoC? I know it has been done for the RPi, but it would be fun to try to use the low latency FPGA fabric to ARM interconnect.

I guess it should be easy enough (having absolutely no experience with the FPGA/SoC combination myself so just guessing), its just linux running on ARM. The difficult part is the drivers since much of the peripherals will be implemented in or via the FPGA, but there must be demo code written.

Fun to use the low latency path, irrelevant to mining though (my "low latency" path from my RPi to my DE0-Nano runs at 4800 baud! I get the occasional collision (I've got four devices sharing the same serial port wire-or style), but hardly enough to worry about).