With (fully custom) ASICs, however, you can just match your exact routing needs with wires, which should take care of the routing problems.
I'm certainly not an expert on that area, but I'd expect the overhead of intermediate result storage (in a rolled design) to outweigh the routing overhead (in an unrolled deisn).
As I stated above already a rolled design might still be useful to increase yield by containing defects into smaller functional units.

The new build works well, thanks! What was the issue?

Side note: I can now use a worksize of either 128 or 256 on OS X 10.7.4 and notice a small increase in hashrate over -w 64. May be worth mentioning in the OP instructions. I assume it's because of (one of?) the OpenCL updates Apple has pushed out.

For what it's worth -- when I look at a mining company to invest in one of the big things is how they use the capital they already have and the capital they have raised. Of course a startup like DMC is different, but if a mining company with existing hashpower issues funds and ends up buying and holding assets of another miner over a long term basis, while this does in fact reduce risk it lowers the return on capital because the miner is paying another miner to mine and that second miner has to be profitable before paying out.

So what I like to see in a miner is that they use the capital they are given to do what they said they would do. Now, if someone has 100 bitcoins left over from buying a single, no one said they have to let the shares sit there. But it's a little alarming to see mining companies buying up shares of each other and then using that income to pay dividends on existing shares. In that case, what about buying back the shares so the existing shares are backed entirely by the GHash of the farm?

Doing that is what I would consider as the natural course of operation for any miner issuing shares for expansion.

Not trying to tell anyone what to do just giving a suggestion.

Give me some ideas. 

Investing the funds back in your CD is a bit incestuous too!  Kluge invests in Cognitive. Cognitive invests in Kluge.

In case anyone misunderstands, I'm just stirring.  A lot of big listed companies have cross holdings. I'm not currently a Cognitive investor, but I think BDK is as good a place as any for funds not immediately required.

I'm asking because I'm not fully up-to-speed on possible space-time tradeoffs on the current Xilinx platforms. When I worked on them professionally we had the information about the routing and bitstream format available directly from Xilinx (maybe under NDA, I'm not sure, it was years ago).

I've also remember the comments from a poster who implemented the bitcoin hashers on Virtex-6 and quick-and-dirty solution was to use DSP48s for some fraction of the adders in SHA-256 mixing steps.

In theory at least it should be possible to fill every BRAM with multiple copies of the constants and use those constants at least in those hashing cells that are close to the BRAMs. As far as I understand your design you currently have just one class/macro of hashing cell, but have plans on implementing another class/macro to fill out the space that currently remains unused.

Overall, I'll venture to guess that the ultimate Spartan-6 bitstream will use the sea-of-hashers concept and the hashers will be a heterogenous mixture: close-to-DSP48, close-to-BRAM and far-from-DSP-and-BRAM. I occasionally talk to my friends who do digital design and they always mention "don't leave any FPGA resource unused, even at the expense of partially mangling the original algorithm".

I guess the ultimate way to express all the above is that the design space tradeoffs are multidimensional space of clock-freq*number-of-gates*time-to-market.

Finally I would say that implementing FPGA design mostly about placement and routing... Do not even start trying it, if you are not prepared to waste weeks figuring all of that things, or use only simple designs, when you have about clocks 2-3 times smaller than chip's maximums... designs @ 50 - 100 Mhz would be easy....

In a completely unrolled design, there are no long lines.
The start vector is fed in on the left side, then the calculations percolate down to the right, and at the right a "matching" circuit determines if a "golden nonce" was found. There is no feedback from the right side to the left side.
Thus, while I do think that Bitfury's approach is EASIER (as one only has to worry about a few hundred wires and their associated delays, and not tens of thousands), I fail to see why it is inherently faster. I don't think it is inherently faster.
Maybe the Xilinx router goofs up wires that would be short and local and sends them the long way like a crooked cab driver an out-of-town tourist. But, to reiterate, a fully unrolled miner does not involve a feedback from the right side to the left side.

For me it is now double spacing instead of triple spacing.

That is already "subtracted" from the results, and apparently both the MH/s and MH/J are still better for the rolled version. This is most likely due to the Spartan6's awful long distance routing fabric, which means that keeping things very close to each other pays off (which is one reason why 85 small, 64-clocks-per-hash cores together are faster than just three 2-clocks-per-hash cores, you can just clock them at much higher frequencies, and you can utilize more area on the chip).

I agree with a modular design that can be sold and then upgraded or added to. The $15,000 BFL entry point is just focking stupid and actually it's bullshit because it kills the democratic/decentralized component of mining. You are now completely pushing out small scale miners and any form of ingenuity. This $15,000 bullshit is just a money box and will be worth .50 if bitcoin goes to shit. It's the nuclear weapon of bitcoin, once it exists you just up the ante too much and screw everyone who can't afford one.

If you guys can produce a 4-5 Gh/s base product which could be upgraded to 20-25 with additional modules added to the unit over time that would be ideal.

Please beat out BFL so we can piss on their poor business practices and customer service.  Mining is speculative enough without being forced to put out your money for months in advance and then still get delayed.

Is BFL obsolete already ?

Achronix was founded in 2004 by researchers at Cornell University who wanted to push the performance limits of FPGAs and change this estimated $3bn market, challenging the market leaders Xilinx and Altera.

FPGAs are, as the name suggests, malleable and can be rejiggered to change their basic functions in ways that an ASIC cannot. It might take $30m or $40m to develop an ASIC to do a particular job — say, support the Ethernet or InfiniBand protocols — and if you make a mistake, you cannot erase and go back.

For very high volume products — with hundreds of thousands to millions of units where the cost per unit has to be low — you want an ASIC. But in places where you need a chip that might only require thousands to tens of thousands of units to satisfy an entire market, an FPGA, while more expensive to buy, is better because it is less expensive to make and is correctable in a way that an ASIC is not.

According to Greg Martin, a spokesman for the FPGA maker, Achronix can compete with Xilinx and Altera because it has, at 1.5GHz in its current Speedster1 line, the fastest such chips on the market. And by moving to Intel's 22nm technology, the company could have ramped up the clock speed to 3GHz.

By the way, the goal is to bring the cost of that 1 million LUT FPGA down to around $400 a pop when they start shipping in the fourth quarter of 2011. FPGAs sell for $1,000 and higher today, depending on features.