Klondike - 16 chip ASIC Open Source Board - Preliminary

[sensei]

I Know we want to keep the parts count low, but I like indicators.

A green LED to show power and a blue LED to show operation, controlled by the PIC? I don't know what the resource map of the PIC looks like. Maybe there isn't a port available.

Do we need a momentary switch for resetting the board?

[1714042053]

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[1714042053]

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[BkkCoins]

I Know we want to keep the parts count low, but I like indicators.

A green LED to show power and a blue LED to show operation, controlled by the PIC? I don't know what the resource map of the PIC looks like. Maybe there isn't a port available.

Do we need a momentary switch for resetting the board?

I haven't allocated any pins to indicators yet as I'm waiting for ASIC docs. Once I really know what will be needed there I'll see if there is a pin or two left over. Same with an external temp sensor, though I'd probably assign that before indicators. There could be enough for both. Right now I have 9 pins available and I'm expecting to use 4 for the ASICs.

[BkkCoins]

What are your thoughts regarding powering the bricks? One big PSU or individual ones for each klego (pain to power up...)?

A K16 will use around 32W, so a K64 will need about 128W each (with 4 leads). They're designed to take a PCIe 6 pin connector much like a GPU. I would guess that you could run a K64 off each PCIe lead from the PSU with splitters to feed each of the 4 sections. I haven't gone to check the specs but they would  handle something like that. I wouldn't have a problem running 4x K64 off my 600W supply. I used to run 3 GPUs at 500W without any issues. I'd say you're better off going that route than using crappy low wattage power adapters for each board, or section of board.  Like with GPUs  stick with solid reliable PSU units like Corsair, preferably high efficiency Gold (90%) rated.

[sensei]

You can also get adapters for about $1 a piece.

The right angle 6-pin molex comes in a bit cheaper, part number 1586041-6.

[h4r13q1n]

monitoring this thread.

[KS]

What are your thoughts regarding powering the bricks? One big PSU or individual ones for each klego (pain to power up...)?

stick with solid reliable PSU units like Corsair, preferably high efficiency Gold (90%) rated.

I'm toying with the Enermax Platimax series right now. 1500W of 95% efficiency just arrived from Amazon. Plenty of PCI-E connectors (and a "free fan inside"!). Probably overkill

[kostagr33k]

Out of curiosity BKK did you see this?

https://bitcointalk.org/index.php?topic=197675.0


Curious if any of that makes sense to you as I am no EE by any means ;p


kosta

[ektwr]

Can i put this project to my site as review article?

[Ente]

Out of curiosity BKK did you see this?

https://bitcointalk.org/index.php?topic=197675.0

Curious if any of that makes sense to you as I am no EE by any means ;p

kosta

What exactly is there to see?

Ente

[flyonwall]

Hi BkkCoin,

As I mentioned in my previous posts here, I have been thinking about the serial ports on the Avalon chips. I am not too sure whether the microcontroller you chose can handle the communication bandwidth with all 16 chips on-board. The two serial ports maybe very high-speed asynchronous serial ports, and could be interrupting the microcontroller very often. Even assuming that each chip is handed 134,217,727 nonces to work on  (max 2,147,483,647 nonces divided by 16), the microcontroller would still have to handle at least (282 / 134) * 16 = 32 interrupts per second. In reality, we can assume that each board would be mining in the context of a pool, and work is given to each chip in much smaller increments, which means  interrupts can occur much more often than 32 a second. This is most probably why ngzhang used a Spartan-6 FPGA in the Control Unit. I am not saying your design won't work, it should work but the microcontroller will be a bottleneck.

Your PSU sounds good to me, and so I have decided to use the same regulator products as you have chosen.

[BkkCoins]

You can also get adapters for about $1 a piece.

The right angle 6-pin molex comes in a bit cheaper, part number 1586041-6.

You have to be very careful with the PCIe connector sourcing. It is not a standard MiniFit/MicroFit/ValuLok connector. That one you specify above will not work (check the drawing).

The standard connectors have a spacing of 4.2mm x 5.5mm, non square arrangement of pins, both in connector and on board. The proper correct PCIe connector has a square arrangement of 4.2mm both in connector and on board.

Correct part#s are Molex 45718-0002 for RA and 45558-0003 for straight.

I'd be very interested if anyone locates any Asian second source for these as 4UCON does not ahve them listed and they would be my goto for connector clones.

[BkkCoins]

Hi BkkCoin,

As I mentioned in my previous posts here, I have been thinking about the serial ports on the Avalon chips. I am not too sure whether the microcontroller you chose can handle the communication bandwidth with all 16 chips on-board. The two serial ports maybe very high-speed asynchronous serial ports, and could be interrupting the microcontroller very often. Even assuming that each chip is handed 134,217,727 nonces to work on  (max 2,147,483,647 nonces divided by 16), the microcontroller would still have to handle at least (282 / 134) * 16 = 32 interrupts per second. In reality, we can assume that each board would be mining in the context of a pool, and work is given to each chip in much smaller increments, which means  interrupts can occur much more often than 32 a second. This is most probably why ngzhang used a Spartan-6 FPGA in the Control Unit. I am not saying your design won't work, it should work but the microcontroller will be a bottleneck.

Your PSU sounds good to me, and so I have decided to use the same regulator products as you have chosen.

This isn't a problem as you have a wrong idea of how it processes work items. The chip is given a starting nonce and increments once per clock cycle from there. So you only assign new work once per nonce. The Avalon sends a start sequence to all ten chips per board as a long serial stream of 320 bits once per work item, and the chips clock this up. This takes 2^32 / 282x10^6 / 16 seconds to complete in chip before another work item is sent, ie 0.951 seconds. The bandwidth is very low and why I2C works well for passing work items on to multiple boards.

The interesting thing is that the hash engine doesn't even know when to stop. It will continue hashing right into each others range if let alone. So the PIC needs to know when it has completed work based on time and send the next work unit to keep it on valid work.

[fasmax]

flyonwall
What if you broadcast the work to all ASIC at the same time.
It the an ASIC finds a solution of sufficient difficulty then it sends it back.
So you would broadcast the to the ASIC.
Set a timer wait for about .5 seconds if you don't hear back send more work.

[SebastianJu]

BkkCoins... can you tell how error-resistent your design is? Burnin claimed that the chips will be working in a row. So if one chip breaks all chips stop working. Im not seeing why it should be built this way but i would like to know how your design is working. Is it the same way? And if so can a broken asic be replaced easily or are all the chips on that pcb gone then?

And you new pricelist with the parts... do one only need this kit and an old mini-oven to build a miner out of it or is there more needed?

[ecliptic]

Is the DC Input fused?

[BkkCoins]

Out of curiosity BKK did you see this?

https://bitcointalk.org/index.php?topic=197675.0

Curious if any of that makes sense to you as I am no EE by any means ;p

kosta

What exactly is there to see?

Ente

I was wondering the same. But that is the most curious arrangement of fans I've ever seen. Even a bit idiotic, but presumably (?) they have it working.

[BkkCoins]

BkkCoins... can you tell how error-resistent your design is? Burnin claimed that the chips will be working in a row. So if one chip breaks all chips stop working. Im not seeing why it should be built this way but i would like to know how your design is working. Is it the same way? And if so can a broken asic be replaced easily or are all the chips on that pcb gone then?

And you new pricelist with the parts... do one only need this kit and an old mini-oven to build a miner out of it or is there more needed?

Every design will have to accommodate the way the ASIC was designed to work.

Best knowledge right now is that the chips are arranged as a daisy chain so that data shifted in one end passes thru chips to fill a counter register in each. This is how the Icarus was done. In this case if the shift path is damaged in one chip all chips after it will be hashing wrong values. But a chip could be damaged in a way that affects it's hashing but not it's shifting, and this wouldn't affect other chips.

There is mitigation for this which I'll consider once official docs are out. If enough pins are free on the PIC then multiple serial lines from the PIC to the chips would allow nonce assignment in units smaller than 16 chips. eg. 4 serials going to 4 chips that daisy chain as a group of 4. But this is impacted by whether or not there are two serials per chip. I'm guessing not. I think there is an enable per chip that allows stopping nonce count while shifting in new data - just a guess. The Icarus didn't do that, it just counted while shifting and ignored bad results until the LSB was shifted and correct then the count was valid.

It should be fairly easy to replace an ASIC if you keep some spares. Repair shops can pull a chip and place a new one easily, and with a bit of practice on dummy chips you could likely do it too if you were inclined to that. At least you don't have to re-ball the chip as it's QFN. See youtube videos, search "qfn chip replacement".

Board, parts, oven (preferably with temp profile controller), skill, solder paste, stencil, technical aptitude, skill, some inspection magnifier probably, tweezers (preferably vacuum), dexterity with tiny parts (0402 caps are the size of a grain of rice), soldering iron for fixes and thru-hole pins. Maybe I've forgotten something, but otherwise that's it.

Is the DC Input fused?

That's good idea I hadn't thought about yet. I'll have a look at suitable parts and include one, preferably resettable. I would think a good PSU would have this covered but better to not rely on that.

[BkkCoins]

Can i put this project to my site as review article?

Not sure what that is. It may be better to wait until a working unit exists. Unless you sometimes review development ideas instead of products, but even then maybe a board would be nice to point at.

If Kicad had half decent 3D preview then I'd love to post a visual mock up, but it just spits out a 3D board with only one chip rendered. Anyone here good with 3D stuff? Apparently it uses some kind of 3D model called Wings3D but I haven't had time to look into making models for the parts I use.

http://happyrobotlabs.com/posts/tutorials/tutorial-3d-kicad-parts-using-openscad-and-wings3d/

[SebastianJu]

BkkCoins... can you tell how error-resistent your design is? Burnin claimed that the chips will be working in a row. So if one chip breaks all chips stop working. Im not seeing why it should be built this way but i would like to know how your design is working. Is it the same way? And if so can a broken asic be replaced easily or are all the chips on that pcb gone then?

And you new pricelist with the parts... do one only need this kit and an old mini-oven to build a miner out of it or is there more needed?

Every design will have to accommodate the way the ASIC was designed to work.

Best knowledge right now is that the chips are arranged as a daisy chain so that data shifted in one end passes thru chips to fill a counter register in each. This is how the Icarus was done. In this case if the shift path is damaged in one chip all chips after it will be hashing wrong values. But a chip could be damaged in a way that affects it's hashing but not it's shifting, and this wouldn't affect other chips.

There is mitigation for this which I'll consider once official docs are out. If enough pins are free on the PIC then multiple serial lines from the PIC to the chips would allow nonce assignment in units smaller than 16 chips. eg. 4 serials going to 4 chips that daisy chain as a group of 4. But this is impacted by whether or not there are two serials per chip. I'm guessing not. I think there is an enable per chip that allows stopping nonce count while shifting in new data - just a guess. The Icarus didn't do that, it just counted while shifting and ignored bad results until the LSB was shifted and correct then the count was valid.

It should be fairly easy to replace an ASIC if you keep some spares. Repair shops can pull a chip and place a new one easily, and with a bit of practice on dummy chips you could likely do it too if you were inclined to that. At least you don't have to re-ball the chip as it's QFN. See youtube videos, search "qfn chip replacement".

Board, parts, oven (preferably with temp profile controller), skill, solder paste, stencil, technical aptitude, skill, some inspection magnifier probably, tweezers (preferably vacuum), dexterity with tiny parts (0402 caps are the size of a grain of rice), soldering iron for fixes and thru-hole pins. Maybe I've forgotten something, but otherwise that's it.

Is the DC Input fused?

That's good idea I hadn't thought about yet. I'll have a look at suitable parts and include one, preferably resettable. I would think a good PSU would have this covered but better to not rely on that.

Sounds good with the chips and errors. I already thought that its better to go with smaller pcbs. But if a broken asic can be replaced easily thats not an issue.

I like the list of needed things because it seems i could manage this. The oven looks like the most big/complicated thing in the list once you have the parts ready. I need to check if i still have an old one. otherwise i have to buy one. At least im confident now that i can do this.

[flyonwall]

Hi BkkCoin,

As I mentioned in my previous posts here, I have been thinking about the serial ports on the Avalon chips. I am not too sure whether the microcontroller you chose can handle the communication bandwidth with all 16 chips on-board. The two serial ports maybe very high-speed asynchronous serial ports, and could be interrupting the microcontroller very often. Even assuming that each chip is handed 134,217,727 nonces to work on  (max 2,147,483,647 nonces divided by 16), the microcontroller would still have to handle at least (282 / 134) * 16 = 32 interrupts per second. In reality, we can assume that each board would be mining in the context of a pool, and work is given to each chip in much smaller increments, which means  interrupts can occur much more often than 32 a second. This is most probably why ngzhang used a Spartan-6 FPGA in the Control Unit. I am not saying your design won't work, it should work but the microcontroller will be a bottleneck.

Your PSU sounds good to me, and so I have decided to use the same regulator products as you have chosen.

This isn't a problem as you have a wrong idea of how it processes work items. The chip is given a starting nonce and increments once per clock cycle from there. So you only assign new work once per nonce. The Avalon sends a start sequence to all ten chips per board as a long serial stream of 320 bits once per work item, and the chips clock this up. This takes 2^32 / 282x10^6 / 16 seconds to complete in chip before another work item is sent, ie 0.951 seconds. The bandwidth is very low and why I2C works well for passing work items on to multiple boards.

The interesting thing is that the hash engine doesn't even know when to stop. It will continue hashing right into each others range if let alone. So the PIC needs to know when it has completed work based on time and send the next work unit to keep it on valid work.

Thanks Bkk. I don't think we disagree on how it works. Each chip needs only a message to get started for every work item. Each work item can be several nonces, maybe millions of nonces, right? The things is, the less work you give to each chip, the faster it gets done. Each chip does not have to report the hashes it completes (unless it satisfies the current difficulty), yes, but still, the PIC has to send at least the start message (and you're right, maybe there's only one start message for all chips). The point still is that it's the PICs responsibility to keep the chips all busy. Why would ngzhang choose a Spartan-6 for this job? (This part is probably the most expensive part in the Avalon system: at least it's more expensive than each of the ASICs.)