X6500 Custom FPGA Miner

[99Percent]

That looks really nice!

We would need to know if the mounting holes (if any) will fit any coolers in order to decide whether to order these sans heat sinks.

BTW, I am now sure my heat sinks are mounted correctly on my two x6500 but I am still getting >2% invalids on one of the FPGAs, curiously only on one of each board the one assigned 0, the other one is almost nil of invalids. Would this be a miner issue, or maybe power is not arriving evenly to both the FPGAs? The overall % of invalids averages to 1.5%

[nbtcminer]

@Fizzisist:

Now I know you have to be cost efficient with your heatsink options but have you ever considered using any of the Alpha heatsink models? I remember using Alpha heatinks way back in the day and they were pretty darn awesome (fully copper). They now sell a pretty decent line of chipset coolers which might be worth looking at:

https://www.micforg.co.jp/cgi-local/an/wse4.cgi?webpage=cat_cse.html

[fizzisist]

We would need to know if the mounting holes (if any) will fit any coolers in order to decide whether to order these sans heat sinks.

The new board has mounting holes which should be compatible with any Northbridge heatsinks. There are two 3 mm diameter holes placed on a 59 mm diagonal. These are usually used with "pushpins." At first glance at least, it looks like all of the heatsinks on this page are compatible: http://www.frozencpu.com/cat/l3/g40/c16/s500/list/p1/Air_Cooling-Chipset_HeatsinksCoolers-Northbridge-Page1.html

nbtcminer, Alpha looks like a good company, I'll look around there. Thanks.

[fizzisist]

I am now sure my heat sinks are mounted correctly on my two x6500 but I am still getting >2% invalids on one of the FPGAs, curiously only on one of each board the one assigned 0, the other one is almost nil of invalids. Would this be a miner issue, or maybe power is not arriving evenly to both the FPGAs? The overall % of invalids averages to 1.5%

That seems really strange, especially that both boards are exhibiting the same behavior. I never saw an inclination for one FPGA to have more invalids than the other in my tests. It's not clear in your pictures, is the fan moving less air over FPGA 0? That is the one on the left when the USB connector is pointing at you. If so, you might want to try a 92 mm fan to get a little more coverage. By the way, those new mounting holes at the bottom left and right corners on rev. 3 are spaced perfectly for a 92 mm fan.

[99Percent]

Seems like the fans are doing a good job but I will take a closer look. How do Identify which is FPGA is which on the board? The heat sinks don't feel warm at all. Could it require cooling from underneath the board?

I will probably order my next x6500 without heatsinks since I will try to find my own cooling solution.

[shad]

there is a text printed on the board

[fizzisist]

Yep, it says on the board, next to the FPGAs. I really don't know what's going on here. It seems to me that your fan setup is good, and you say the heatsinks are on good. Airflow on the bottom of the board would be good, but I think you have plenty of air. Does the PCB itself feel warm? That would be an indication that either your heatsink isn't on right (the heat is going into the PCB instead of the heatsink) or you should think about getting airflow on the PCB itself. If that feels cool, too, then something else is going on. Do you get invalids when running at 180 MHz?

[fizzisist]

Spent a little time drawing some components:



I'll do a little more work on this, then post the Sketchup file so that anyone can play around with it. I imagine it would be helpful when designing an enclosure or heatsink or whatever.

[nbtcminer]

@Fizzisist:

This is kind of a minor thing, but would it be possible to move the USB connector to the same side as the barrel / molex connector? That would make it much easier for enclosure /air flow designs.

[TheSeven]

I am now sure my heat sinks are mounted correctly on my two x6500 but I am still getting >2% invalids on one of the FPGAs, curiously only on one of each board the one assigned 0, the other one is almost nil of invalids. Would this be a miner issue, or maybe power is not arriving evenly to both the FPGAs? The overall % of invalids averages to 1.5%

That seems really strange, especially that both boards are exhibiting the same behavior. I never saw an inclination for one FPGA to have more invalids than the other in my tests. It's not clear in your pictures, is the fan moving less air over FPGA 0? That is the one on the left when the USB connector is pointing at you. If so, you might want to try a 92 mm fan to get a little more coverage. By the way, those new mounting holes at the bottom left and right corners on rev. 3 are spaced perfectly for a 92 mm fan.

I noticed something similar as well while testing MPBM on the cluster. On most boards, there were no invalids at all while the ambient temperature was rather low, except for two boards. On one of them, FPGA0 got like 2% stales while FPGA1 didn't have any, and on the other one it was like 0.5% on FPGA0 and zero on FPGA1. As ambient temperatures increased all boards produced invalids at some point, but this seemed to be biased towards the FPGA0 side as well. FPGA0 on that "misbehaving" board was at like 5% invalid at that point, most other FPGAs still <1%.
No idea what exactly is going on here, but it indeed seems like there's something different between the two FPGAs, either with power supply, cooling or signal routing.
I think I can definitely rule out that this is a miner issue, as both FPGAs use exactly the same code base in MPBM. However it might still be interesting whether this happens with x6500miner as well, as this might be somehow related to communication behavior, so different software might be affected to different degrees.

@Fizzisist:

Now I know you have to be cost efficient with your heatsink options but have you ever considered using any of the Alpha heatsink models? I remember using Alpha heatinks way back in the day and they were pretty darn awesome (fully copper). They now sell a pretty decent line of chipset coolers which might be worth looking at:

https://www.micforg.co.jp/cgi-local/an/wse4.cgi?webpage=cat_cse.html

Oh noes! The current heatsink looks way better
But seriously, I don't think using better heatsinks will help much here. The real bottleneck is the thermal bridge between the FPGA's die and the heatsink, which is obstructed by that nasty plastic package.

[fizzisist]

I noticed something similar as well while testing MPBM on the cluster. On most boards, there were no invalids at all while the ambient temperature was rather low, except for two boards. On one of them, FPGA0 got like 2% stales while FPGA1 didn't have any, and on the other one it was like 0.5% on FPGA0 and zero on FPGA1. As ambient temperatures increased all boards produced invalids at some point, but this seemed to be biased towards the FPGA0 side as well. FPGA0 on that "misbehaving" board was at like 5% invalid at that point, most other FPGAs still <1%.
No idea what exactly is going on here, but it indeed seems like there's something different between the two FPGAs, either with power supply, cooling or signal routing.
I think I can definitely rule out that this is a miner issue, as both FPGAs use exactly the same code base in MPBM. However it might still be interesting whether this happens with x6500miner as well, as this might be somehow related to communication behavior, so different software might be affected to different degrees.

I'm not sure what you saw, but I have some hard numbers to look at. I just took the trouble to compile all of the test results I have for the boards. I saved the "Run Summary" that prints out when you quit x6500-miner for every board that shipped out of here. Mind you, some of these tests were done before my cooling setup was really nailed down. Most tests were done at 180 MHz. Some runs also were noted as "bad" and I changed something, like reseating a heatsink or gluing a heatsink on, then retested. My notes show all of this. If we go too far back, x6500-miner wasn't recording the invalids rate, so this only includes about 2/3 of the boards.

Here are the raw results for all tests:

FPGA 0:
  Accepted + Rejected: 171902 shares
  Invalid: 1322
  -> 0.77% invalids
FPGA 1:
  Accepted + Rejected: 171557
  Invalid: 2975
  -> 1.73% invalids

As you can see, on average, FPGA 1 is actually worse. This makes sense to me, because I've always had FPGA 0 closest to the fan (air flowing left-to-right).

If I go through and remove those ones that I noted were not good and later improved them, taking only the last test with that board, I get the following:

FPGA 0:
  Accepted + Rejected: 149807 shares
  Invalid: 1154 -> 0.77%
FPGA 1:
  Accepted + Rejected: 150775
  Invalid: 1620 -> 1.07%

[Vanderbleek]

Standardized chipset mounting holes will allow for water cooling too.

@Fizzisist:

This is kind of a minor thing, but would it be possible to move the USB connector to the same side as the barrel / molex connector? That would make it much easier for enclosure /air flow designs.

Might make it easier to develop some sort of backplane too, so you could just plug the board into a "dock."

I think I'm going to have to save up my BTC to get one of these.

[shad]

all connectors on the same side would make my setup much easier

but as soon is i have enough btc i will buy a seconed board anyway

[ZodiacDragon84]

Is there a way to put a male USB connector to the board next to the female connector, so that multiple boards could be daisy chained together?

[bitcowok]

Heh you should have come up with all these suggestions a month ago when the new board was being designed.   I for one much prefer power one side, usb the other. The rev3 board, for me is completely optimal.

[99Percent]

How difficult would be to daisy chain the USB, and power?

[spiccioli]

Hi fizzisist,

could a fully passive cooler like this, one per fpga, be enough?

http://www.frozencpu.com/products/12775/vid-165/Deep_Cool_Nbridge_8_Northbridge_Chipset_Cooler.html?tl=g40c16s500&id=sLNsfH2v

spiccioli

[rjk]

Hi fizzisist,

could a fully passive cooler like this, one per fpga, be enough?

http://www.frozencpu.com/products/12775/vid-165/Deep_Cool_Nbridge_8_Northbridge_Chipset_Cooler.html?tl=g40c16s500&id=sLNsfH2v

spiccioli

Wow, those towers are lol.

[nbtcminer]

I noticed something similar as well while testing MPBM on the cluster. On most boards, there were no invalids at all while the ambient temperature was rather low, except for two boards. On one of them, FPGA0 got like 2% stales while FPGA1 didn't have any, and on the other one it was like 0.5% on FPGA0 and zero on FPGA1. As ambient temperatures increased all boards produced invalids at some point, but this seemed to be biased towards the FPGA0 side as well. FPGA0 on that "misbehaving" board was at like 5% invalid at that point, most other FPGAs still <1%.

Oh noes! The current heatsink looks way better
But seriously, I don't think using better heatsinks will help much here. The real bottleneck is the thermal bridge between the FPGA's die and the heatsink, which is obstructed by that nasty plastic package.

@TheSeven:

I'm glad you noticed the FPGA 0 / 1 invalid thing too. I didn't think much of it at first but I think it might be more hardware related then anything (I experienced the same issue of FPGA 1 generating more invalids then FPGA 0, which usually had 0% invalids). However having said that I'm at about 0.2% invalids on FPGA 1 and 0 % on FPGA 0 after 4 days of 24/7 mining so I'm not really too concerned about it at the moment.

BTW with regards to the plastic surface on the FPGA; do you think the anodized aluminum will do as good of a job as a full copper heatsink? I think a copper heatsink + good thermal compound (and/or epoxy) + active cooling should do the trick of eliminating overheating as a source of mh/s degradation.

Cheers,
nbtcminer

[Icoin]

the x6500 miner software seems to have some trouble with p2pool, after some hours of work with avarage 5% rejected 0 stale shares the miner just pulls blocks but doesnt provide any shares, have to restart the software to make it work again. does someone have this aswell with p2pool ?