Cairnsmore1 - Quad XC6SLX150 Board

[shad]

those look to near at the fpga

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[yohan]

A little more product detail just gone on there.

There is one set of holes per FPGA for a heatsink already. It just doesn't render as well as the plated holes. We are looking to see if we can fit some slightly wider ones on the other corners for our preferred heatsink option.

[simon66]

ummm... Nice board but I think 1 hole in the center might be a problem for me. I had plans to water cool this baby. Oh well, I guess I have to suck it up lol. Thanks for the img btw.

[rjk]

I wonder if there is a big enough air or water block to cover all 4 at once, if they were clustered together closer. Probably wouldn't work too well.

[simon66]

I wonder if there is a big enough air or water block to cover all 4 at once, if they were clustered together closer. Probably wouldn't work too well.

Oh yea, you gave me a great idea. You can always ask for a company to make you a custom block. I think I might just do that.

[TheHarbinger]

Guys

CAD image is now here http://www.enterpoint.co.uk/cairnsmore/cairnsmore1.html. I will be adding some more detail to this page later today.

Yohan

I just got rid of all my viagra.  Just going to carry a printout of this in my wallet.

[Glasswalker]

ummm... Nice board but I think 1 hole in the center might be a problem for me. I had plans to water cool this baby. Oh well, I guess I have to suck it up lol. Thanks for the img btw.

The holes on the corners of each FPGA are setup to take standard northbridge heatsinks. Which means any northbridge standard waterblock should work just fine using through-hole mount available on this board.

[rjk]

ummm... Nice board but I think 1 hole in the center might be a problem for me. I had plans to water cool this baby. Oh well, I guess I have to suck it up lol. Thanks for the img btw.

The holes on the corners of each FPGA are setup to take standard northbridge heatsinks. Which means any northbridge standard waterblock should work just fine using through-hole mount available on this board.

Yeah but you can't mount 4 heatsinks or blocks with only 1 hole in the middle.

[roomservice]

ummm... Nice board but I think 1 hole in the center might be a problem for me. I had plans to water cool this baby. Oh well, I guess I have to suck it up lol. Thanks for the img btw.

The holes on the corners of each FPGA are setup to take standard northbridge heatsinks. Which means any northbridge standard waterblock should work just fine using through-hole mount available on this board.

Yeah but you can't mount 4 heatsinks or blocks with only 1 hole in the middle.

I would be more interested in one large heatsink which covers all four fpga.

[Inspector 2211]

ummm... Nice board but I think 1 hole in the center might be a problem for me. I had plans to water cool this baby. Oh well, I guess I have to suck it up lol. Thanks for the img btw.

The holes on the corners of each FPGA are setup to take standard northbridge heatsinks. Which means any northbridge standard waterblock should work just fine using through-hole mount available on this board.

Yeah but you can't mount 4 heatsinks or blocks with only 1 hole in the middle.

I would be more interested in one large heatsink which covers all four fpga.

What if the four FPGAs are not precisely co-planar?
Are you OK with one or two of them running hot because the heat sink does not completely touch it/them?

[Glasswalker]

ummm... Nice board but I think 1 hole in the center might be a problem for me. I had plans to water cool this baby. Oh well, I guess I have to suck it up lol. Thanks for the img btw.

The holes on the corners of each FPGA are setup to take standard northbridge heatsinks. Which means any northbridge standard waterblock should work just fine using through-hole mount available on this board.

Yeah but you can't mount 4 heatsinks or blocks with only 1 hole in the middle.

Yes you can (if the middle hole you're looking at isn't actually for the heatsink).

The middle hole you see I believe is just for added support in mounting the board to it's chassis.

See the holes closer to the FPGA chips. They don't render as nice because of them not being plated holes. Those offer 2 distinct holes for each FPGA for heatsink mounting. It's stated they are standard northbridge hole spacing.

[Gomeler]

Sent out some feelers to some waterblock manufacturers to see if they'd be interested in manufacturing a two-sided waterblock that would be sandwiched by a pair of these boards. I'd like to mill my own, been a while since I tinkered with milling waterblocks, but having someone who does this for a living would yield something that the community could use. Waiting to see what they say, if some agree to being able to take on the project I'll be in touch with Enterpoint to get some exact dimensions for a preliminary waterblock design.

ummm... Nice board but I think 1 hole in the center might be a problem for me. I had plans to water cool this baby. Oh well, I guess I have to suck it up lol. Thanks for the img btw.

The holes on the corners of each FPGA are setup to take standard northbridge heatsinks. Which means any northbridge standard waterblock should work just fine using through-hole mount available on this board.

Yeah but you can't mount 4 heatsinks or blocks with only 1 hole in the middle.

I would be more interested in one large heatsink which covers all four fpga.

What if the four FPGAs are not precisely co-planar?
Are you OK with one or two of them running hot because the heat sink does not completely touch it/them?

Not a problem with a custom milled heatsink, so long as any height differences are consistent between devices. If they aren't consistent then there is an issue on the manufacturing side of things.

[Glasswalker]

I have a couple questions.

Can you elaborate on what chip exactly is the Array Controller?

Also what are the finished dimensions of the board (based on these cad designs) I'm shopping around for rackmount case solutions, and need dimensions to decide on a case.

Also when you say there is potential (with software development) to be able to drive the jtag via the USB, does that mean we could reflash the bitstreams on the 4 LX150 FPGAs via USB from the PC? without needing third party JTAG hardware? When you say software development needed for this, do you mean someone will need to release PC software to flash it with? Or do you mean that firmware of some kind for the "array controller" needs to be written to support it?

[Keninishna]

CAD design looks sexy, This guy in this thread https://bitcointalk.org/index.php?topic=49971.0 claims to be getting 227 mh/s on one of these cheap LX150s, in his latest design he says he can clock it to 180 mhz which would net around 270 mh/s!! I'm really hoping either he releases his bitstream or the enterpoint engineers can come up with something similar or even better, considering this is just 1 person. 1080 mh/s per board will make me piss myself.

[BinaryMage]

CAD design looks sexy, This guy in this thread https://bitcointalk.org/index.php?topic=49971.0 claims to be getting 227 mh/s on one of these cheap LX150s, in his latest design he says he can clock it to 180 mhz which would net around 270 mh/s!! I'm really hoping either he releases his bitstream or the enterpoint engineers can come up with something similar or even better, considering this is just 1 person. 1080 mh/s per board will make me piss myself.

Though I'm not willing to commit to the latter, I agree with the former. 1080 MH/s would give these boards ~1.5 MH/s per $, significantly better than BFL's ~1.25, and with lower power draw to boot!

[Garr255]

I bet Cognitive shareholders would agree to issuing some shares to raise funds for a few of these!

[yohan]

Our board should not need JTAG very often with the on-board bitstream storage. It shoul only be needed when an update is required.

It will also be possible to update the bitstream stored in a non-JTAG way if build the necessary function into the design. We can also store a few different bitstreams per FPGA which can be selected using a multi-boot technique.

[Gomeler]

Our board should not need JTAG very often with the on-board bitstream storage. It shoul only be needed when an update is required.

It will also be possible to update the bitstream stored in a non-JTAG way if build the necessary function into the design. We can also store a few different bitstreams per FPGA which can be selected using a multi-boot technique.

If we could program the flash through the USB connection it would greatly simplify interacting with the devices. I really like the idea of being able to select which bitstream but this wouldn't be as important to me as reprograming via USB. I figure I'd load a bitstream and run it for a few weeks/months without touching the device. Just my opinion though.

[Garr255]

If we could program the flash through the USB connection it would greatly simplify interacting with the devices. I really like the idea of being able to select which bitstream but this wouldn't be as important to me as reprograming via USB. I figure I'd load a bitstream and run it for a few weeks/months without touching the device. Just my opinion though.

+1

[Lethos]

Glad to see a UK supplier of what looks like epic level FPGA.
Seriously mouth wide open at what i'm looking at here.