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Author Topic: Cairnsmore1 - Quad XC6SLX150 Board  (Read 251127 times)
MXRider
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June 19, 2012, 04:41:45 PM
 #761

I would advice Enterpoint not to publish that much information. It might help competitors to push them out of the market.
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gyverlb
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June 19, 2012, 04:59:10 PM
 #762

I would advice Enterpoint not to publish that much information. It might help competitors to push them out of the market.
That's their call. The benefit for them is not easy to quantify : it will help gain customer trust but they may already have enough of that Smiley

P2pool tuning guide
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June 19, 2012, 09:55:00 PM
 #763

Received confirmation by mail that I was scheduled for ordering and ordered my boards yesterday.

Just when I wondered if there was some delay to be expected here...

...
I have received no response to the email I sent them on Saturday. When did you send your purchase request email, please?

IOWs, how long was the time between your first email and the confirmation?
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June 19, 2012, 10:06:53 PM
 #764

I have received no response to the email I sent them on Saturday. When did you send your purchase request email, please?

IOWs, how long was the time between your first email and the confirmation?

I sent mine on Sunday, waiting also for the reply
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June 19, 2012, 10:15:00 PM
 #765

Received confirmation by mail that I was scheduled for ordering and ordered my boards yesterday.

Just when I wondered if there was some delay to be expected here...

...
I have received no response to the email I sent them on Saturday. When did you send your purchase request email, please?

IOWs, how long was the time between your first email and the confirmation?
  • pre-ordered 2 boards May the 5th
  • received and declined an early ship proposition for one of the 2 boards May the 26th
  • received a get-go for my whole order and ordered June the 18th, paid the 19th and received shipping confirmation the same day

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yohan
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June 19, 2012, 10:17:22 PM
 #766

You will usually get a reply within a day. So send again. We have occasionally had an email go astray.
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June 19, 2012, 10:32:36 PM
 #767

You will usually get a reply within a day. So send again. We have occasionally had an email go astray.
Ok, mail resent.
LazyOtto
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June 19, 2012, 11:24:19 PM
 #768

You will usually get a reply within a day. So send again. We have occasionally had an email go astray.
Before resending, I went and searched the filtered/spam directory.

I had received a response within two hours of sending the purchase request.

Nice work, guys. And apologies for *my* negligence to check in the first place.
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June 20, 2012, 04:32:20 PM
 #769

D) The code is a bit strange, several things are... Wierd... in it. And it causes some problems, such as the boundry between clock domains between the comms code and the hashing cores, this causes in the default setup a clocking breakdown and the comms core fails, leaving the chip useless until it's restarted. There is also some over-sensitive settings on the hashing clock, which is why we had to underclock it to 50Mhz (over that the clock becomes unstable), which since the icarus code runs one hash per clock, that means 50MHash per chip. And a few other issues. Essentially it needs A LOT of hand holding to get it into a useful state at all.

There are seperate clock domains for the comms and hashing? Interesting. I hadn't really looked into it but was under the impression that the Icarus code was based on teknohog's clustering code and used a single clock domain for comms and hashing.

Quad XC6SLX150 Board: 860 MHash/s or so.
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June 20, 2012, 05:40:21 PM
 #770

Programming utilities now available on http://www.enterpoint.co.uk/cairnsmore/cairnsmore1_support_materials.html "twin_test.bit" is bitstream to run 2 FPGAs at high performance level and will give the biggest mining returns currently.



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June 20, 2012, 06:21:19 PM
 #771

Slight mistake in the guide so far;
Quote
mount –t auto /dev/sdb /mnt
on page 10 should be
Quote
mount –t auto /dev/sdb1 /mnt

I get as far as the programming stage when i need to set the dips and i get an error of
Code:
No JTAG Chain found

My Serial is 0018 and i seem to recall you mentioning the dip settings changed mid run at around number 30 26?, so would i use the same settings as the pdf's show?
Quote
Dip switches - One of things I have not quite got to as yet. One thing I was reminded about is that the functions on the Controller dip switches changed mid production ship so this might cause confusion when you are playing with them. The normal positions should be the same if I remember right but what they change differs. Hopefully that makes some sense. This change came in about board 26.

When i set 3 to off on SW1, i only get PGA 0 light up, all others are off?

My initial DIP settings also do not match the shipping test normal mode

SW6 was 1 off, 234 on
SW1 was all on

SW2 (PGA 0) was all on
SW3 (PGA 1) was 1 off, 234 on
SW4 (PGA 2) was 1 off, 234 on
SW5 (PGA 3) was all on
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June 20, 2012, 07:28:14 PM
 #772

no success either.
No jtag chain found,

or
JEDEC: ff ff 0xff 0xff
unknown JEDEC manufacturer: ff
ISF Bitfile probably not loaded

one with the pdf settings to program, and the other with normal operation (the dip switch setting where the first jtag probing at the beginning of the manual is successful)
Board Serial 62-0016

I'll wait patiently Wink

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yohan
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June 20, 2012, 07:37:41 PM
 #773

Dip switches are these same setting for both controller versions. There is some extra stuff to come to allow update of the controller using the same tools. Bitstream is already available if you have a programming cable and the tool can work that way as well to update the controller. If you are a power FPGA user and have it available ISE Impact can be used as well.

I'll have to take all the queries back to the engineer working on these bits so probably tomorrow before I have any response. Anything else anyone notices that needs fixing do let me know and I will try and get it all tidied up quickly. I wasn't expecting this to be a perfect process so it will probably be a bit buggy for a few days whilst we iron out the silly stuff. There is nothing better that the Microsoft way of debugging software. We are running a lot of this stuff in our line now so we might also suffer from being too familiar with the tools as well so we might have to add some things to the manuals.
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June 20, 2012, 08:14:32 PM
 #774

Yohan,

inside twin_test.pdf, page 2 and 3 are labelled

Code:
DIP Switch Settings for shipping_test.bit PROGRAMMING OPERATION

while page 1 is ok.

spiccioli
BCbitcoin
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June 20, 2012, 08:22:35 PM
 #775

Are future boards shipping with the 2x190mhz firmware installed?
atsoat
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June 20, 2012, 08:22:55 PM
 #776


I get as far as the programming stage when i need to set the dips and i get an error of
Code:
No JTAG Chain found

My Serial is 0018 and i seem to recall you mentioning the dip settings changed mid run at around number 30 26?, so would i use the same settings as the pdf's show?
Quote
Dip switches - One of things I have not quite got to as yet. One thing I was reminded about is that the functions on the Controller dip switches changed mid production ship so this might cause confusion when you are playing with them. The normal positions should be the same if I remember right but what they change differs. Hopefully that makes some sense. This change came in about board 26.

When i set 3 to off on SW6, i only get PGA 0 light up, all others are off?

My initial DIP settings also do not match the shipping test normal mode

SW1 was 1 off, 234 on
SW6 was all on

SW2 (PGA 0) was all on
SW3 (PGA 1) was 1 off, 234 on
SW4 (PGA 2) was 1 off, 234 on
SW5 (PGA 3) was all on



I have an early board as well.

Try programming with:

SW1 1 off, 234 on [ I actually had 1 on during programming, but not sure if this was necessary]
SW6 all on

SW2 (PGA 0) all on
SW3 (PGA 1) 12 off, 34 on
SW4 (PGA 2) 12 off, 34 on
SW5 (PGA 3) all on


And then run (without powering down inbetween) with the same config.

For the twin_test.bit only program 0 and 3.

Seems to have worked for me. I'm using the standard cgminer.

It seems to be faster and you now get a green light when it finds a nonce!

spiccioli
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June 20, 2012, 08:40:47 PM
 #777


I have an early board as well.

Try programming with:

SW1 1 off, 234 on [ I actually had 1 on during programming, but not sure if this was necessary]
SW6 all on

SW2 (PGA 0) all on
SW3 (PGA 1) 12 off, 34 on
SW4 (PGA 2) 12 off, 34 on
SW5 (PGA 3) all on


And then run (without powering down inbetween) with the same config.

For the twin_test.bit only program 0 and 3.

Seems to have worked for me. I'm using the standard cgminer.

It seems to be faster and you now get a green light when it finds a nonce!



atsoat,

setting switches your way on my board (serial G2-0008) I can issue the programming command

Code:
xc3sprog -c cm1 -p0 twin_test.bit

but it fails with

Code:
Using Libftdi,
DNA is 0x19573723a1207bfe
Device failed to configure, INSTRUCTION_CAPTURE is 0x19

and on FPGA0 all leds remain lit, FPGA1-3 yellow led lit, spartan3 blinking red led.

Sad

spiccioli

daemonic
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June 20, 2012, 08:52:48 PM
 #778


I have an early board as well.

Try programming with:

SW1 1 off, 234 on [ I actually had 1 on during programming, but not sure if this was necessary]
SW6 all on

SW2 (PGA 0) all on
SW3 (PGA 1) 12 off, 34 on
SW4 (PGA 2) 12 off, 34 on
SW5 (PGA 3) all on


And then run (without powering down inbetween) with the same config.

For the twin_test.bit only program 0 and 3.

Seems to have worked for me. I'm using the standard cgminer.

It seems to be faster and you now get a green light when it finds a nonce!



atsoat,

setting switches your way on my board (serial G2-0008) I can issue the programming command

Code:
xc3sprog -c cm1 -p0 twin_test.bit

but it fails with

Code:
Using Libftdi,
DNA is 0x19573723a1207bfe
Device failed to configure, INSTRUCTION_CAPTURE is 0x19

and on FPGA0 all leds remain lit, FPGA1-3 yellow led lit, spartan3 blinking red led.

Sad

spiccioli
exactly the same for me (obviously a different DNA)
spiccioli
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nec sine labore


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June 20, 2012, 08:57:02 PM
 #779

daemonic,

keep trying, it took me a good 10 retries for -p 0 to complete, but in the end I was able to reprogram it.

-p 3 took three retries, before succeeding.

Right now I'm mining on ABC pool, using mpbm Smiley

spiccioli

norulezapply
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June 20, 2012, 09:08:14 PM
 #780

You guys got it writing to the SPI flash too?

I've done the first part successfully but when I'm trying to write to SPI flash I get "Unknown JDEC manufacturer: ff"
"ISF bitfile probably not loaded"

Not sure if I need to change the DIP switches to the ones in twin_test.bit now? Do I do the first part then change my DIP switches to match the "twin_test.bit" PDF file ones whilst it's still turned on or something?

If my post helped, I'll happily accept a few bitmills!   15rGg6A1JFZV3b7TTbtpAaiYGdUD1e1oAm
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