Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)

[asjfdlksfd]

Hmm this is interesting. My room temp is 26C, and the FPGA never reported more than 45C on the 600MHz bitstream.

Are you sure the values are calculated correctly? Whats the temperature without calculating hashes? It should been round about 30-35 °C.
Which temp values do you get from serial port with minicom if no mining is working?
I've modified a little bit the kc705uartworker.py for checking:

Code:

            print("Temperature: ", "0x" + response, temperature)

Here the results from the console at the beginning of mining. Be aware, the lower values comes from the AVNet MMP

Code:

2013-05-24 04:12:54.601721 [500] stdout: ('Temperature: ', '0xA116', 43.97220840454105)
2013-05-24 04:12:55.744079 [500] stdout: ('Temperature: ', '0x9E8C', 38.973677062988315)
2013-05-24 04:12:59.743875 [500] stdout: ('Temperature: ', '0x9FDF', 41.58060340881349)
2013-05-24 04:13:02.601813 [500] stdout: ('Temperature: ', '0xA119', 43.99527854919438)
2013-05-24 04:13:03.744184 [500] stdout: ('Temperature: ', '0xA055', 42.488029098510765)
2013-05-24 04:13:06.601711 [500] stdout: ('Temperature: ', '0xA00A', 41.91127548217776)
2013-05-24 04:13:07.744082 [500] stdout: ('Temperature: ', '0x9F0F', 39.98107337951666)
2013-05-24 04:13:10.601820 [500] stdout: ('Temperature: ', '0x9F85', 40.88849906921388)
2013-05-24 04:13:11.744180 [500] stdout: ('Temperature: ', '0x9E44', 38.41999359130864)
...
2013-05-24 04:22:23.744699 [500] stdout: ('Temperature: ', '0xA77F', 56.59157752990728)
2013-05-24 04:22:27.744679 [500] stdout: ('Temperature: ', '0xA772', 56.49160690307622)
2013-05-24 04:22:30.601187 [500] stdout: ('Temperature: ', '0xB20A', 77.34701766967777)
2013-05-24 04:22:31.744582 [500] stdout: ('Temperature: ', '0xA777', 56.530057144165085)
2013-05-24 04:22:34.601285 [500] stdout: ('Temperature: ', '0xB1F6', 77.1932167053223)
2013-05-24 04:22:35.744667 [500] stdout: ('Temperature: ', '0xA78D', 56.69923820495609)
...

[asjfdlksfd]

I would love to know what differences you made in implementation to get down to 45C for 600mhz. That seems like a really drastic improvement.

I'm unsure that he mades so much improvement.
As I understood vivado reports on his design >12W which must be dissipationed against 400 MHz github design which reports <9 W and gives temps near by 60 °C.

But there chip to cooler heat conduction is possible better.

[goxed]

Is your fan rotating at full speed?

Here is my temperature while mining at 600MHZ
2013-05-23 22:28:30.048826 [500] stdout: Temperature:  26.8926113129
2013-05-23 22:28:30.298841 [350] Untitled KC705UART worker: Found share: XXXXXXX
:000000021910f9e1ac919036f4c838972845e8bff5a5676eaa8294fc0000008500000000495a089
9298a623a17a125e003af676ad660389dfc2e3ab7269cafdc95f292f3519ede561a017fe9:b54360
0a
2013-05-23 22:28:30.339843 [250] Untitled KC705UART worker: Eclipse accepted sha
re b543600a (difficulty 1.39333)

[asjfdlksfd]

Is your fan rotating at full speed?

Depends on noise...yes. Is it readable? As I understood theres a pin on fpga which
powers the fan. Possible the rotate count information from the fan could been
connected to the fpga for calculation by an counter. But I think that it is

Here is my temperature while mining at 600MHZ
2013-05-23 22:28:30.048826 [500] stdout: Temperature:  26.8926113129

Thats to less or you are living in Alaska and your miner is outside 

Could you check the temp calculation? It's a good idea to modify the print line
given above with my extension to have an cross check.
Eighter the calculation in the python script is wrong or your kc705 reports really
to less temperature or mine reports to much.
In my opinion with this cooler and the amout of 12 W consumption the temperature
should been room temp + 40 °C estimated. By me it should 66° C but at the moment
I get 71°C. I've clocked now my fpga to 550 MHz and Vivado reports < 12 W.

My AVNet MMP reports 55 °C at <8W which confirms the values of KC705.
So lets precheck the calculation of:
2013-05-24 04:22:30.601187 [500] stdout: ('Temperature: ', '0xB20A', 77.34701766967777)

The formula on README of OSFPGA KC705_Experimental says:
Temp (C) = reading * 503.975 / 65536 - 273.15:

Code:

Python 3.2.4 (default, May  8 2013, 20:55:18) 
[GCC 4.7.3] on linux2
Type "help", "copyright", "credits" or "license" for more information.
>>> 0xB20A
45578
>>> 0xB20A * 503.975 / 65536
350.49701766967775
>>> ( 0xB20A * 503.975 / 65536 ) - 273.15
77.34701766967777
>>> 0xB20A * 503.975 / 65536 - 273.15
77.34701766967777

[gingernuts]

Does the KC705 have realtime PSU monitoring? If so, how many amps is it really using on the vcore 1v rail? I'd really like to know if Vivado's estimates are anywhere near close!

[senseless]

Does the KC705 have realtime PSU monitoring? If so, how many amps is it really using on the vcore 1v rail? I'd really like to know if Vivado's estimates are anywhere near close!

Use the chipscope that comes with the software

[goxed]

according to the kc705 datasheet pg 65, the PmBus has to be read using a PMBus pod from Texas Instruments to figure out current drawn from the voltage regulators.
Using chipscope one can monitor the voltage though.

[goxed]

Is your fan rotating at full speed?

Depends on noise...yes. Is it readable? As I understood theres a pin on fpga which
powers the fan. Possible the rotate count information from the fan could been
connected to the fpga for calculation by an counter. But I think that it is

Here is my temperature while mining at 600MHZ
2013-05-23 22:28:30.048826 [500] stdout: Temperature:  26.8926113129

Thats to less or you are living in Alaska and your miner is outside 

Could you check the temp calculation? It's a good idea to modify the print line
given above with my extension to have an cross check.
Eighter the calculation in the python script is wrong or your kc705 reports really
to less temperature or mine reports to much.
In my opinion with this cooler and the amout of 12 W consumption the temperature
should been room temp + 40 °C estimated. By me it should 66° C but at the moment
I get 71°C. I've clocked now my fpga to 550 MHz and Vivado reports < 12 W.

My AVNet MMP reports 55 °C at <8W which confirms the values of KC705.
So lets precheck the calculation of:
2013-05-24 04:22:30.601187 [500] stdout: ('Temperature: ', '0xB20A', 77.34701766967777)

The formula on README of OSFPGA KC705_Experimental says:
Temp (C) = reading * 503.975 / 65536 - 273.15:

Code:

Python 3.2.4 (default, May  8 2013, 20:55:18) 
[GCC 4.7.3] on linux2
Type "help", "copyright", "credits" or "license" for more information.
>>> 0xB20A
45578
>>> 0xB20A * 503.975 / 65536
350.49701766967775
>>> ( 0xB20A * 503.975 / 65536 ) - 273.15
77.34701766967777
>>> 0xB20A * 503.975 / 65536 - 273.15
77.34701766967777

I will edit the python code in a day or two. currently trying to improve the miner. But meanwhile here is temperature output from Chipscope while mining at 600MHz.

[fpgaminer]

I have requested a pull for the open-source fpga project on github.

Hello goxed!  I just checked your pull requests.  There are no code changes in them.  One just adds a file named "600MHz" with the text "600MHz" in it.  The other is the same.  There must have been a mistake somewhere.

Does the KC705 have realtime PSU monitoring? If so, how many amps is it really using on the vcore 1v rail? I'd really like to know if Vivado's estimates are anywhere near close!

They shouldn't be hardly close at all.  The toggle rate of a SHA-256 hasher is significantly higher than typical FPGA designs.  Without a simulation to extract toggle rates from, Vivado's power estimator will do a very poor job.

Hmm, I used exactly you vivado project to create an bitstream. But the temparature is near by 76-78 °C realted to my room temperature (24 °C at the moment):
2013-05-24 01:20:10.619202 [500] stdout: ('Temperature: ', 76.9086849212647)

Just a note, that temperature reading is coming from the die itself, so it should be fairly close to the "real" temperature of the fabric.  The chips aren't designed to operate continuously above 85C (though I think they'll tolerate something like 100C without immediately failing).  Personally, I'd throw an extra fan at my KC705 if the Kintex was running near 76C.

[asjfdlksfd]

Hi fpgaminer,

can I reply my question about the dps adder replacement by simple adders?
I won't do this job again if you are allready finished ;-)
If we can drop the used dsps below 50 % we can try to add a second ring.

Cheers...

[gingernuts]

Given that the Spartan 6 150's on other mining boards burn ~10W and only run at ~27C under a small (40mm squared) heat sink and moderate airflow, I would have thought that the Kintex is far more likely to be running at around 30C than 70C. If it is burning 10W then that heatsink and fan would have to have a thermal resistance of 5C/W to get the chip that hot - and that's pretty crappy for a heatsink with a fan...

[Paladin69]

Can these be used on Litecoins yet?

[Khertan]

A bit off topic, but some experts here can answer me maybe, i m trying to optimize modification i made for a de0 nano, and i m trying to estimate the power used with the altera tool power play and dse explorer. How from the simulation can i extract the toggle rate ?

 thx

[asjfdlksfd]

Given that the Spartan 6 150's on other mining boards burn ~10W and only run at ~27C under a small (40mm squared) heat sink and moderate airflow, I would have thought that the Kintex is far more likely to be running at around 30C than 70C. If it is burning 10W then that heatsink and fan would have to have a thermal resistance of 5C/W to get the chip that hot - and that's pretty crappy for a heatsink with a fan...

As I remember Spartan-6 has no internal temp measuring, isn't it? My Spartan-6 boards on by both mq boards said round about 40 °C at room temp of 25 °C = 15 K difference. But they have an gpu cooler with an 6cm diameter.

The KC705 cooler with running fan tastes more than 40 °C (my finger means it's nasty warm, not to leave them to long on the cooler). So the internal +50 K looks like is a fact.
I checked the coolers stats from malico.com.tw web site (30x30x6 = MLT30-06) which I've measured. The stats says for that cooler an resistance of 4.82 K/W @ 200LFM to 2.4 K/W @ 600LFM. I'm unshure whats LFM means.
The Fan is 30x30 mm². I've found an titan TFD-3007M12S which could have 5m³/h (2,95cfm).
I guess with values + internal resistance ~ 4K/W at >12W on chip looks like is not so much aside from you calculation.

The cooler on MMP K7 boards which runs only on 350 MHz because of the limited pdc tastes warm round about <40°C, but not hot. With <8W and reported internal 55° C that's consistence to the KC705.

I will search my PT100 thermometer to check the temp later on cooler, but I guess that the high results are a fact.

I tried to start chipscope but never did this before and have problems how to do that

[asjfdlksfd]

Thanks for that - according to the manual the MMP power board only has 6A of VCCINT - which at 1.0v is just 6W - have you got a fan you can point at the regulator chips?

I've bought TI Simple switcher board for the AVNET. I'm unsure how much amperes they can deliver. At the moment I've downclocked to 350 MHz and got now stable near by 350 MHs without invalid nonces anymore.
Viavados Report Power means the chip needs aprox. 7.4 W but it's still the DSP design from the site.

Now I understand why I get invalid nonces...:

Xilinx power bank / FMC Voltage	Voltage (V)	Max Current (A)	Tolerance
Vccint/Vccbram	1	6	3.00%
Vcco	1.5 / 1.35	4	5.00%
Vccaux/Vccaux_io/Vccadc/Vcco/MGTVccaux	1.8	6	5.00%
Vccaux_io	2	2	3.00%
Vcco	2.5	8	5.00%
Vcco	3.3	8	5.00%
MGTAVcc	1	6	3.00%
MGTAVtt/MGTAVTTrcal	1.2	4	2.50%

I'm unsure we will get more power to the mmp by resoldering the second 1V line. Maybe or not...
But generally it is better to use 1V with an higher rate. I guess again D12F200A looks good and costs are not so high (est. 19 EUR + VAT + transport).

It's a little bit more complex than expected. I checked the simple switcher board and checked the documentation for Vccint/bram and MGTAVcc 1.0 V rails.
Both are descriped with an max. current of 6 A, but both rails from the pdc board supports only the fpga core.
So official the max. current is 2x 6A supported from TI LM21212 for fpga. But in fact also the LM21212 supports up to 12A and not only 6A described in TIs documentation for these chips.

On PDC board the LM21212s gets there power from the 3.3V rail with a max. current of 16.5A. 2x 12A at 1V should been possible so I think the LM21212s are limited to supports only 6A+ by an setup on pdc board. Possible this could been changed.
In fact of that it is possible to use 12W for the FPGA it should been possible to implement an bitstream design which supports more than 350 MHz as in the moment with an better balance so between both rails the current ist better balanced.
It is easier to use only one rail with 20 A :/

[goxed]

Given that the Spartan 6 150's on other mining boards burn ~10W and only run at ~27C under a small (40mm squared) heat sink and moderate airflow, I would have thought that the Kintex is far more likely to be running at around 30C than 70C. If it is burning 10W then that heatsink and fan would have to have a thermal resistance of 5C/W to get the chip that hot - and that's pretty crappy for a heatsink with a fan...

The KC7k325T kintex-7  FPGA on my KC705 board has consistent temps between 25 to 35C hashing as 600MH/s. I am using the default heatsink, and reading temps off the chipscope. I will soon have access to another kc705, and will report its temps once ii is set up.

[goxed]

Given that the Spartan 6 150's on other mining boards burn ~10W and only run at ~27C under a small (40mm squared) heat sink and moderate airflow, I would have thought that the Kintex is far more likely to be running at around 30C than 70C. If it is burning 10W then that heatsink and fan would have to have a thermal resistance of 5C/W to get the chip that hot - and that's pretty crappy for a heatsink with a fan...

As I remember Spartan-6 has no internal temp measuring, isn't it? My Spartan-6 boards on by both mq boards said round about 40 °C at room temp of 25 °C = 15 K difference. But they have an gpu cooler with an 6cm diameter.

The KC705 cooler with running fan tastes more than 40 °C (my finger means it's nasty warm, not to leave them to long on the cooler). So the internal +50 K looks like is a fact.
I checked the coolers stats from malico.com.tw web site (30x30x6 = MLT30-06) which I've measured. The stats says for that cooler an resistance of 4.82 K/W @ 200LFM to 2.4 K/W @ 600LFM. I'm unshure whats LFM means.
The Fan is 30x30 mm². I've found an titan TFD-3007M12S which could have 5m³/h (2,95cfm).
I guess with values + internal resistance ~ 4K/W at >12W on chip looks like is not so much aside from you calculation.

The cooler on MMP K7 boards which runs only on 350 MHz because of the limited pdc tastes warm round about <40°C, but not hot. With <8W and reported internal 55° C that's consistence to the KC705.

I will search my PT100 thermometer to check the temp later on cooler, but I guess that the high results are a fact.

I tried to start chipscope but never did this before and have problems how to do that

Hey can you please report your KC705 VccInt from either XADC / chipscope or a DMM? Mine's 1.05V

[goxed]

I have requested a pull for the open-source fpga project on github.

Hello goxed!  I just checked your pull requests.  There are no code changes in them.  One just adds a file named "600MHz" with the text "600MHz" in it.  The other is the same.  There must have been a mistake somewhere.

Hey thanks for letting me know. my bad! I think I have to learn how to correctly use github.

[goxed]

I have a question about compiling sha256_pipes2.v under Vivado. It compiles fine under Xilinx ISE, but vivado seems to not like this source, it always points the following line with syntax error.

Code:

for (i = 0; i <= STAGES; i = i + 1) begin : S

   

Anyone got this verilog source to compile in Vivado?

[kingcoin]

I have a question about compiling sha256_pipes2.v under Vivado. It compiles fine under Xilinx ISE, but vivado seems to not like this source, it always points the following line with syntax error.

Code:

for (i = 0; i <= STAGES; i = i + 1) begin : S

   

Anyone got this verilog source to compile in Vivado?

I haven't read that file, but in general if that is part of a generate statement you have to make sure that you have made Vivado accept Verilog-2001,  SystemVerilog or whatever version of Verilog your syntax corresponds to. From a TCL script you can read the file using something like this:

Code:

 read_verilog -sv sha256_pipes2.v