Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)

[OrphanedGland]

Hi all,

I finally joined today to participate in this development. I am an experienced ASIC designer turned game programmer. I just started looking at the source code, hopefully will be contributing to the improvement of the core soon.

Question to others, have you considered pooling together to tape out an ASIC? A TSMC shuttle wouldn't cost 1 million. I can do the ASIC, but I lack the PCB board design knowledge. I can do it, but it'll probably have a short somewhere.

___________________________________________________________
Donate to me at: 1PNkxttFgUzvaMjmnzEU5dbviSiv9qkHBp

I have done some VLSI development, but it was full custom (ie hand-drawn layout using magic, rather than place and route RTL / standard cells).  We used MOSIS (www.mosis.com) which does "multi-project wafer runs" to keep costs down.  Back in 2001 we got a chip made using a 0.18um TSMC CMOS process.  Ended up costing around $50k for 50 chips, although not all of them were packaged.  The RTL used on this FPGA project could be used by yourself as a starting point to produce an ASIC design.  I would then recommend looking into optimizing the adder structures making use of CSA and CLA techniques.  Then some decisions need to be made about the external I/O.

[kokjo]

maybe the guys talking about ASIC should start a new thread about ASIC mining.
no offence. but the thread is about FPGA mining. i really like guys who haves bit idea for bitcoin mining, but you are getting offtopic now.

[FallingEdge]

to TheSeven
Thank's for this implementation.
I get your project from https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/0a9077e5c070e0a601981c6ec42dfc946fe3ccd6/projects/VHDL_Xilinx_Port
VHDL synthesized well, but an error got when run miner.py:

Code:

root@debian:/home/user2/d# python miner.py
Traceback (most recent call last):
  File "miner.py", line 478, in <module>
    curses.wrapper(miner.run)
  File "/usr/local/lib/python2.7/curses/wrapper.py", line 43, in wrapper
    return func(stdscr, *args, **kwds)
  File "miner.py", line 380, in run
    self.showstats()
  File "miner.py", line 290, in showstats
    self.statuswin.vline(4, x, curses.ACS_VLINE, my - 5)
_curses.error: wmove() returned ERR

What it means?
I run it on Debian 6.0, Python 2.7.2

 

[kokjo]

to TheSeven
Thank's for this implementation.
I get your project from https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/0a9077e5c070e0a601981c6ec42dfc946fe3ccd6/projects/VHDL_Xilinx_Port
VHDL synthesized well, but an error got when run miner.py:

Code:

root@debian:/home/user2/d# python miner.py
Traceback (most recent call last):
  File "miner.py", line 478, in <module>
    curses.wrapper(miner.run)
  File "/usr/local/lib/python2.7/curses/wrapper.py", line 43, in wrapper
    return func(stdscr, *args, **kwds)
  File "miner.py", line 380, in run
    self.showstats()
  File "miner.py", line 290, in showstats
    self.statuswin.vline(4, x, curses.ACS_VLINE, my - 5)
_curses.error: wmove() returned ERR

What it means?
I run it on Debian 6.0, Python 2.7.2

 

it has some thing to do with curses.
try a different terminal maybe, i don't know.

[Freakin]

How would something like a Papilio stack up to the cards being used in this thread?
http://papilio.cc/

Is it laughably underpowered?

Looks like it's a Spartan 3E chip on board, but it appears to be a cheap stripped down FPGA

[O_Shovah]

So if i would compare a Altera Cyclon III with 55k macrocells

 http://de.farnell.com/altera/ep3c55u484c7n/fpga-cyclone-iii-55k-le-484ubga/dp/1742170

to a Xilinx Spartan 3 with roughly 53k macrocells

 http://de.farnell.com/xilinx/xc3sd3400a-4csg484i/fpga-spartan-3a-dsp-484csbga/dp/1876218

The Xilinx would be a lot slower than the altera due to the routing problem using the current code altough they both have almost the same number of Elements.

Or am i mistaken here ?

Has anyone tested one or both of this chips and may supply Mh/s or similiar data for performance comparison ?

Itmight be interesting if the lower performance of the xilinx chips is caught up by theri lower prices.


The other thing is : How do the chips of the different families differ if they have the same number of elements  eg between cyclone III  and IV ?

[TheSeven]

to TheSeven
Thank's for this implementation.
I get your project from https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/0a9077e5c070e0a601981c6ec42dfc946fe3ccd6/projects/VHDL_Xilinx_Port
VHDL synthesized well, but an error got when run miner.py:

Code:

root@debian:/home/user2/d# python miner.py
Traceback (most recent call last):
  File "miner.py", line 478, in <module>
    curses.wrapper(miner.run)
  File "/usr/local/lib/python2.7/curses/wrapper.py", line 43, in wrapper
    return func(stdscr, *args, **kwds)
  File "miner.py", line 380, in run
    self.showstats()
  File "miner.py", line 290, in showstats
    self.statuswin.vline(4, x, curses.ACS_VLINE, my - 5)
_curses.error: wmove() returned ERR

What it means?
I run it on Debian 6.0, Python 2.7.2

 

it has some thing to do with curses.
try a different terminal maybe, i don't know.

Yes, it's a curses error, most likely being caused by the terminal window being too small to draw the summary box at the top.
Depending on the length of your pool names the current version will need around 120 chars of width, the older one in the git repository maybe a bit less.

[FallingEdge]

Yes, it's a curses error, most likely being caused by the terminal window being too small to draw the summary box at the top.

You're right, I increase terminal window size and now it work.

Depending on the length of your pool names the current version will need around 120 chars of width, the older one in the git repository maybe a bit less.

What is a current version? This?   http://dl.dropbox.com/u/23683845/pyfpgaminer-0.0.1.zip

[TheSeven]

What is a current version? This?   http://dl.dropbox.com/u/23683845/pyfpgaminer-0.0.1.zip

http://dl.dropbox.com/u/23683845/pyfpgaminer-0.0.3.zip

[FallingEdge]

http://dl.dropbox.com/u/23683845/pyfpgaminer-0.0.3.zip

Thanks, it work fine,
but i get only  6.253394 MH/s 

My  FPGA is Virtex IIPro XC2VP50 and project settings are:
  miner clock frequency = 50 MHz
  DEPTH = 3

In your opinion, is  6 MH/s correct value for this project settings?
or did I do something wrong?

[lame.duck]

Yes, this values should be correct, i get with LOOP=3

8   MHash/s @ 65 MHz on a EP2C35C8    (Fmax=63 MHz)         
14 MHash/s @ 85 MHz on a EP3C25C6

both with the original code from fpgaminer

[TheSeven]

http://dl.dropbox.com/u/23683845/pyfpgaminer-0.0.3.zip

Thanks, it work fine,
but i get only  6.253394 MH/s 

My  FPGA is Virtex IIPro XC2VP50 and project settings are:
  miner clock frequency = 50 MHz
  DEPTH = 3

In your opinion, is  6 MH/s correct value for this project settings?
or did I do something wrong?

DEPTH = 3 means 2^3 = 8 pipeline stages for the 64 SHA256 rounds, so each nonce will take 64 / 8 = 8 clock cycles. At 50 MHz that's 50 / 8 = 6.25 MH/s.

[O_Shovah]

I ve been looking for another developement board and got interested in this one xilinx Spartan 6

http://shop.trenz-electronic.de/catalog/product_info.php?products_id=830

As i asume the LE's of altera and xilinx to be equivalent this should be abled to run the xilinx version of teknohog an full scale or are there any other limitations than routing ?

If nobody has objections ,i will order it and be ready to help improving the code after my exams in august.

[lame.duck]

Why not just download the ISE from webpack and doing some dry runs on the code? The software will tell you the device utilisation and the expectable performance numbers and the functionl correctness can be tested before.

For mining there could with the current code base some better suited boards, but this can change with better designs.

[makomk]

I ve been looking for another developement board and got interested in this one xilinx Spartan 6

http://shop.trenz-electronic.de/catalog/product_info.php?products_id=830

As i asume the LE's of altera and xilinx to be equivalent this should be abled to run the xilinx version of teknohog an full scale or are there any other limitations than routing ?

They're not even remotely equivalent for the Spartan 6 series. The good news is that Spartan-6's LUTs are 6-input rather than 4-input, and that registers aren't as closely tied to LUTs which means you don't waste as many LUTs. The bad news is that the number of actual 6-LUTs is only 2/3rds of the number of equivalent "logic cells" they advertise, and of those only half have the carry chains required to use them as adders, and I don't think they can calculate more than a single bit of an addition per LUT (unlike the ALEs on Altera's recent Stratix FPGAs), and they lack the small local-ish RAM blocks that are used as shift registers on the Cyclone IV.

Basically, you're going to have fun fitting the design into anything smaller than the XC6SLX100, and unfortunately FPGAs that big aren't supported by Xilinx's free WebPack tools. The number of LUTs and registers might look like it'll fit with some cramming on the LX75, but you'll be constrained by the number of adders required. As for the LX45 - no chance as far as I can see, not even close to enough LUTs.

[O_Shovah]

Thank you both for your advice.

I've downloaded the ISE and am going to try am few dry runs for this chip.

If this chip isn't worth the effort wich board would you recommend for less than 300 Euro including maybe a reduction for students ?
(Beside the DE-115 already shown)

I remember fpgaminer to have reported he started testing on an Spartan 6 board.His results would be interesting.

[sjohn]

thanks for all your hard work so far, is there anyway you could have a sof file preconfigured at 80Mh/s for my de2-115?

[fpgaminer]

thanks for all your hard work so far, is there anyway you could have a sof file preconfigured at 80Mh/s for my de2-115?

You are most welcome Do you have appropriate cooling on your DE2-115? 80MHz on the DE2-115 will damage your FPGA without proper cooling, and will also fail to generate correct shares.

I can make a SOF regardless and let you know the cooling requirements, but I want to make sure you are fully aware of the dangers (like the loss of $600 when your FPGA dies from heat).

[BkkCoins]

Here's my idea of how to go about a good FPGA/ASIC platform. It's similar in basic concept to TheSeven's but I think more flexible.

Design and build a small board that has a PIC18F97 chip and 4 slots (maybe RAM type upward facing connectors). This chip costs $5 and has a ethernet MAC/PHY and TCP/IP stack on board. You can program it do be the controller and connect to mining servers to get jobs and relay results. Given there is already web server open source code around for it means it's reasonable easy to do this.

Set a standard for the edge connectors on board that involves either I2C, SPI or JTAG or a combo so that the controller can talk to some number of FPGA chips via this bus. It also inits the FPGA at boot from a TFTP server on the net (or wherever).

Make small cards that plug into this similar to RAM on a mainboard that have grids of FPGA or ASIC chips on board. These boards could be made by anybody using whatever tech as long as they can tap into the standardized BUS and receive jobs.

Breaking the system into two halves allows for flexibility and scaling up as money is available. You may start out with a mainboard and one 2 FPGA card. Then later add more cards, or sell cards and get 4 chip cards, 8 chips cards etc. You would only be limited by the BUS addressing limit and I think 256 would be a good number for that.

This allows developing with FPGA and later moving to ASIC without re-designing. It allows community work on improving components over time. It allows making a PCIe board mainboard instead of dedicated ethernet board. Having it modular and standardized allows for a secondary market so that as people upgrade there is room for reselling old parts that can still be used.

The mainboard doesn't have to be PIC but that is cheap and easy to program with free tools and should be more than adequate to get jobs and relay to slots. It has readily available TCP/IP code, it's very low power. It's only downside is it doesn't have USB built in which would allow hanging the system off another PC without using a PCIe slot.

I think something along this lines would be very smart and allow everyone to work together with their ideas for different FPGA /ASIC designs. I made small PIC boards and even an FPGA break out board (for XC2S200E long ago) manually myself and that isn't hard at all. With only a small set of BUS lines between FPGAs the PCB becomes very easy, and once proven then commercial high grade boards can be made. And then once that's proven full on ASIC modules could be done.

The only thing that needs to happen to go down this road is a standard agreed for the bus slot and protocol. I would think that JTAG is ideal as it allows programming and then also updating registers with DATA as jobs get processed. But I'm not familiar with the actual FPGA code. Maybe using a secondary I2C bus allows separating the FPGA architecture from the data processing protocol and that may be good.

[O_Shovah]

Here's my idea of how to go about a good FPGA/ASIC platform. It's similar in basic concept to TheSeven's but I think more flexible.

Design and build a small board that has a PIC18F97 chip and 4 slots (maybe RAM type upward facing connectors). This chip costs $5 and has a ethernet MAC/PHY and TCP/IP stack on board. You can program it do be the controller and connect to mining servers to get jobs and relay results. Given there is already web server open source code around for it means it's reasonable easy to do this.

Set a standard for the edge connectors on board that involves either I2C, SPI or JTAG or a combo so that the controller can talk to some number of FPGA chips via this bus. It also inits the FPGA at boot from a TFTP server on the net (or wherever).

Make small cards that plug into this similar to RAM on a mainboard that have grids of FPGA or ASIC chips on board. These boards could be made by anybody using whatever tech as long as they can tap into the standardized BUS and receive jobs.

Breaking the system into two halves allows for flexibility and scaling up as money is available. You may start out with a mainboard and one 2 FPGA card. Then later add more cards, or sell cards and get 4 chip cards, 8 chips cards etc. You would only be limited by the BUS addressing limit and I think 256 would be a good number for that.

This allows developing with FPGA and later moving to ASIC without re-designing. It allows community work on improving components over time. It allows making a PCIe board mainboard instead of dedicated ethernet board. Having it modular and standardized allows for a secondary market so that as people upgrade there is room for reselling old parts that can still be used.

The mainboard doesn't have to be PIC but that is cheap and easy to program with free tools and should be more than adequate to get jobs and relay to slots. It has readily available TCP/IP code, it's very low power. It's only downside is it doesn't have USB built in which would allow hanging the system off another PC without using a PCIe slot.

I think something along this lines would be very smart and allow everyone to work together with their ideas for different FPGA /ASIC designs. I made small PIC boards and even an FPGA break out board (for XC2S200E long ago) manually myself and that isn't hard at all. With only a small set of BUS lines between FPGAs the PCB becomes very easy, and once proven then commercial high grade boards can be made. And then once that's proven full on ASIC modules could be done.

The only thing that needs to happen to go down this road is a standard agreed for the bus slot and protocol. I would think that JTAG is ideal as it allows programming and then also updating registers with DATA as jobs get processed. But I'm not familiar with the actual FPGA code. Maybe using a secondary I2C bus allows separating the FPGA architecture from the data processing protocol and that may be good.

I totally second your idea.

I also thought about creating a modular system simmilar to the "copacobana" project.So it would be possible to scale your system according to your financial limits.

The demanding task still is to make such a design affordable to people else than enthusiasts.Eg the minimum "copacobana" system is about 11500 Euro.

I propose we should open another thread for  " Modular FPGA miner Hardware Design " or simmilar to discuss possible  design approaches.