Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)

[BkkCoins]

Here's my idea of how to go about a good FPGA/ASIC platform. It's similar in basic concept to TheSeven's but I think more flexible.

Design and build a small board that has a PIC18F97 chip and 4 slots (maybe RAM type upward facing connectors). This chip costs $5 and has a ethernet MAC/PHY and TCP/IP stack on board. You can program it do be the controller and connect to mining servers to get jobs and relay results. Given there is already web server open source code around for it means it's reasonable easy to do this.

Set a standard for the edge connectors on board that involves either I2C, SPI or JTAG or a combo so that the controller can talk to some number of FPGA chips via this bus. It also inits the FPGA at boot from a TFTP server on the net (or wherever).

Make small cards that plug into this similar to RAM on a mainboard that have grids of FPGA or ASIC chips on board. These boards could be made by anybody using whatever tech as long as they can tap into the standardized BUS and receive jobs.

Breaking the system into two halves allows for flexibility and scaling up as money is available. You may start out with a mainboard and one 2 FPGA card. Then later add more cards, or sell cards and get 4 chip cards, 8 chips cards etc. You would only be limited by the BUS addressing limit and I think 256 would be a good number for that.

This allows developing with FPGA and later moving to ASIC without re-designing. It allows community work on improving components over time. It allows making a PCIe board mainboard instead of dedicated ethernet board. Having it modular and standardized allows for a secondary market so that as people upgrade there is room for reselling old parts that can still be used.

The mainboard doesn't have to be PIC but that is cheap and easy to program with free tools and should be more than adequate to get jobs and relay to slots. It has readily available TCP/IP code, it's very low power. It's only downside is it doesn't have USB built in which would allow hanging the system off another PC without using a PCIe slot.

I think something along this lines would be very smart and allow everyone to work together with their ideas for different FPGA /ASIC designs. I made small PIC boards and even an FPGA break out board (for XC2S200E long ago) manually myself and that isn't hard at all. With only a small set of BUS lines between FPGAs the PCB becomes very easy, and once proven then commercial high grade boards can be made. And then once that's proven full on ASIC modules could be done.

The only thing that needs to happen to go down this road is a standard agreed for the bus slot and protocol. I would think that JTAG is ideal as it allows programming and then also updating registers with DATA as jobs get processed. But I'm not familiar with the actual FPGA code. Maybe using a secondary I2C bus allows separating the FPGA architecture from the data processing protocol and that may be good.

[O_Shovah]

Here's my idea of how to go about a good FPGA/ASIC platform. It's similar in basic concept to TheSeven's but I think more flexible.

Design and build a small board that has a PIC18F97 chip and 4 slots (maybe RAM type upward facing connectors). This chip costs $5 and has a ethernet MAC/PHY and TCP/IP stack on board. You can program it do be the controller and connect to mining servers to get jobs and relay results. Given there is already web server open source code around for it means it's reasonable easy to do this.

Set a standard for the edge connectors on board that involves either I2C, SPI or JTAG or a combo so that the controller can talk to some number of FPGA chips via this bus. It also inits the FPGA at boot from a TFTP server on the net (or wherever).

Make small cards that plug into this similar to RAM on a mainboard that have grids of FPGA or ASIC chips on board. These boards could be made by anybody using whatever tech as long as they can tap into the standardized BUS and receive jobs.

Breaking the system into two halves allows for flexibility and scaling up as money is available. You may start out with a mainboard and one 2 FPGA card. Then later add more cards, or sell cards and get 4 chip cards, 8 chips cards etc. You would only be limited by the BUS addressing limit and I think 256 would be a good number for that.

This allows developing with FPGA and later moving to ASIC without re-designing. It allows community work on improving components over time. It allows making a PCIe board mainboard instead of dedicated ethernet board. Having it modular and standardized allows for a secondary market so that as people upgrade there is room for reselling old parts that can still be used.

The mainboard doesn't have to be PIC but that is cheap and easy to program with free tools and should be more than adequate to get jobs and relay to slots. It has readily available TCP/IP code, it's very low power. It's only downside is it doesn't have USB built in which would allow hanging the system off another PC without using a PCIe slot.

I think something along this lines would be very smart and allow everyone to work together with their ideas for different FPGA /ASIC designs. I made small PIC boards and even an FPGA break out board (for XC2S200E long ago) manually myself and that isn't hard at all. With only a small set of BUS lines between FPGAs the PCB becomes very easy, and once proven then commercial high grade boards can be made. And then once that's proven full on ASIC modules could be done.

The only thing that needs to happen to go down this road is a standard agreed for the bus slot and protocol. I would think that JTAG is ideal as it allows programming and then also updating registers with DATA as jobs get processed. But I'm not familiar with the actual FPGA code. Maybe using a secondary I2C bus allows separating the FPGA architecture from the data processing protocol and that may be good.

I totally second your idea.

I also thought about creating a modular system simmilar to the "copacobana" project.So it would be possible to scale your system according to your financial limits.

The demanding task still is to make such a design affordable to people else than enthusiasts.Eg the minimum "copacobana" system is about 11500 Euro.

I propose we should open another thread for  " Modular FPGA miner Hardware Design " or simmilar to discuss possible  design approaches.

[BkkCoins]

I think a 4 slot main board should be doable in the under $20 cost range. So whatever is a good markup on that for a small business to sell them. Or sell kits with PCB from an online fab. I'm assuming the design would be completely open.

The plugins would depend totally on the FPGA being used. The boards ought to be simple and low cost. Any good chips are not very cheap though.

A new thread is a good idea if people want to discuss a connector/protocol standard.

So DIMM = Dual Inline Miner Module.

[O_Shovah]

I have opened a new Thread specifically for the hardware development of a dedicated FPGA mining system.  http://forum.bitcoin.org/index.php?topic=22426.0

I'd like to invite everybody interested in helping to plot out the hardware needed to get a prototype of a modular Mining system no matter his experience.

I especially like to ask all of you who are currently developing this FPGA Miner to help us determine wich FPGA chips are needed at minium for one execution of a full unrolled Miner.


Thank you for your help 

[shivansps]

I wonder what kind of FPGA boards can be used for mining? im been looking in ebay and there is some small boards at 25usd...

http://cgi.ebay.com/MAXII-EPM570-CPLD-FPGA-Mini-Development-Board-Red-JTAG-/190524705338?pt=LH_DefaultDomain_0&hash=item2c5c284a3a#ht_3191wt_905

http://cgi.ebay.com/Altera-CycloneII-EP2C5T144-FPGA-Board-USB-Blaster-JTAG-/200522075217?pt=LH_DefaultDomain_0&hash=item2eb00c0c51#ht_3760wt_905

http://cgi.ebay.com/Altera-CycloneII-EP2C5T144-FPGA-Mini-Development-Board-/190501210627?pt=LH_DefaultDomain_0&hash=item2c5ac1ca03#ht_2749wt_905

[lame.duck]

the EP2C5 boards are to small for the original design. Maybe one could change it for using Block-RAM as registers but ... there are boards with a better price/performance ratio.

EP2C8 does work with LOOP set to  5, but such a board would be rather suited for learning verilog or VHDl rather than for mining.

I have a board with a EP3C25 that runs with the LOOP=3. which results in 10 MHash/s, with proper cooling i could get get 20% more from what the timing analyzer says but i don't like to have the board scrapped.

[BkkCoins]

It's interesting to see peoples hash rates with various chips and designs. It would be nice if there were a place to centrally note them for easy comparison.

None of the ones I've noticed so far has been anything to challenge GPU speed/cost. And I'm thinking as a chip only cost versus GPU not the dev kit cost.

If we could find one FPGA chip that gets a good speed to cost ratio that may be worth building a board around. It would be a winner. So far the chips alone seem too costly for the hash rates to be worthwhile, and power costs would have to become much more significant to make them viable.

[njloof]

It's interesting to see peoples hash rates with various chips and designs. It would be nice if there were a place to centrally note them for easy comparison.

... like here?

https://en.bitcoin.it/wiki/Mining_hardware_comparison

[BkkCoins]

It's interesting to see peoples hash rates with various chips and designs. It would be nice if there were a place to centrally note them for easy comparison.

... like here?

https://en.bitcoin.it/wiki/Mining_hardware_comparison

Yes, excellent. I don't have an account there but it would be great if people chose to add their numbers there. It's the perfect place to collect that data.

[O_Shovah]

I add a Subheadline for FPGA's

Everybody please  enter your values  so we may get a platform to compare our approaches:

https://en.bitcoin.it/wiki/Mining_hardware_comparison#FPGA_Devices

[LazarusLong]

TheSeven, could you explain what you're doing here?
I am porting this stuff to C and i am wondering about those magic numbers like 94.738 and 45.335163.

Code:

    self.log("Endtime: %f\n" % endtime)
    delta = (endtime - starttime)  - 0.0145
    self.mhps = 45.335163 / delta
    delta = min(60, delta * 94.738)
    self.log("%f MH/s\n" % self.mhps, curses.A_BOLD)
    self.fpgajobinterval = min(self.fpgajobinterval, max(0.5, delta * 0.8 - 1))
    self.fpgapollinterval = min(self.fpgapollinterval, self.fpgajobinterval / 5)
    self.log("FPGA job interval: ")

And why to multiply with 0.8 ??

[O_Shovah]

Thank you fpgaminer for adding the wiki link.

Seems theres already showing some activity 

[TheSeven]

TheSeven, could you explain what you're doing here?
I am porting this stuff to C and i am wondering about those magic numbers like 94.738 and 45.335163.

Code:

    self.log("Endtime: %f\n" % endtime)
    delta = (endtime - starttime)  - 0.0145
    self.mhps = 45.335163 / delta
    delta = min(60, delta * 94.738)
    self.log("%f MH/s\n" % self.mhps, curses.A_BOLD)
    self.fpgajobinterval = min(self.fpgajobinterval, max(0.5, delta * 0.8 - 1))
    self.fpgapollinterval = min(self.fpgapollinterval, self.fpgajobinterval / 5)
    self.log("FPGA job interval: ")

And why to multiply with 0.8 ??

0.0145 is the duration (in seconds) to upload the getwork to the FPGA and donwnload the nonce found.
45335163 is the number of nonces that will have been checked until the matching nonce is found, which means that during this time 45.335163 megahashes have been calculated.
94.738 == 2^32 / 45335163, which means that 94.738 times the measured time is needed for the FPGA to process the full getwork.
* 0.8 - 1 is just a precaution to give the software enough time to send a new getwork to the FPGA before it runs out of work, as it doesn't hurt if we miss out a couple of nonces at the end. Remember that the FPGA will keep working on the old getwork while a new one is being transmitted, and that it can even submit a share during that. (I just realized that a WORK ACK packet (0x01) might get lost if that happens!)

[LazarusLong]

Hmmm 
I have a delta of 15s with the test pattern - thus ~3MH/s on my Lattice ECP33
15s * 94.738 gives a quite large number, therefore the  min(60) hits and I end up with 47s job intervall.
Whay is it right to take this short path to 60s? I guess this was not ment to run on delta > 1.

[O_Shovah]

I further edited the wiki article https://en.bitcoin.it/wiki/Mining_hardware_comparison#Hardware_Prices

Now there is a column for the Mhash/$/€ ratio. This should help to compare the devices for economical reasons.

I also added a references section  so threre are the links for the price and performance sources.

I will continue adding the Mhash/$/€ column for the other subsections too. 

[shivansps]

I wonder who was the noob who messed up my work of adding the APUs intro the tables by joining them with the AMD cpus...

Anyway, what could be a good option for a starter? ill like to get 1 FPGA board and put it to mine just for fun.

[O_Shovah]

Well i cant remember to have done something to the AMD section yet 

As this FPGA subjet in total is still experimental still one of the best  affordable board in comparsion to its Mhash ratio the DE-115 proposed by fpgaminer.

( or as now may be seen in the Mhash/$/€    )
 

[TheSeven]

Hmmm 
I have a delta of 15s with the test pattern - thus ~3MH/s on my Lattice ECP33
15s * 94.738 gives a quite large number, therefore the  min(60) hits and I end up with 47s job intervall.
Whay is it right to take this short path to 60s? I guess this was not ment to run on delta > 1.

It is recommended to request a new getwork at least every 60 seconds, so that you're working on one with a semi-current timestamp in the block. By buffering work I'm already exceeding that on slow FPGAs, this limit is just to prevent it from being much worse (at 3MH/s it would be like a 66 minute delay from the getwork request to share submission in the worst case, so you would usually only work on a single getwork before long polling kills it off).

[inh]

Did I miss it in the thread where someone hit 109 Mhps?

[lame.duck]

Did I miss it in the thread where someone hit 109 Mhps?

Did you already read the first post of this thread? There it is but if largish Mhps numbers give you a thrill you could download quartus, load the design and testcompile it with different combinations of  processing options, regarding logic count, cacle time, power consumption and look what for results you get -> numver of logic cells, maximum cycle time, junction temperature with cooling options from 'no cooling' to 'large heat sink with Air flow' ...  i think the number of test setups 'mining' is bigger than the number of people writing in this thread. Really important to most people are new designs that need  lesser logic,  alleo for  higher clock rates and simetimes some tweeks in there is only a dozen of logis elements necessare to  decrement the LOOP-setting by one or th squeeze in a second hasher ...