has been put on a leash by his bosses. He stopped posting/insulting people here on the forums
Q: "Are you stating that after the mask set is made, BFL is able to make changes to the design and add circuits (like clock buffers) without have to start the whole set of wafers again?"
Inaba: "I can't really comment on this because it's part of our Unicorn Blood recipe. I'm sure the trolls will have a field day with this statement... All I have to say to that is: Have fun on 110nm suckas!"
E.g. in the way BitSyncom/Avalon did recently:
This update is mainly to address the uncertainty that have been surrounding the ASIC scene recently due to the lackluster performance by our competitors. We will be walking you through our process of getting the ASIC fabricated. Unlike our competitors we are a in-house team and everyone is always on the same page.
Another update will address the actual status of our chips as we have obtained word from TSMC whom will offer us weekly updates on their website. All in all, see our arguments below regarding our competitors and wait for weekly updates directly from TSMC.
Anyhow, any of our numbers, estimates, and shipping date have not changed, just in case somebody got the wrong idea about this update.
First things first. the following Gallery is our contract with TSMC with pricing and other sensitive information removed.
http://imgur.com/a/DnUNm
Some background information on ASIC production process, before tape out, 3 day before uploading
GDS, we fill out a MT form with TSMC detailing the ASIC specific information so they may understand what we are doing. The gallery is here
http://imgur.com/a/YOLez
to put simply, to create the physical ASIC goes something like this.
sign contract -> submit GDS for review -> mask making -> wafer making -> ship to packaging company -> packaging -> shipping.
Only then can the chips be in your hands or placed on PCB for finalization.
This whole process will take 30-50 days depending on the processor node technology used, mainly due to the increasing in layer number as you go down in processor size. for example, we have 29 layers, and since TSMC is one of the big companies in fabrication, each layer take 1.2 ( normal lot ) day per layer. in addition, accordingly to friedcat, their fab is producing 4 layers every week [odd, but I guess it is possible if fab is small].
This also means while you wait for the wafer(chips) fabrication you can not do anything else, it is usually around this time you make sure you have everything else ready.
a few things to note is,
1. while this wafer making process is going, you can't cancel it, or make adjustments, and if you wish to change anything, you will have to re-run this whole work flow all over again ( the large amount of the NRE upwards of 6 digits in USD is paid when you make the MASK). so anytime, BFL mention they are waiting for chips to come e.g.
next week, but if they are
still making adjustments, then this is physically impossible. In addition, fabrication company don't do chip packaging, if they are expecting the chips to arrive next week that means the production is already finished and they are probably in the chip packaging company (it is usually this time you find out if your chips work or not. which can also take some time since you'll have to test each of the chips for defects.)
2. the whole chip fabrication is very mathematically predictable based on the number of layers your ASIC has and the speed which the fabrication company can produce a layer. There is no such thing as a fabrication company giving a "fuzzy" date when it comes to when the chips will come from the assembly line. The only number that can vary is the shipping time from the fabrication company to the packaging company, but even that is no more than a few days of difference, depending on the shipping method.
3.a if bASIC made an MPW to start (which is the correct way to save money, but
not time). the cost to get large amount of chips during this time is astronomical, however the average size is about 50. It is unheard of for somebody to only produce 2 chips to built a prototype and now no longer have any chips left over to build another prototype.
3.b. Even after testing MWP and everything is fine, it'll take the same amount of time to produce a new MASK ( cost and everything ) then make wafers, which will take another 30 - 50 days, which I suppose is consistent with bASIC's new mid-Jan shipping date, ( but this is optimistic estimate, the regular workflow is about 2 month)
3.c. what we think that happened is bASIC has licensed a SHA256 core, the IP company has already produced demo ASICs that utilizes this core, and did some math on how many core you can placed in the chip to obtain the 14GH/s estimated hashrate, while regular SHA256 and Bitcoin's blockchain hashing algorithm is not very different but it is not something you can compare via simulation without making an actual chip, and if they made an actual chip, even if it doesn't perform up to specifications you can still demonstrate it and be world first.
the conclusion is as follows.
1. If BFL really have chips coming, then they are not making any so-to-speak "clock buffer adjustments", either that or they don't have any chips coming and have not tape-out at all, it is also entirely possible that they have not make the MASK yet either. I guess we will find out on the week of the 11th, in this month hopefully.
2. we believe bASIC has no prototype, or have any chips. Also we at Avalon have also explored the possibility of licensing an IP core, but after some in-house comparison, none of the core on the market is superior to our own, thus we eliminated that option.
Questions, Comments are welcome.
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