Gateless Gate Sharp 1.3.8: 30Mh/s (Ethash) on RX 480!

[z97rx470]

Whenever the pool goes down the miner will cause windows to freeze/crash... I have a really hard time getting back running after that as I keep getting a BSOD "Thread stuck in device driver" like 30 seconds after the desktop boots up with nothing running.. It was stable all day until my pool went down now I can't even get back into windows... might have to reformat again

This is no good... Which driver are you using with which card?

I'm using the Radeon Blockchain Compute Driver Version 17.30.1029 for every card.
Managed to get around the BSOD by going in safe mode and disabling overclocking on startup in Afterburner

a 4x port multipler

Ah, an important detail! Thank you. I always wondered about those 4x port multipliers.
Which algo are you using? Are other algos working at all?

I've only tested Claymores ETH+DCR dual miner and Cryptonite and they were running stable until I started running GGS now the other miners aren't even stable anymore :/
is it possible that GGS damaged my hardware? I didn't press boost performance

[zawawa]

I'm using the Radeon Blockchain Compute Driver Version 17.30.1029 for every card.

Well, this is exactly what I was suspecting. I was fairly clear about GGS supporting only Adrenalin 17.12.2 and 18.1.1.
There is not much I can do when you run GGS with a deprecated, unsupported driver.
Maybe I should add a warning about unsupported drivers...

[dadreda]

Does anyone mine ETH on Coinotron? I am not able to connect mining ETH but NeoScrypt no problems. I mine there now with Claymore, I was wanting to try GGS.

[z97rx470]

I'm using the Radeon Blockchain Compute Driver Version 17.30.1029 for every card.

Well, this is exactly what I was suspecting. I was fairly clear about GGS supporting only Adrenalin 17.12.2 and 18.1.1.
There is not much I can do when you run GGS with a deprecated, unsupported driver.
Maybe I should add a warning about unsupported drivers...

Thanks I switched drivers didn't see that part about the driver compatibility and so far so good.

Does the GGS overclock not work? I changed the clock speeds in the devices tab (under the appropriate algorithm) but nothing happens

[zawawa]

I'm using the Radeon Blockchain Compute Driver Version 17.30.1029 for every card.

Well, this is exactly what I was suspecting. I was fairly clear about GGS supporting only Adrenalin 17.12.2 and 18.1.1.
There is not much I can do when you run GGS with a deprecated, unsupported driver.
Maybe I should add a warning about unsupported drivers...

Thanks I switched drivers didn't see that part about the driver compatibility and so far so good.

Does the GGS overclock not work? I changed the clock speeds in the devices tab (under the appropriate algorithm) but nothing happens

It should work. I noticed AfterBurner and even RadeonSettings sometimes interfere with GGS's overclocking feature.
I would stop these processes and see if the problem still persists.

[heavyarms1912]

Hynix MJR memory is very unstable with TRRD=5 but more speedy on cryptonight.
Does anyone knows what straps parameters can make memory more stable?

What about bug with rejected shares after recieving new job before share accepted? Bug is still exists...

And it's need more info about current difficulty and reasons of rejecting shares.

Higher TRFC values should improve stability.  Also, TFAW/TFAW32 to 0 can introduce instability when I had experimented with it.  Might improve hashrate by a notch (happened with Elpida).

[UnclWish]

Hynix MJR memory is very unstable with TRRD=5 but more speedy on cryptonight.
Does anyone knows what straps parameters can make memory more stable?

What about bug with rejected shares after recieving new job before share accepted? Bug is still exists...

And it's need more info about current difficulty and reasons of rejecting shares.

Higher TRFC values should improve stability.  Also, TFAW/TFAW32 to 0 can introduce instability when I had experimented with it.  Might improve hashrate by a notch (happened with Elpida).

Thanks, I'll try it... Higher TRFC lower hashrate? TFAW/TFAW32 to 0 - increase speed?

[heavyarms1912]

Hynix MJR memory is very unstable with TRRD=5 but more speedy on cryptonight.
Does anyone knows what straps parameters can make memory more stable?

What about bug with rejected shares after recieving new job before share accepted? Bug is still exists...

And it's need more info about current difficulty and reasons of rejecting shares.

Higher TRFC values should improve stability.  Also, TFAW/TFAW32 to 0 can introduce instability when I had experimented with it.  Might improve hashrate by a notch (happened with Elpida).

Thanks, I'll try it... Higher TRFC lower hashrate? TFAW/TFAW32 to 0 - increase speed?

Higher TRC/TRFC will reduce the hashrate a bit but improve stability.  Also increase max memory oc capability.
TFAW/TFAW32=0; I am not sure how it impacts.  I had mixed results.  Elpidas were okay. Hynix didn't like it.

[UnclWish]

Hynix MJR memory is very unstable with TRRD=5 but more speedy on cryptonight.
Does anyone knows what straps parameters can make memory more stable?

What about bug with rejected shares after recieving new job before share accepted? Bug is still exists...

And it's need more info about current difficulty and reasons of rejecting shares.

Higher TRFC values should improve stability.  Also, TFAW/TFAW32 to 0 can introduce instability when I had experimented with it.  Might improve hashrate by a notch (happened with Elpida).

Thanks, I'll try it... Higher TRFC lower hashrate? TFAW/TFAW32 to 0 - increase speed?

Higher TRC/TRFC will reduce the hashrate a bit but improve stability.  Also increase max memory oc capability.
TFAW/TFAW32=0; I am not sure how it impacts.  I had mixed results.  Elpidas were okay. Hynix didn't like it.

Yes, hynix mjr didn't like TFAW/TFAW32=0 so as TRRD=5.
Thanks for help.
Another one question: does changing some parameters needs to change others? Is any parameters depends from other? What parameters are linked between each other?

[heavyarms1912]

Hynix MJR memory is very unstable with TRRD=5 but more speedy on cryptonight.
Does anyone knows what straps parameters can make memory more stable?

What about bug with rejected shares after recieving new job before share accepted? Bug is still exists...

And it's need more info about current difficulty and reasons of rejecting shares.

Higher TRFC values should improve stability.  Also, TFAW/TFAW32 to 0 can introduce instability when I had experimented with it.  Might improve hashrate by a notch (happened with Elpida).

Thanks, I'll try it... Higher TRFC lower hashrate? TFAW/TFAW32 to 0 - increase speed?

Higher TRC/TRFC will reduce the hashrate a bit but improve stability.  Also increase max memory oc capability.
TFAW/TFAW32=0; I am not sure how it impacts.  I had mixed results.  Elpidas were okay. Hynix didn't like it.

Yes, hynix mjr didn't like TFAW/TFAW32=0 so as TRRD=5.
Thanks for help.
Another one question: does changing some parameters needs to change others? Is any parameters depends from other? What parameters are linked between each other?

Yup, there are quite a few interdependency.  I am not an expert in RAM timings though.  Will need to read GDDR5 doc.
I try to follow relative pattern on stock timing straps while doing modifications.  If you're off by a lot you would get lots of memory errors within few seconds or crashes.

[Pete_X]

Yes, hynix mjr didn't like TFAW/TFAW32=0 so as TRRD=5.
Thanks for help.
Another one question: (1) does changing some parameters needs to change others? (2) Is any parameters depends from other? (3) What parameters are linked between each other?

(1) Based on what so far is known about the Polaris mctrl: In some cases: Yes

(2) There are for sure relations "inside" the strap and also with Timings that are not in the strap (as the strap does not contain all timings). A Datasheet from an AMD DEV would be more than handy

(3) trfc/trc and so on .. there are a few, but it`s also to see in combination with the diff, vendors of the gddr rams. As there are (again) slight differences. A value that works on samsung, does not on hynix and maybe helps a bit on Elpida and so on ....

Basically it`s the same as on the DDR Rams, just abit more complicated - as the memcontrollers evolved a lot ... much tweaking is without the datasheets just trial and error.

[UnclWish]

Yes, hynix mjr didn't like TFAW/TFAW32=0 so as TRRD=5.
Thanks for help.
Another one question: (1) does changing some parameters needs to change others? (2) Is any parameters depends from other? (3) What parameters are linked between each other?

(1) Based on what so far is known about the Polaris mctrl: In some cases: Yes

(2) There are for sure relations "inside" the strap and also with Timings that are not in the strap (as the strap does not contain all timings). A Datasheet from an AMD DEV would be more than handy

(3) trfc/trc and so on .. there are a few, but it`s also to see in combination with the diff, vendors of the gddr rams. As there are (again) slight differences. A value that works on samsung, does not on hynix and maybe helps a bit on Elpida and so on ....

Basically it`s the same as on the DDR Rams, just abit more complicated - as the memcontrollers evolved a lot ... much tweaking is without the datasheets just trial and error.

How trfc and trc linked between each other? I didn't find any dependens with them... trfc usually is 186,192,206,219. trc is 65,70,73,75.

[Pete_X]

Yes, hynix mjr didn't like TFAW/TFAW32=0 so as TRRD=5.
Thanks for help.
Another one question: (1) does changing some parameters needs to change others? (2) Is any parameters depends from other? (3) What parameters are linked between each other?

(1) Based on what so far is known about the Polaris mctrl: In some cases: Yes

(2) There are for sure relations "inside" the strap and also with Timings that are not in the strap (as the strap does not contain all timings). A Datasheet from an AMD DEV would be more than handy

(3) trfc/trc and so on .. there are a few, but it`s also to see in combination with the diff, vendors of the gddr rams. As there are (again) slight differences. A value that works on samsung, does not on hynix and maybe helps a bit on Elpida and so on ....

Basically it`s the same as on the DDR Rams, just abit more complicated - as the memcontrollers evolved a lot ... much tweaking is without the datasheets just trial and error.

How trfc and trc linked between each other? I didn't find any dependens with them... trfc usually is 186,192,206,219. trc is 65,70,73,75.

Basically: (got a bit rosty on these )
tRFC is the time allowed to refresh a whole memory bank (Time between a ref and the next act command)
tRC is the time allowed for a complete cycle (act, pre etc)
tFAW should be the window for 4 act, 32 etc ....

Reading some JEDEC docs sheds some light on these

[UnclWish]

Yes, hynix mjr didn't like TFAW/TFAW32=0 so as TRRD=5.
Thanks for help.
Another one question: (1) does changing some parameters needs to change others? (2) Is any parameters depends from other? (3) What parameters are linked between each other?

(1) Based on what so far is known about the Polaris mctrl: In some cases: Yes

(2) There are for sure relations "inside" the strap and also with Timings that are not in the strap (as the strap does not contain all timings). A Datasheet from an AMD DEV would be more than handy

(3) trfc/trc and so on .. there are a few, but it`s also to see in combination with the diff, vendors of the gddr rams. As there are (again) slight differences. A value that works on samsung, does not on hynix and maybe helps a bit on Elpida and so on ....

Basically it`s the same as on the DDR Rams, just abit more complicated - as the memcontrollers evolved a lot ... much tweaking is without the datasheets just trial and error.

How trfc and trc linked between each other? I didn't find any dependens with them... trfc usually is 186,192,206,219. trc is 65,70,73,75.

Basically: (got a bit rosty on these )
tRFC is the time allowed to refresh a whole memory bank (Time between a ref and the next act command)
tRC is the time allowed for a complete cycle (act, pre etc)
tFAW should be the window for 4 act, 32 etc ....

Reading some JEDEC docs sheds some light on these

I'm no so strong in english, therefore reading these docs gives me not so much... Automatic translators such specific docs translate very ugly, you know...
Can you give an example on some strap? I would be very greatful!

[zawawa]

Yes, hynix mjr didn't like TFAW/TFAW32=0 so as TRRD=5.
Thanks for help.
Another one question: (1) does changing some parameters needs to change others? (2) Is any parameters depends from other? (3) What parameters are linked between each other?

(1) Based on what so far is known about the Polaris mctrl: In some cases: Yes

(2) There are for sure relations "inside" the strap and also with Timings that are not in the strap (as the strap does not contain all timings). A Datasheet from an AMD DEV would be more than handy

(3) trfc/trc and so on .. there are a few, but it`s also to see in combination with the diff, vendors of the gddr rams. As there are (again) slight differences. A value that works on samsung, does not on hynix and maybe helps a bit on Elpida and so on ....

Basically it`s the same as on the DDR Rams, just abit more complicated - as the memcontrollers evolved a lot ... much tweaking is without the datasheets just trial and error.

How trfc and trc linked between each other? I didn't find any dependens with them... trfc usually is 186,192,206,219. trc is 65,70,73,75.

Basically: (got a bit rosty on these )
tRFC is the time allowed to refresh a whole memory bank (Time between a ref and the next act command)
tRC is the time allowed for a complete cycle (act, pre etc)
tFAW should be the window for 4 act, 32 etc ....

Reading some JEDEC docs sheds some light on these

I'm no so strong in english, therefore reading these docs gives me not so much... Automatic translators such specific docs translate very ugly, you know...
Can you give an example on some strap? I would be very greatful!

There is no way around reading specs if you really want to understand how these timings work.
If you just want a good strap, you can try one of these:

https://github.com/jaschaknack/PolarisBiosEditor/blob/b0bf3c7a80f4e9b35cac244d86e2e66d8e06a137/PolarisBiosEditor.cs

[UnclWish]

Yes, hynix mjr didn't like TFAW/TFAW32=0 so as TRRD=5.
Thanks for help.
Another one question: (1) does changing some parameters needs to change others? (2) Is any parameters depends from other? (3) What parameters are linked between each other?

(1) Based on what so far is known about the Polaris mctrl: In some cases: Yes

(2) There are for sure relations "inside" the strap and also with Timings that are not in the strap (as the strap does not contain all timings). A Datasheet from an AMD DEV would be more than handy

(3) trfc/trc and so on .. there are a few, but it`s also to see in combination with the diff, vendors of the gddr rams. As there are (again) slight differences. A value that works on samsung, does not on hynix and maybe helps a bit on Elpida and so on ....

Basically it`s the same as on the DDR Rams, just abit more complicated - as the memcontrollers evolved a lot ... much tweaking is without the datasheets just trial and error.

How trfc and trc linked between each other? I didn't find any dependens with them... trfc usually is 186,192,206,219. trc is 65,70,73,75.

Basically: (got a bit rosty on these )
tRFC is the time allowed to refresh a whole memory bank (Time between a ref and the next act command)
tRC is the time allowed for a complete cycle (act, pre etc)
tFAW should be the window for 4 act, 32 etc ....

Reading some JEDEC docs sheds some light on these

I'm no so strong in english, therefore reading these docs gives me not so much... Automatic translators such specific docs translate very ugly, you know...
Can you give an example on some strap? I would be very greatful!

There is no way around reading specs if you really want to understand how these timings work.
If you just want a good strap, you can try one of these:

https://github.com/jaschaknack/PolarisBiosEditor/blob/b0bf3c7a80f4e9b35cac244d86e2e66d8e06a137/PolarisBiosEditor.cs

I used this straps allready. For hynix mjr they are not good enough, especially for cryptonight. They are good for ethereum.
I find and edit strap by myself and can reach 1k h/s in cryptonight with hynix 8Gb mjr memory on Nitro+, but it not stable enough... There is no memory errors, but give rejected shares about 3-5% from speed.
Most improtant strap parametr for cryptonight is TRRD. With TRRD=5 and 2000MHz it's easy to have 1k h/s in cryptonight. I think it's not only for hynix mjr.
But hynix mjr became not stable with TRRD=5.
I tried TRFC 198, 206, 219. TRC up to 73. FAW/TFAW32 set to not 0. But it's not helps. GPU continue to give rejects sometime...
Any other suggestions?
And please give me link to JEDEC docs about GDDR5 memory. I'll try to understand how that memory works...

[zawawa]

Here it is!

https://www.jedec.org/sites/default/files/docs/JESD212.pdf

[Pete_X]

Here it is!

https://www.jedec.org/sites/default/files/docs/JESD212.pdf

Yep, also 232, 235 and 250 are kinda usefull ... not to forget 79 regarding the basics of DRAM  


@UnclWish:

tRRD is for example tied to tFAW and tFAW32. The "0" values are for sure not really "0", the Polaris memcontroller "helps" there is fill up. if they would really be "0" we would have a problem - See page 59 of 212C)

Edit: ... and not to forget the temperature aspect. GDDR like to be below 60c - over that you risk instability.

[zawawa]

This f*cking memory timing thing is taking forever, but it is finally getting stable now.
Time to wrap it up...
(These cards are with stock BIOS'es, just in case you are wondering.)
It is only for 480/580/470/480 for now, but support for Vega should come pretty soon...

[Pete_X]

This f*cking memory timing thing is taking forever, but it is finally getting stable now.
Time to wrap it up...
(These cards are with stock BIOS'es, just in case you are wondering.)
It is only for 480/580/470/480 for now, but support for Vega should come pretty soon...

Good stuff m8! Stock Bios should be the way to go, as you need a common base if you start to tweak. Nearly impossible to adapt to all possible variations there might be!

470/480 and 580 are here to give it a wirl