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Author Topic: FPGA development board "Lancelot" - accept bitsteam developer's orders.  (Read 96061 times)
luffy
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November 06, 2012, 05:09:05 PM
 #421

v1 Lancelot (stock voltage) after 10 hours with --icarus-timing long i get better results:
A:3617 R:59 HW:92 U:5.5
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Dexter770221
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November 06, 2012, 09:19:46 PM
 #422

I've done it. Soldered 2x68k in serial on top of original 10k resistor. 1206 packages (I didn't have other values). Voltage jumped from 1.17V to 1.22V. So far so good but I don't see any big improvement... Results later.

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November 07, 2012, 12:32:13 AM
 #423

It is really a magic that all miners are electronic engineers Smiley

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November 07, 2012, 02:38:27 AM
 #424

v1 Lancelot (stock voltage) after 10 hours with --icarus-timing long i get better results:
A:3617 R:59 HW:92 U:5.5
Don't forget that long (and short) depends on how idle the computer is.
long of course will keep correcting that forever, but short stops after a while and uses what it's worked out up to then.

The problem with both is that on a variable clock, it will sometimes be too long ... if the clock goes up by even 2%.
If you have a static clock then no issues, but you can then also use what's described below anyway.

However with a variable clock:

The fix is to actually specify the values.

It doesn't matter if they are a little out - that will only affect the MH/s reported ... as long as it's not too far out.

Try this instead:

--icarus-timing 2:70

2 (2ns) (Hs) means it clocks at 435MH/s (instead of 380MH/s) which just means that the MH/s reported will not be correct
1/(2x10^-9) H/s

70 (7.0s) (read_count) will be OK up to 613MH/s
(2^32/(70/10)) H/s

The issue of the '70' value is it MUST be less than the time it takes to check the full nonce range.
The closer it is to the correct time, the lower the overhead of getting more work.
That overhead is, however, very, very small.
It determines how much of each nonce range is checked (unless a share is found) but aborting early doesn't affect the probability of finding shares.
Normally the '70' (read_count) is calculated from the other Hs value
info->Hs = Hs / NANOSEC;
info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
info->read_count = (int)(info->fullnonce * TIME_FACTOR) - 1;

Hs=2 TIME_FACTOR=10 NANOSEC=10^9

The internal usage of the '2' value ensures correct MH/s display when a share isn't found.

P.S. I failed electrical engineering and got a Comp Sci degree Tongue

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luffy
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November 07, 2012, 07:57:48 AM
 #425

@kano: many thanks, i will try it
@Dexter770221: can you please confirm the registors' location given by rgzen?
thanks
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November 07, 2012, 08:13:02 AM
 #426

Thanks Kano for the additional info about that timings. Propably "long" will report very close to your calculations. After 12 hours U:5.8 (from 5.7), so it's little improvment, however hardware errors dropped to ~3% (previously was ~5%).
Yes luffy, resistors showed by rgzen are correct one.

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November 07, 2012, 09:18:27 AM
 #427

ok!
then what resistor can we solder in parallel with the current one in order to get 1.24v-1.28v?
and what are the pins where we measure the VCC voltage?
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November 07, 2012, 10:07:12 AM
 #428

ok!
then what resistor can we solder in parallel with the current one in order to get 1.24v-1.28v?
and what are the pins where we measure the VCC voltage?


http://www.1728.org/resistrs.htm
Calculation showed about 90-100K
+1 for the question where to measure VCC out core voltage

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Dexter770221
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November 07, 2012, 10:37:06 AM
 #429

ngzhang mentioned that this resistor should be somwhere around 9k. R=(R1*R2)/(R1+R2)=(10*100)/(10+100)=1000/110=9.09k. 100k in parallel should be perfect.
When board is placed in front of you as is on rgzen pictures, 4 holes for measure voltage are placed on the right edge of the board. They are visible on bottom picture, near 270uF capacitor and coil.

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November 07, 2012, 11:02:39 AM
 #430

ngzhang mentioned that this resistor should be somwhere around 9k. R=(R1*R2)/(R1+R2)=(10*100)/(10+100)=1000/110=9.09k. 100k in parallel should be perfect.
When board is placed in front of you as is on rgzen pictures, 4 holes for measure voltage are placed on the right edge of the board. They are visible on bottom picture, near 270uF capacitor and coil.
Hey,
thank you for the update! It seems that you know hardware stuff better than me (i am not expert at all). From what i have seen in pdf (core_power) schematic (i might be wrong of course) we have to measure a voltage VCCINT1V2_A and  VCCINT1V2_B. Is that true? If it is, are the wholes you are referring to equal to "VCCINT1V2_A and  VCCINT1V2_B". If yes, would it be very hard for you just to mark them on the picture, because it is very hard for me to find them out:)
Once again excuse me but as i said i am not an expert at all:)

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Dexter770221
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November 07, 2012, 11:55:23 AM
 #431

http://i.minus.com/iOoHctgIXSDTB.JPG - picture from first post (courtesy of ngzhang).
At the edge of the board you can see 4 holes (right side, white squares around it) labeled GND, V.CORE1, V.CORE2, V.AUX. Those are test points for this voltages. V.AUX is 3,3V for IO.

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November 07, 2012, 12:09:31 PM
 #432

http://i.minus.com/iOoHctgIXSDTB.JPG - picture from first post (courtesy of ngzhang).
At the edge of the board you can see 4 holes (right side, white squares around it) labeled GND, V.CORE1, V.CORE2, V.AUX. Those are test points for this voltages. V.AUX is 3,3V for IO.

Thanks!
I got it...

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November 08, 2012, 09:33:19 PM
 #433

Sixteen hours past since the miner started it throws the following:

(5s):526.7 (avg):483.0 Mh/s | Q:1250  A:5336  R:64  HW:0  E:427%  U:5.7/m

According to my calcs it is more less 411 MH/s or around 8% improvement...
I repeat that I have the first version flashed with the V42 bitstream and the resistors changed and --icarus-timing 2:70 with cgminer 2.7.4.
So I am asking... What are your results with other configurations??

PD: And I have too curiosity of know what are exactly the differences between the first and the second version of the board.
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November 08, 2012, 09:50:46 PM
 #434

After my mod (136k in parallel with 10k resistors, Vcore@1.22V) I'm getting U:5.8, error rate ~3%. It's not big improvement but always it's something. I think that ngzang just posted little modified bitstream with auto adjusted clock, version "handy placed small cores" is still in his possesion and he don't want to share with it...

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November 08, 2012, 10:15:47 PM
 #435

hey
can you tell me with the info I have posted how much is my hardware error rate?Huh
It is possible yo be 0%?
thanks
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November 08, 2012, 10:19:20 PM
 #436

or it can be R/(A+R)? in this case around 1.2%
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November 08, 2012, 10:59:41 PM
 #437

hey
can you tell me with the info I have posted how much is my hardware error rate?Huh
It is possible yo be 0%?
thanks
cgminer before 2.7.6 doesn't report HW: for the Icarus driver.
So you won't known unless you are using 2.7.6 (where I added it) or later.
... preferably the latest version Tongue

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November 09, 2012, 08:44:46 AM
 #438

ok, I have upgrade my software.

thanks
luffy
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November 11, 2012, 07:39:10 AM
 #439

i upgarded too. i noticed that even icarus board without any modifications has a few HW hits although none of my VGAs (7950,5870,5970) has any!
kano
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November 11, 2012, 11:19:16 AM
 #440

i upgarded too. i noticed that even icarus board without any modifications has a few HW hits although none of my VGAs (7950,5870,5970) has any!
I get about 0.2% on my 2 original Icarus boards.

The GPU code always reported HW: errors, but the others didn't.
GPU's often get none - usually only get them when over heating of over clocking too far
(I'm not sure if I've ever had a HW error on one my 6950 GPUs in 16 months - the other one fan failed and got replaced so had a few when that happened)

Anyway, I changed it so all devices (except ztex) go through the same (new) HW check code
(after I realised that it wasn't doing that - which I thought it was in the FPGA code)

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