FPGA development board "Lancelot" - accept bitsteam developer's orders.

[ngzhang]

any news and Q&A will post in this thread.
as we all know, Lancelot is a improvement edition for past "icarus" board. now the hardware design work is nearly finish ), but the firmware development is facing serious difficulties.
i write down what is confirmable and what we are still working at.
please feel free to ask questions, and i will answer what i can answer, if i can't answer right now, i will answer them later.
the design is not finished yet, so if there is any valuable suggestion i will put it into the design.

--------------------------------------------------------------------------------------------------------------------
ADD @ 8/5

accept bitsteam developer's orders.

one set for one person only.

on set include:

1* Lancelot, with standard cooling system, WITHOUT power adapter.
1* DEV kit, with necessary software, documents.
1* EMS shipment Service.

the total price is 500USD.

if you want to place an order, please sent a email to:

ngzhang1983@msn.com

or a PM, or both for a measure.

the message must include : your address.

payment accept MTGOX redeem code and bitcoins.

the shipment date is in 1 week after the payment.

---------------------------------------------------------------------------------------------
ADD some pictures.





---------------------------------------------------------------------------------------------

1st batch production date fixed @ 7/17! quantity is 100. ----already finished, and tested.
bitsteam development reached a milestone. single core running correctly (very small but fast), but overall performance still waiting measurement. maybe will release at about 550MH/s per board, and rise to over 700MH/s after 1-2 bitsteam updates.
pre-order is still NOT acceptable.
price will reduce significantly after batch 2 (hope will have batch 3. )

EXTREMELY busy these days! reviewing HDL codes with other developers to mid night everyday! fix the hardware bugs! do the prepare work for the production! and lots of school works!
apologize for all delay, include mails and messages. will catch up next week..

sample stage reached (@6/6)! doing the hardware test.

some pictures:





notice: all test batch boards are green, and retail products is blue PCB. this is a personal habits.

--------------------------------------------------------------

1, price.

500 USD for one, and will lower up to  20% if your order is large (>50 Pcs).

2, delivery time.
still unknown. hardware will come out in may, first batch delivery will in July.

3, architecture.
XC6SLX150 *2, maybe -2C/ -2I/ -3C/ -N3C speed grade. first batch will be -2I speed grade.

4, speed.
still unknown, our design goal is higher than 550MH/s pre board (-2I speed grade), but.... who knows. certainly, will not slower than icarus.

5, power consume.
better than icarus. (hope for 10-25% more MH/W performance, means 25MH/w)

6, other features.

a, board temperature monitoring.
b, PWM fan control and speed monitoring.
c, standard 6 or 9CM low speed(1200RPM) fan.
d, MCU friendly port for development.
e, 64 GPIOs for general purpose application. plus 8LEDs, 8Switches, 4 push buttons, 24 internal connections.
f, 100 CM^2 PCB size.
g, both 2.5/5.5mm power plug and D-type Molex power connector.
h, 6-layer PCB with 2OZ copper for enhance cooling. special layout design for lower the FPGA core temperature.
i, USB port for communication.
j, ROHS.
k, will compatible with present icarus bitsteam at first.
l, core power module can provide 14A(25A peak) for each FPGA VCCINT, and io power module can provide 6A for VCCIO and VCCAUX (share by 2 FPGAs), all continuous output.
m, 2 milliOHM MOSFET.

7, pre-orders.
not start yet. will start when we begin the first batch's production.

8, cluster model.
our plan is implement a cluster model by a mother board. and will have LAN and WIFI function for independent operation.
but this mother board is still at the beginning stage of development . i hope will have a sample in future 2-3 months.
happily, there is no technical difficulties on this part, only need is to do.

9, about developer tools.
DEV KIT is still available.

10, open source.
hardware will still fully open sourced, software and firmware will have open sourced versions too.
on of ouer plan is to apply a close sourced commercial SHA256 core, but this practice is still under valuation.

11, payment
will same as past, BTCs, MTGOX$, wire, paypal(with 5%plus fee), LR. but NO Dwolla.

12, warranty.
will have a 90 days limited warranty and 1 year repair service with charge.
limited warranty means will have a free repair service for any unartificial caused damage. but NOT include FPGA damage (for any reason) and Artificial damage.

-------------------------------------------------------------------------Small installation guide---------------------------------------------------------

Introduction:

All Lancelot mining board delivery with a default bitsteam, so the boards can operate "out of box".

the Power switch is at the right side of the board, default is OFF. please keep the board OFF when you do the assembling work.


Hardware installation:

1, connect the Power cable, use Molex-D-type connector or 5.5/2.5mm power plug. please do not use both of them.
2, connect the USB cable. notice that computer will not found any new hardware when the board is power OFF.
3, keep the environment cool.
4, turn on the board. the fan will start to operate, and the white LED (DONE1 and DONE2) will light up. and your computer will find some new hardware.

software installation:

1, the only need driver is the FT232R driver, you can download it here:
http://www.ftdichip.com/Drivers/VCP.htm
use the  "Virtual COM Port Drivers".

2, open your device manager, and record the COM port number.

3, download cgminer, i only test the 2.4.1 version.
https://bitcointalk.org/index.php?topic=28402.0

start the program by a .bat file, the following is an example:

Code:

cgminer  -G -o http://pit.deepbit.net:8332 -u ngzhang1983@msn.com_0 -p 1234  -S com6

pause

the "-G" parameter means disable the GPU devices, the "-S com6" parameter indicate the Lancelot mining board is at com port "6". you must change this number to your board number.

you should get the follow screen:

Code:

 
cgminer version 2.4.1 - Started: [2012-08-22 20:29:26]
--------------------------------------------------------------------------------
 (5s):363.9 (avg):253.4 Mh/s | Q:6  A:0  R:0  HW:0  E:0%  U:0.0/m
 TQ: 1  ST: 3  SS: 0  DW: 1  NB: 2  LW: 0  GF: 0  RF: 0
 Connected to http://pit.deepbit.net:8332 with LP as user 4382312@gmail.com_0
 Block: 000002e6078f1b66e8735513a4a298e7...  Started: [20:29:39]
--------------------------------------------------------------------------------
 [P]ool management [S]ettings [D]isplay options [Q]uit
 ICA 0:                | 184.4/253.4Mh/s | A:0 R:0 HW:0 U:0.00/m
--------------------------------------------------------------------------------

 [2012-08-22 20:29:23] Started cgminer 2.4.1
 [2012-08-22 20:29:23] Found 0 ztex board(s)
 [2012-08-22 20:29:23] Probing for an alive pool
 [2012-08-22 20:29:26] Long-polling activated for http://pit.deepbit.net:8332/li
stenChannel
 [2012-08-22 20:29:26] Pool 0 http://pit.deepbit.net:8332 alive
 [2012-08-22 20:29:27] Pool 1 http://mine3.btcguild.com:8332 alive
 [2012-08-22 20:29:27] Long-polling activated for http://mine3.btcguild.com:8332
/LP/
 [2012-08-22 20:29:39] LONGPOLL from pool 0 detected new block

[likuidxd]

Preorders available?

I'd like to see an option to purchase a preconfigured cluster similar to what BFL is doing with their rig boxes, any plans?

[bitlane]

If these ship @ $1/mh/s.....you can count me in for 10-20 Units

I am glad I waited to see this before I ordered something else.

[Dexter770221]

Development version (programming cable, software) will be available?

[trouserless]

will this work with p2pool software (longpoll timing problem)?  This is still a problem with the BFL singles from what I've read.

[ngzhang]

will this work with p2pool software (longpoll timing problem)?  This is still a problem with the BFL singles from what I've read.

this question please ask those miner developers.

[drlatino999]

Count me in for a pair, I need to reduce my power bill. Good luck on the firmware development.

[DiabloD3]

Still no 28nm FPGAs?

[ngzhang]

Still no 28nm FPGAs?

 

next year.

[PsychoticBoy]

Count me in

[psahx]

Curiously watching.

[Hpman]

h, 6-layer PCB with 2OZ copper for enhance cooling. special layout design for lower the FPGA core temperature.

I like this feature, first time i read this within a bitcoin fpga project. In my opinion, the right (only) way to handle 8W? thermal with that lousy chip package. Hopfull other projects will take care too of that.

Hpman

[Dexter770221]

For commercial SHA core bitstream will be encrypted? If so, AES key will be programmed into eFuse? And Vfs pin, RFUSE pin will be connected?
How much current will be available (VCCINT) for each FPGA?

[tgmarks]

So excited for this. Can't wait to get my hands on a few of these.

[Unacceptable]

500+ mh/s for $500 or so??? Even without any warranty I may be in for some 

Good Luck !!!!!!!!

[Raize]

Posting because I have to in order to subscribe.

[bitcoindaddy]

500+ mh/s for $500 or so??? Even without any warranty I may be in for some 

Good Luck !!!!!!!!

Can you explain why you're excited when BFL offers more MH/s/$?  I like having competition, but I'm not getting it?

[freshzive]

500+ mh/s for $500 or so??? Even without any warranty I may be in for some 

Good Luck !!!!!!!!

Can you explain why you're excited when BFL offers more MH/s/$?  I like having competition, but I'm not getting it?

Power consumption should be much lower. In short term, maybe this is not an issue, but in long term as difficulty continues to rise, it will become a huge factor.

[drlatino999]

500+ mh/s for $500 or so??? Even without any warranty I may be in for some  

Good Luck !!!!!!!!

Can you explain why you're excited when BFL offers more MH/s/$?  I like having competition, but I'm not getting it?

For myself, it's lead time. I have a feeling that when Lancelot is ready for production that I will place an order and within a month I will receive a product. With BFL, it's an unknown wait time.

[allinvain]

You can bet your ass I'm subscribed.

[simon66]

Subbed. Also, will you be posting any CAD pics? Thanks

[simon66]

So will this 2 a double or Quad fpga? Just wondering.

[seriouscoin]

So will this 2 a double or Quad fpga? Just wondering.

do you have problem reading simon? its on the fcking OP.

[1l1l11ll1l]

So will this 2 a double or Quad fpga? Just wondering.

do you have problem reading simon? its on the fcking OP.

wow.

[friedcat]

1 MH/$ is way less than I expected, but still very good!

Expect a rally of mining difficulty, guys.

[Serenata]

1, price.
500 USD for one, and will lower up to  20% if your order is large.

Will you be accepting Bitcoins (and/or other payment methods) this time?

[Philj]

just tell me where to throw my BTC at

[nelisky]

That's pretty amazing. Here's hoping you pull it off

[seriouscoin]

Its better than Icarus but i dont understand why not offering quad FPGAs. Much cleaner setup, less power cables, and USB cables.

[ngzhang]

Its better than Icarus but i dont understand why not offering quad FPGAs. Much cleaner setup, less power cables, and USB cables.

because we have a future plan, set up a rig by 8-16 Lancelot on a single mother board (which is less than 200USD cost), this cluster only have one 220V power plug and LAN ports (RJ45 and WIFI).
so until now, i still consider 2 FPGAs pre board is the best structure for balance the cost, size, yield, etc.

Temperature and fan control would be a huge improvement over Icarus.

Any changes to the protocol? ACKs when jobs are done?  or still waiting up to 11 secs for response?

i must say, icarus protocol is simple but efficient. by this protocol, one 20$ router can handle up to 70 icarus boards with a CPU usage under 10%. why all of you think we must improve this protocol? 
certainly.... i must do some modify to support added functions.

[gyverlb]

Temperature and fan control would be a huge improvement over Icarus.

Any changes to the protocol? ACKs when jobs are done?  or still waiting up to 11 secs for response?

i must say, icarus protocol is simple but efficient. by this protocol, one 20$ router can handle up to 70 icarus boards with a CPU usage under 10%. why all of you think we must improve this protocol? 
certainly.... i must do some modify to support added functions.

Does it work well with p2pool (with new workbase given on average every 10 seconds) ? GPU miners can choose the amount of work given to a GPU to control the latency which makes most of them able to work well on p2pool, is something equivalent already available or planned for the icarus protocol ?

[ngzhang]

Temperature and fan control would be a huge improvement over Icarus.

Any changes to the protocol? ACKs when jobs are done?  or still waiting up to 11 secs for response?

i must say, icarus protocol is simple but efficient. by this protocol, one 20$ router can handle up to 70 icarus boards with a CPU usage under 10%. why all of you think we must improve this protocol? 
certainly.... i must do some modify to support added functions.

Does it work well with p2pool (with new workbase given on average every 10 seconds) ? GPU miners can choose the amount of work given to a GPU to control the latency which makes most of them able to work well on p2pool, is something equivalent already available or planned for the icarus protocol ?

certainly. this protocol can push new work to FPGAs at any time. and FPGA will handle it at that time.

[Raize]

If I were to give you enough money to purchase 30 Icarus and 30 Lancelot miners today, what would be your estimated delivery date for both orders given everything you have today? (I do realize you still have a lot of development and it might be hard to estimate, but I figure it is still worth asking, in case I want to purchase Icarus for possible use or resale.) Thanks.

[Unacceptable]

500+ mh/s for $500 or so??? Even without any warranty I may be in for some 

Good Luck !!!!!!!!

Can you explain why you're excited when BFL offers more MH/s/$?  I like having competition, but I'm not getting it?

Well,as you know BFL's shipping time is,hhmm,slow........& the lower wattage of Lancelot is a +.

But mostly,all but BFL's hash rates are pretty low=long ROI.Almost $600 for 300+ mh/s takes close to 15 months to recoup investment.

I hope to encourage higher hash rates by investing

Also being unemployed,I can only come up with $500-$600 a pop 

[simon66]

500+ mh/s for $500 or so??? Even without any warranty I may be in for some  

Good Luck !!!!!!!!

Can you explain why you're excited when BFL offers more MH/s/$?  I like having competition, but I'm not getting it?

Well,as you know BFL's shipping time is,hhmm,slow........& the lower wattage of Lancelot is a +.

But mostly,all but BFL's hash rates are pretty low=long ROI.Almost $600 for 300+ mh/s takes close to 15 months to recoup investment.

I hope to encourage higher hash rates by investing

Also being unemployed,I can only come up with $500-$600 a pop  

Yea but you can save up and buy a BFL single. Lancelot should've been at least 4 Spartans. There are 3 competitors that offer good prices (Well 1 out of 3)

1: https://bitcointalk.org/index.php?topic=49180.0    <----- $1,359.00
2: https://bitcointalk.org/index.php?topic=79114.0    <----- $1,069.99
3: https://bitcointalk.org/index.php?topic=78239.0    <----- $640

All these are Quads. They also got doubles.

PS. Kinda have to go, I'll post more info soon. Don't kill me just yet lol.

[DiabloD3]

500+ mh/s for $500 or so??? Even without any warranty I may be in for some  

Good Luck !!!!!!!!

Can you explain why you're excited when BFL offers more MH/s/$?  I like having competition, but I'm not getting it?

Well,as you know BFL's shipping time is,hhmm,slow........& the lower wattage of Lancelot is a +.

But mostly,all but BFL's hash rates are pretty low=long ROI.Almost $600 for 300+ mh/s takes close to 15 months to recoup investment.

I hope to encourage higher hash rates by investing

Also being unemployed,I can only come up with $500-$600 a pop  

Yea but you can save up and buy a BFL single. Lancelot should've been at least 4 Spartans. There are 3 competitors that offer good prices (Well 1 out of 3)

1: https://bitcointalk.org/index.php?topic=49180.0    <----- $1,359.00
2: https://bitcointalk.org/index.php?topic=79114.0    <----- $1,069.99
3: https://bitcointalk.org/index.php?topic=78239.0    <----- $640

All these are Quads. They also got doubles.

PS. Kinda have to go, I'll post more info soon. Don't kill me just yet lol.

Small problem, BFLs use twice as much power per mhash and thus take much longer to pay themselves off, and you also have to start paying attention to cooling problems as well.

[TheSeven]

500+ mh/s for $500 or so??? Even without any warranty I may be in for some 

Good Luck !!!!!!!!

Can you explain why you're excited when BFL offers more MH/s/$?  I like having competition, but I'm not getting it?

Simple as that: They must have found a way to get chips that usually cost $2000-4000 each for less than $200.

[DiabloD3]

500+ mh/s for $500 or so??? Even without any warranty I may be in for some 

Good Luck !!!!!!!!

Can you explain why you're excited when BFL offers more MH/s/$?  I like having competition, but I'm not getting it?

Simple as that: They must have found a way to get chips that usually cost $2000-4000 each for less than $200.

Some people think they've found a source for used or unwanted chips, which is pretty sneaky^Wbusiness savvy.

[drlatino999]

500+ mh/s for $500 or so??? Even without any warranty I may be in for some 

Good Luck !!!!!!!!

Can you explain why you're excited when BFL offers more MH/s/$?  I like having competition, but I'm not getting it?

Well,as you know BFL's shipping time is,hhmm,slow........& the lower wattage of Lancelot is a +.

But mostly,all but BFL's hash rates are pretty low=long ROI.Almost $600 for 300+ mh/s takes close to 15 months to recoup investment.

I hope to encourage higher hash rates by investing

Also being unemployed,I can only come up with $500-$600 a pop 

Yea but you can save up and buy a BFL single. Lancelot should've been at least 4 Spartans. There are 3 competitors that offer good prices (Well 1 out of 3)

1: https://bitcointalk.org/index.php?topic=49180.0    <----- $1,359.00
2: https://bitcointalk.org/index.php?topic=79114.0    <----- $1,069.99
3: https://bitcointalk.org/index.php?topic=78239.0    <----- $640

All these are Quads. They also got doubles.

PS. Kinda have to go, I'll post more info soon. Don't kill me just yet lol.

Small problem, BFLs use twice as much power per mhash and thus take much longer to pay themselves off, and you also have to start paying attention to cooling problems as well.

So I looked into the power issue, and say that the BFL does produce 832MH/s @ 80 watts. Hardware break even is 328 days. Lancelot if it pushes 500MH/s @ 25 watts. 1 year, 102 days. This is with the current price of BTC and a 0.103 kw/h cost of electricity. If the calculator is wrong, sue me - http://bitcoinx.com/profit/index.php

[simon66]

OP please don't kill me lol. I know that you're trying to sell your product and at 250mh/s per chip is not that bad. I said something about your board still being under production. I think you should up it up with 4 fpga's on to it. That's about 1gh/s at @ ~50 watts (I think lol).

[DiabloD3]

500+ mh/s for $500 or so??? Even without any warranty I may be in for some  

Good Luck !!!!!!!!

Can you explain why you're excited when BFL offers more MH/s/$?  I like having competition, but I'm not getting it?

Well,as you know BFL's shipping time is,hhmm,slow........& the lower wattage of Lancelot is a +.

But mostly,all but BFL's hash rates are pretty low=long ROI.Almost $600 for 300+ mh/s takes close to 15 months to recoup investment.

I hope to encourage higher hash rates by investing

Also being unemployed,I can only come up with $500-$600 a pop  

Yea but you can save up and buy a BFL single. Lancelot should've been at least 4 Spartans. There are 3 competitors that offer good prices (Well 1 out of 3)

1: https://bitcointalk.org/index.php?topic=49180.0    <----- $1,359.00
2: https://bitcointalk.org/index.php?topic=79114.0    <----- $1,069.99
3: https://bitcointalk.org/index.php?topic=78239.0    <----- $640

All these are Quads. They also got doubles.

PS. Kinda have to go, I'll post more info soon. Don't kill me just yet lol.

Small problem, BFLs use twice as much power per mhash and thus take much longer to pay themselves off, and you also have to start paying attention to cooling problems as well.

So I looked into the power issue, and say that the BFL does produce 832MH/s @ 80 watts. Hardware break even is 328 days. Lancelot if it pushes 500MH/s @ 25 watts. 1 year, 102 days. This is with the current price of BTC and a 0.103 kw/h cost of electricity. If the calculator is wrong, sue me - http://bitcoinx.com/profit/index.php

The calculator is wrong because although it uses historical conditions to predict the future, it doesn't predict a realistic window.

Now, if you believe the calculator is correct:

BFL's peak profit is at 47 months at $490.04.
Lancelot's peak profit is 57 months at $243.54.

So, yes, the BFL will provide the best deal. You make twice as much.

For Lancelot to be an equiv deal, it will need to cost about $250.

Now, in comparison, BTCFPGA ModMiner is 800 mhash @ 40 watts for $1070
ZTEX 1.15y is 850 mhash @ 38 watts for $1359

Modminer's peak profit is at 57 months at $119.61
1.15y's peak profit is at at 60 months at... negative $75.37. Thats right, the best you can do is lose $75.37.

Oh, and GPU mining? Lets say $400 for mobo, cpu, mem, psu, $550 for 7970, 250 watts usage at 1125mhz, 675 mhash each, four 7970s: 2700 mhash @ 1050 watts for $2600 or so. Peak profit is a loss of $917.51 at 24 months.

Edit:

BFL MiniRig is 25200 mhash @ 1250 watts for $15,295
BFL MiniRig's peak profit is at 57 months at $22222.48

[Unacceptable]

500+ mh/s for $500 or so??? Even without any warranty I may be in for some  

Good Luck !!!!!!!!

Can you explain why you're excited when BFL offers more MH/s/$?  I like having competition, but I'm not getting it?

Well,as you know BFL's shipping time is,hhmm,slow........& the lower wattage of Lancelot is a +.

But mostly,all but BFL's hash rates are pretty low=long ROI.Almost $600 for 300+ mh/s takes close to 15 months to recoup investment.

I hope to encourage higher hash rates by investing

Also being unemployed,I can only come up with $500-$600 a pop  

Yea but you can save up and buy a BFL single. Lancelot should've been at least 4 Spartans. There are 3 competitors that offer good prices (Well 1 out of 3)

1: https://bitcointalk.org/index.php?topic=49180.0    <----- $1,359.00
2: https://bitcointalk.org/index.php?topic=79114.0    <----- $1,069.99
3: https://bitcointalk.org/index.php?topic=78239.0    <----- $640

All these are Quads. They also got doubles.

PS. Kinda have to go, I'll post more info soon. Don't kill me just yet lol.

Yes,I have already ordered one single & have mined enough for half of another.By the time I get my single (in 3 weeks,maybe) I should have about $400 towards the next one

I have 2 6950's & 2 6970's already paid for,mining towards singles.So the BFL ROI for me is about 4 months.

Quads are out of reach,too much cash to layout at once,until I have at least 6 BFL singles or a mix of FPGA's (Lancelot).This is the second best bang for the buck,IMO.

I just can't justify,this is my opinon again,anything with less than 1 mh/s per dollar.The ROI is way too long.

  I respect the opinon's of others,even if they differ from mine...........& most do

ngzhang,good luck.Thanks for getting your product "down to earth",pricewise & mh/s wise

[ngzhang]

If I were to give you enough money to purchase 30 Icarus and 30 Lancelot miners today, what would be your estimated delivery date for both orders given everything you have today? (I do realize you still have a lot of development and it might be hard to estimate, but I figure it is still worth asking, in case I want to purchase Icarus for possible use or resale.) Thanks.

the answer is: we no longer accept icarus orders, and Lancelot is not have no delivery schedule now.

OP please don't kill me lol. I know that you're trying to sell your product and at 250mh/s per chip is not that bad. I said something about your board still being under production. I think you should up it up with 4 fpga's on to it. That's about 1gh/s at @ ~50 watts (I think lol).

 

i think you will (or most of have this viewpoint) will change their mind after 1 month time form now. i still have some secrets.

[Raize]

Ahh, OK. I'm sorry, I thought you still accepted bulk orders.

[rudrigorc2]

this thread is serious business , subd! 

[rjk]

this thread is serious business , subd! 

Sub for srs bsns.

[Brunic]

this thread is serious business , subd! 

Sub for srs bsns.

+1?

No...we must not hijack the thread like we did with GPUMAX...

[DiabloD3]

I've updated all the numbers on whos most profitable:

https://bitcointalk.org/index.php?topic=77469.msg887606#msg887606

ATM Lancelot is the most cost effective after BFL's huge lead.

[Dhomochevsky]

Do you still plan on making the Lancelot bitstream backwards compatible with Icarus? I didn't see a mention about that in your OP and thought to ask.

[Syke]

I've updated all the numbers on whos most profitable:

https://bitcointalk.org/index.php?topic=77469.msg887606#msg887606

ATM Lancelot is the most cost effective after BFL's huge lead.

Can you add this one:

https://bitcointalk.org/index.php?topic=78239.0

[DiabloD3]

I've updated all the numbers on whos most profitable:

https://bitcointalk.org/index.php?topic=77469.msg887606#msg887606

ATM Lancelot is the most cost effective after BFL's huge lead.

Can you add this one:

https://bitcointalk.org/index.php?topic=78239.0

Added. It just barely beats the BFL single, but doesn't beat BFL minirigs.

[stcupp]

I've updated all the numbers on whos most profitable:

https://bitcointalk.org/index.php?topic=77469.msg887606#msg887606

ATM Lancelot is the most cost effective after BFL's huge lead.

Can you add this one:

https://bitcointalk.org/index.php?topic=78239.0

Added. It just barely beats the BFL single, but doesn't beat BFL minirigs.

you might also want to add that the price of that board will be double or $1280 from what I can tell, if its not ordered before June.

[DiabloD3]

I've updated all the numbers on whos most profitable:

https://bitcointalk.org/index.php?topic=77469.msg887606#msg887606

ATM Lancelot is the most cost effective after BFL's huge lead.

Can you add this one:

https://bitcointalk.org/index.php?topic=78239.0

Added. It just barely beats the BFL single, but doesn't beat BFL minirigs.

you might also want to add that the price of that board will be double or $1280 from what I can tell, if its not ordered before June.

Heh, if it is, then why are they bothering to produce it, no one will buy it.

[stcupp]

I've updated all the numbers on whos most profitable:

https://bitcointalk.org/index.php?topic=77469.msg887606#msg887606

ATM Lancelot is the most cost effective after BFL's huge lead.

Can you add this one:

https://bitcointalk.org/index.php?topic=78239.0

Added. It just barely beats the BFL single, but doesn't beat BFL minirigs.

you might also want to add that the price of that board will be double or $1280 from what I can tell, if its not ordered before June.

Heh, if it is, then why are they bothering to produce it, no one will buy it.

Why do you say that?

Ztex's quad is $1359 and people are buying it.....

[DiabloD3]

I've updated all the numbers on whos most profitable:

https://bitcointalk.org/index.php?topic=77469.msg887606#msg887606

ATM Lancelot is the most cost effective after BFL's huge lead.

Can you add this one:

https://bitcointalk.org/index.php?topic=78239.0

Added. It just barely beats the BFL single, but doesn't beat BFL minirigs.

you might also want to add that the price of that board will be double or $1280 from what I can tell, if its not ordered before June.

Heh, if it is, then why are they bothering to produce it, no one will buy it.

Why do you say that?

Ztex's quad is $1359 and people are buying it.....

BFL's is the same mhash for half the non-preorder price of that Enterpoint board. Thats why I say that.

[rjk]

BFL's is the same mhash for half the non-preorder price of that Enterpoint board. Thats why I say that.

BFL is very expensive to import to Europe due to taxes and stuff, and European power is often very expensive as well. They will probably have buyers aplenty.

[seriouscoin]

I've updated all the numbers on whos most profitable:

https://bitcointalk.org/index.php?topic=77469.msg887606#msg887606

ATM Lancelot is the most cost effective after BFL's huge lead.

Can you add this one:

https://bitcointalk.org/index.php?topic=78239.0

Added. It just barely beats the BFL single, but doesn't beat BFL minirigs.

you might also want to add that the price of that board will be double or $1280 from what I can tell, if its not ordered before June.

50% increase = double?

Must be some nerd-wannabe's math skill

[PatrickHarnett]

I've updated all the numbers on whos most profitable:

https://bitcointalk.org/index.php?topic=77469.msg887606#msg887606

ATM Lancelot is the most cost effective after BFL's huge lead.

Can you add this one:

https://bitcointalk.org/index.php?topic=78239.0

Added. It just barely beats the BFL single, but doesn't beat BFL minirigs.

you might also want to add that the price of that board will be double or $1280 from what I can tell, if its not ordered before June.

I'm not sure where the $1280 price comes from, but they do say they are producing at cost (no profit margin) - they are only doing that for two months.

The 50% increase will take it to $960, and would allow for some profit.

[Gomeler]

I've updated all the numbers on whos most profitable:

https://bitcointalk.org/index.php?topic=77469.msg887606#msg887606

ATM Lancelot is the most cost effective after BFL's huge lead.

Can you add this one:

https://bitcointalk.org/index.php?topic=78239.0

Added. It just barely beats the BFL single, but doesn't beat BFL minirigs.

you might also want to add that the price of that board will be double or $1280 from what I can tell, if its not ordered before June.

I'm not sure where the $1280 price comes from, but they do say they are producing at cost (no profit margin) - they are only doing that for two months.

The 50% increase will take it to $960, and would allow for some profit.

and if Enterpoint can deliver their product at the pace that ZTEX does with a price between ZTEX and BFL then I am sure they'll sell a bundle of their boards. It'll be even better if the hashing rate per Spartan 6 core increases with future development on that bitstream. To top it off, 1 year warranty. I'm happy 

[Garr255]

Scribed.

[O_Shovah]

I Will provide the watercooling as soon as i get the board drawings

[kano]

BFL's is the same mhash for half the non-preorder price of that Enterpoint board. Thats why I say that.

BFL is very expensive to import to Europe due to taxes and stuff, and European power is often very expensive as well. They will probably have buyers aplenty.

... and the OBVIOUS thing that MOST people seem to completely ignore is that when you buy a BFL you have to pay for it months before you get it.
... and the OBVIOUS point there is that during those months you are not mining - whereas if you buy another device and mine you are effectively reducing the comparative cost price of the other device ... and we are not talking a small amount of dollars either.

[kano]

will this work with p2pool software (longpoll timing problem)?  This is still a problem with the BFL singles from what I've read.

No idea why this question has been asked here more than once.
It is a problem ONLY with BFL singles (the BFL designers were BTC noobs ... and still seem to be)
It is not a problem with Icarus and obviously it will not be a problem with Lancelot

[nedbert9]

BFL's is the same mhash for half the non-preorder price of that Enterpoint board. Thats why I say that.

BFL is very expensive to import to Europe due to taxes and stuff, and European power is often very expensive as well. They will probably have buyers aplenty.

... and the OBVIOUS thing that MOST people seem to completely ignore is that when you buy a BFL you have to pay for it months before you get it.
... and the OBVIOUS point there is that during those months you are not mining - whereas if you buy another device and mine you are effectively reducing the comparative cost price of the other device ... and we are not talking a small amount of dollars either.

True.  However, for my expenses the ROI is at least 1 month shorter with BFL - including opportunity cost.

Give me an open source option that can compete head to head with BFL and I will be very happy about purchasing it.

Hope people start putting money toward OpenBitASIC.  If they can do what they are saying it'd be one hell of an open solution.

[O_Shovah]

Hello everybody,

I found the BFL shipping to become more in time lately.

Nontheless I am also courious  for the lancelot plattform.
I guess i will create an alternative water cooling for it like i did for the Bitforce Box and the x6500.


In the meantime you might find this spreadsheet i created usefull for claculating costs and uses:

The Bitcoin mine or invest spreadsheet & mining rig comparison spreadsheet

[ngzhang]

pull out today.
looks like we will have a sample in 2-3 weeks...

[arklan]

all my BTC are belong to zhang, i think. (meaning, do want lancelot as my first FPGA.)

[eckmar]

...
1, price.

500 USD for one, and will lower up to  20% if your order is large.
...

So I assume -20% is at a bulk order of 30?
Could these 30 later on be used on the motherboard which will come in the future?

If both answers are YES, please keep me in mind for your preorder.

Sunny regards from holiday island Koh Samui,
 Eckmar

[ngzhang]

...
1, price.

500 USD for one, and will lower up to  20% if your order is large.
...

So I assume -20% is at a bulk order of 30?
Could these 30 later on be used on the motherboard which will come in the future?

If both answers are YES, please keep me in mind for your preorder.

Sunny regards from holiday island Koh Samui,
 Eckmar

  are the repaired boards working well? 

both answers are YES.

[eckmar]

Hi Ngzhang,

...
  are the repaired boards working well?  
...

Did you not receive my "thanks" Email to your Gmail address?
It has worked fine a few times, so I assumed that you received it even I did never got a response to my question if I could tell your repair success story here in the forum.
But because you are now writing your question here in the board and not as PM, I am assuming I could tell the public about it.

So here we go:
I really like your attitude and do business with you.
You are a honest and reliable guy and still take care about your products after selling them!
Even with shipments you are flexible and split my shipment bulk order of 30 Icarus boards into two parts, so that the total value of each shipment stayed below 10.000 US$. (Here in Thailand you have to pay some "under the table money to customs" for shipments above 10k US$, so even this was not YOUR problem you had split the shipment to solve MY problem. Thanks again for this!)

After installing the 30 boards, 22 worked fine but 8 failed to work.
So at the beginning I was a bit disappointed about the failure rate of your products.
But you asked me to send the 8 boards back to you and investigate the problem.
After X-Ray you found out that on most boards the UART (USB chip) was damaged and because you test all boards before shipment, I now assume that my Thai stuff did something wrong when installing.
You repaired 7 from 8 boards (on one board the two FPGAs chips were out of order, so no repair make sense) for free and I got back to you saying 1.000 times thank you and asked you about if I can publish this story or not. I wonder why this Email did not pass, because three one did it before.
(In future I will stick to PM over this board.)

Anyway to summaries the hole story:
1.) Flexible and fast shipment to Thailand (no Tax, because of ASIAN!)
2.) Good support after sale (very important for me!)
3.) Good quality of products (assuming now that something went terrible wrong with the installation on our side!)
4.) 29 Icarus boards are running fine and I am happy with them!

So please consider me for the first batch of your new product as a customer again!
I would like to order again 30 boards to take advantage of the 20% discount price, but I am not sure how big your first batch is, so I am willing to take everything you can afford.

A happy and satisfied customer,
 Eckmar

[ngzhang]

 

oh, looks like the mail lost again!

  i pleased about everything goes well.

[eckmar]

...
  i pleased about everything goes well.

Yes, I am too.

And I am looking forward to Lancelot.
Could you tell us how big the first batch will be?
Or is this still a secret?
Could I get 30 Lancelot boards or how much do you think I could get from the first batch?

Cu,
 Eckmar

[arklan]

any updates?

[ngzhang]

any updates?

yeah, some updates.
1:
firmware development is still underway, we hope it will be faster than BitFury Design. but i think everyone know about the difficulty now.

2:
get the PCBs yesterday, will do a trial-production next week (maybe on next Thursday i think, i need to wait for factory scheduling ). after that will do a PCB design revise, then push it to a low-volume production.

3:
pre-orders will be taken after both the firmware and hardware development is over.

 

[arklan]

wohoo! very exciting.

[rudrigorc2]

Any word if the new bitstream will be compatible with the Icarus boards? It would be really nice to get a slight bump in performance if cooling won't become an issue.

it is written on the first post

6, other features.

a, board temperature monitoring.
b, PWM fan control and speed monitoring.
c, standard 9CM low speed(1200RPM) fan.
d, MCU friendly port for development.
e, 64 GPIOs for general purpose application. plus 8LEDs, 8Switches, 4 push buttons, 24 internal connections.
f, 100 CM^2 PCB size.
g, both 2.5/5.5mm power plug and D-type Molex power connector.
h, 6-layer PCB with 2OZ copper for enhance cooling. special layout design for lower the FPGA core temperature.
i, USB port for communication.
j, ROHS.
k, will compatible with present icarus bitsteam at first.
l, core power module can provide 12A for each FPGA VCCINT, and io power module can provide 6A for VCCIO and VCCAUX (share by 2 FPGAs), all continuous output.
m, 2 milliOHM MOSFET.

[Garr255]

...at first.

Elaborate please.

[ngzhang]

...at first.

Elaborate please.

there are some differences between both designs, so at first we will announce a update bitsteam for icarus ,  but will slower than Lancelot. this bitsteam will also used for Lancelot testing.
the reason is Lancelot have some special designs for power and heat dissipation, also some more parts for more functions.

notice that  BitFury Design have a high license fee for their bitsteam, but icarus bitsteam update will be free.

Lancelot will also have free bitsteam update Forever.

 

[Garr255]

Sounds good!

I'm looking forward to seeing how Lancelot will compete with all of the newer FPGAs and possibly ASICs being thrown into the market.

[ngzhang]

Sounds good!

I'm looking forward to seeing how Lancelot will compete with all of the newer FPGAs and possibly ASICs being thrown into the market.

ASICs will fuck all FGPAs to shit.

[Garr255]

Sounds good!

I'm looking forward to seeing how Lancelot will compete with all of the newer FPGAs and possibly ASICs being thrown into the market.

...

Probably not the best advertisement for your new product, so I won't quote you

But yes, sadly that is the truth. It's too bad we didn't figure out how to utilize FPGAs earlier.

[Garr255]

So the real contest is time; 28nm vs ASICs.

[ngzhang]

So the real contest is time; 28nm vs ASICs.

no, i mean:

130nm ASICs will fuck 28 nm FPGAs to shit. 

[Garr255]

So the real contest is time; 28nm vs ASICs.

no, i mean:

130nm ASICs will fuck 28 nm FPGAs to shit. 

Haha, yes I know they will, but if the 28nms come out before the ASICs they will at least have a chance of entering the market

[arklan]

we don't expect ASIC's for a couple years though, as i understand it. or am i incorrect?

[Garr255]

we don't expect ASIC's for a couple years though, as i understand it. or am i incorrect?

It all depends on how much money someone will put toward ASIC development

[ngzhang]

So the real contest is time; 28nm vs ASICs.

no, i mean:

130nm ASICs will fuck 28 nm FPGAs to shit. 

Haha, yes I know they will, but if the 28nms come out before the ASICs they will at least have a chance of entering the market

no, i think 28nm FPGAs will never have chance.

too many things will happen in 2013 and 2014.

[kano]

...at first.

Elaborate please.

there are some differences between both designs, so at first we will announce a update bitsteam for icarus ,  but will slower than Lancelot. this bitsteam will also used for Lancelot testing.
the reason is Lancelot have some special designs for power and heat dissipation, also some more parts for more functions.

notice that  BitFury Design have a high license fee for their bitsteam, but icarus bitsteam update will be free.

Lancelot will also have free bitsteam update Forever.

 

Well my latest version of the Icarus code waiting to go into cgminer should either just work with this or maybe with minor changes

The minor changes would be if it must be mined differently to the way the Icarus currently works

The latest version allows specifying the hash speed (standard Icarus Rev3 is 2.6316ns) and the timeout/abort time (11.2s is optimal)
It will also calculate these accurately for you in either of 2 optional 'timing' modes, if you don't know what they are (that's how I got the 2.6316ns)
It should have no problems on a dual FPGA up to 840MH/s

... though, I've still yet to hear from anyone try it on an Icarus with a non-standard bitstream or a non Rev3 Icarus ...

[Garr255]

So the real contest is time; 28nm vs ASICs.

no, i mean:

130nm ASICs will fuck 28 nm FPGAs to shit. 

Haha, yes I know they will, but if the 28nms come out before the ASICs they will at least have a chance of entering the market

no, i think 28nm FPGAs will never have chance.

too many things will happen in 2013 and 2014.

These things are what I'm excited to see. I need to get some sleep now!

[rudrigorc2]

So the real contest is time; 28nm vs ASICs.

no, i mean:

130nm ASICs will fuck 28 nm FPGAs to shit.  

Haha, yes I know they will, but if the 28nms come out before the ASICs they will at least have a chance of entering the market

no, i think 28nm FPGAs will never have chance.

too many things will happen in 2013 and 2014.

These things are what I'm excited to see. I need to get some sleep now!

Have a good nap, pal. But please just do not sleep till 2013!  haha

[bitfury]

So the real contest is time; 28nm vs ASICs.

no, i mean:

130nm ASICs will fuck 28 nm FPGAs to shit. 

Haha, yes I know they will, but if the 28nms come out before the ASICs they will at least have a chance of entering the market

no, i think 28nm FPGAs will never have chance.

too many things will happen in 2013 and 2014.

These things are what I'm excited to see. I need to get some sleep now!

About 28 nm FPGAs chances... I've counted approximately translation of FPGA into ASIC. for example if my design translated - it would get approximately 8.7 million transistors count. And it is comparable to Pentium II design, so what we have with Spartan-6 0.045 um (45 nm) is what you could get if you squeeze hard into 0.35 um ASIC.

But squeezing design so hard into ASIC would be difficult, as many errors will happen on the way. It is LIKELY that builders of ASICs would squeeze more or less kind of simple VHD design, which would give approx. 3 times worse performance, and then start gradually improve technology with about 3-4 month iteration with each try. I think ngzhang understands well, what design mistakes - when in simulators it works but in hardware does not means when it gets to ASIC production.

So back to issue about ASIC vs FPGA - I suppose that 45 nm equivalent FPGA of Spartan6 class like 0.18 um ASIC.
Then 28 nm FPGA Artix7 could be like 0.112 um ASIC (if just counted, but I suppose comparable to 90 nm more, because it has CARRY CHAIN IN EVERY SLICE, AND I HAVE ROUND DESIGN THAT USES THIS FACT, AND WHICH IS 20% smaller Spartan6 is really bad with their Slice X stuff).

Then interesting thing about FPGA prices. They will fall if volumes will be bulk. This is why I am insisting on making FPGA-based products better, with better pricing - to make it at least competitive against ASICs.

Also - costs for chip production for vendor like Xilinx or Altera is not that much than silicon costs.... So production Spartan6 or Virtex7 does not make much difference in raw material / work cost. If they would want - they could sell say 6.8 billion transistor chip for $60-70 and not for $1k-$2k for specific needs, still they would earn profits. And this is huge risk for ASIC builders. Such chip indeed would be very powerful and definitely would blow off low-end 90 nm ASIC solution. And this is what could happen - Xil or Altera will just lower prices for some specific application of their chip, to take share of this. But this will only happen of course if there will be more or less significant sales amount, say we get all-together to levels 10k chips per month.

So there's no "cheap and secure" entry into ASIC world. Those who go with 90 nm will still compete with FPGA. And it is just only about organization of FPGA sales and production, if FPGA devices vendors would have so high expenses, that they could not resist such ASIC.

The killing solution however would be to get 28-nm chip with SIMPLE design from first order. It is doable, I believe in about $4 - $6 mio. But I doubt that someone would invest it this day. At some day it will happen of course. I quoted multiple companies already about ASIC when did FPGA-based design, and typically 90nm with investments about $500k could blow off Spartans, but would be hard to compete against 28-nm.

So, please comment ? If this is just hobby for you and you won't like to stand head-to-head with upcoming ASIC or not ?

Why do you think that 28-nm would not compete ?

You probably have up to date worked the most on bitstream design as well. Interested to hear your point of view, where I made mistake ?

[ngzhang]

So the real contest is time; 28nm vs ASICs.

no, i mean:

130nm ASICs will fuck 28 nm FPGAs to shit. 

Haha, yes I know they will, but if the 28nms come out before the ASICs they will at least have a chance of entering the market

no, i think 28nm FPGAs will never have chance.

too many things will happen in 2013 and 2014.

These things are what I'm excited to see. I need to get some sleep now!

About 28 nm FPGAs chances... I've counted approximately translation of FPGA into ASIC. for example if my design translated - it would get approximately 8.7 million transistors count. And it is comparable to Pentium II design, so what we have with Spartan-6 0.045 um (45 nm) is what you could get if you squeeze hard into 0.35 um ASIC.

But squeezing design so hard into ASIC would be difficult, as many errors will happen on the way. It is LIKELY that builders of ASICs would squeeze more or less kind of simple VHD design, which would give approx. 3 times worse performance, and then start gradually improve technology with about 3-4 month iteration with each try. I think ngzhang understands well, what design mistakes - when in simulators it works but in hardware does not means when it gets to ASIC production.

So back to issue about ASIC vs FPGA - I suppose that 45 nm equivalent FPGA of Spartan6 class like 0.18 um ASIC.
Then 28 nm FPGA Artix7 could be like 0.112 um ASIC (if just counted, but I suppose comparable to 90 nm more, because it has CARRY CHAIN IN EVERY SLICE, AND I HAVE ROUND DESIGN THAT USES THIS FACT, AND WHICH IS 20% smaller Spartan6 is really bad with their Slice X stuff).

Then interesting thing about FPGA prices. They will fall if volumes will be bulk. This is why I am insisting on making FPGA-based products better, with better pricing - to make it at least competitive against ASICs.

Also - costs for chip production for vendor like Xilinx or Altera is not that much than silicon costs.... So production Spartan6 or Virtex7 does not make much difference in raw material / work cost. If they would want - they could sell say 6.8 billion transistor chip for $60-70 and not for $1k-$2k for specific needs, still they would earn profits. And this is huge risk for ASIC builders. Such chip indeed would be very powerful and definitely would blow off low-end 90 nm ASIC solution. And this is what could happen - Xil or Altera will just lower prices for some specific application of their chip, to take share of this. But this will only happen of course if there will be more or less significant sales amount, say we get all-together to levels 10k chips per month.

So there's no "cheap and secure" entry into ASIC world. Those who go with 90 nm will still compete with FPGA. And it is just only about organization of FPGA sales and production, if FPGA devices vendors would have so high expenses, that they could not resist such ASIC.

The killing solution however would be to get 28-nm chip with SIMPLE design from first order. It is doable, I believe in about $4 - $6 mio. But I doubt that someone would invest it this day. At some day it will happen of course. I quoted multiple companies already about ASIC when did FPGA-based design, and typically 90nm with investments about $500k could blow off Spartans, but would be hard to compete against 28-nm.

So, please comment ? If this is just hobby for you and you won't like to stand head-to-head with upcoming ASIC or not ?

Why do you think that 28-nm would not compete ?

You probably have up to date worked the most on bitstream design as well. Interested to hear your point of view, where I made mistake ?

our design is still fixing some small bugs. i will talk with you about the design after it fully completed. at that time we will know if we can solve the problems that you have.

ASIC design is much more complex than FPGA's. simple synthesis will not work.
why i said a 130nm ASIC can defeat a 28nm FPGA? because 32bit adder in 130nm ASIC can operate over 3GHz, a 3-input 32bit adder can easily running over 1GHz. i really doubt a 28nm FPGA will running a 3-input adder over 600MHz, maybe only 500MHz.
a 130nm ASIC is really cheap now, but we must find some professional team to do this work, their salaries and their company management cost will charge a lot. that's the thing stuck me. otherwise a small mining chip will cost only 1$/ea if you build 100K of them.
i mean, taking risks for a ASIC just for mining (and earn bitcoins for benefit) is unreasonable, but i think their are someone who want to push forward the bitcoin applications and resist a 51% attack from Bank of America will consider to pay the bill. if succeed, sell 100K of 1G speed small chips will multiply the total hashing speed by 10.
51% attackers didn't need ASIC, just buy 50 of your 110G rigs (cost only 5M $), and then bitcoin dead. after that, sell the second hand chips, can get 30% money back.

[bitfury]

So the real contest is time; 28nm vs ASICs.

no, i mean:

130nm ASICs will fuck 28 nm FPGAs to shit. 

Haha, yes I know they will, but if the 28nms come out before the ASICs they will at least have a chance of entering the market

no, i think 28nm FPGAs will never have chance.

too many things will happen in 2013 and 2014.

These things are what I'm excited to see. I need to get some sleep now!

About 28 nm FPGAs chances... I've counted approximately translation of FPGA into ASIC. for example if my design translated - it would get approximately 8.7 million transistors count. And it is comparable to Pentium II design, so what we have with Spartan-6 0.045 um (45 nm) is what you could get if you squeeze hard into 0.35 um ASIC.

But squeezing design so hard into ASIC would be difficult, as many errors will happen on the way. It is LIKELY that builders of ASICs would squeeze more or less kind of simple VHD design, which would give approx. 3 times worse performance, and then start gradually improve technology with about 3-4 month iteration with each try. I think ngzhang understands well, what design mistakes - when in simulators it works but in hardware does not means when it gets to ASIC production.

So back to issue about ASIC vs FPGA - I suppose that 45 nm equivalent FPGA of Spartan6 class like 0.18 um ASIC.
Then 28 nm FPGA Artix7 could be like 0.112 um ASIC (if just counted, but I suppose comparable to 90 nm more, because it has CARRY CHAIN IN EVERY SLICE, AND I HAVE ROUND DESIGN THAT USES THIS FACT, AND WHICH IS 20% smaller Spartan6 is really bad with their Slice X stuff).

Then interesting thing about FPGA prices. They will fall if volumes will be bulk. This is why I am insisting on making FPGA-based products better, with better pricing - to make it at least competitive against ASICs.

Also - costs for chip production for vendor like Xilinx or Altera is not that much than silicon costs.... So production Spartan6 or Virtex7 does not make much difference in raw material / work cost. If they would want - they could sell say 6.8 billion transistor chip for $60-70 and not for $1k-$2k for specific needs, still they would earn profits. And this is huge risk for ASIC builders. Such chip indeed would be very powerful and definitely would blow off low-end 90 nm ASIC solution. And this is what could happen - Xil or Altera will just lower prices for some specific application of their chip, to take share of this. But this will only happen of course if there will be more or less significant sales amount, say we get all-together to levels 10k chips per month.

So there's no "cheap and secure" entry into ASIC world. Those who go with 90 nm will still compete with FPGA. And it is just only about organization of FPGA sales and production, if FPGA devices vendors would have so high expenses, that they could not resist such ASIC.

The killing solution however would be to get 28-nm chip with SIMPLE design from first order. It is doable, I believe in about $4 - $6 mio. But I doubt that someone would invest it this day. At some day it will happen of course. I quoted multiple companies already about ASIC when did FPGA-based design, and typically 90nm with investments about $500k could blow off Spartans, but would be hard to compete against 28-nm.

So, please comment ? If this is just hobby for you and you won't like to stand head-to-head with upcoming ASIC or not ?

Why do you think that 28-nm would not compete ?

You probably have up to date worked the most on bitstream design as well. Interested to hear your point of view, where I made mistake ?

our design is still fixing some small bugs. i will talk with you about the design after it fully completed. at that time we will know if we can solve the problems that you have.

This is interesting. If you manage to get it working at clocks that TRCE says - it would be interesting indeed, so we could improve. Because I doubt that our designs could be similar, maybe we can produce even higher speeds by combining techniques used. If you have right equipment around - check power. I expect that you have higher speed of prototype PCB delivery, so maybe several designs should be tried to actually deliver necessary power into spartan. For me such experiments are quite difficult, as I have typically to wait 3 weeks before getting PCB of required quality to solder there Spartan.

ASIC design is much more complex than FPGA's. simple synthesis will not work.
why i said a 130nm ASIC can defeat a 28nm FPGA? because 32bit adder in 130nm ASIC can operate over 3GHz, a 3-input 32bit adder can easily running over 1GHz. i really doubt a 28nm FPGA will running a 3-input adder over 600MHz, maybe only 500MHz.
a 130nm ASIC is really cheap now, but we must find some professional team to do this work, their salaries and their company management cost will charge a lot. that's the thing stuck me. otherwise a small mining chip will cost only 1$/ea if you build 100K of them.
i mean, taking risks for a ASIC just for mining (and earn bitcoins for benefit) is unreasonable, but i think their are someone who want to push forward the bitcoin applications and resist a 51% attack from Bank of America will consider to pay the bill. if succeed, sell 100K of 1G speed small chips will multiply the total hashing speed by 10.
51% attackers didn't need ASIC, just buy 50 of your 110G rigs (cost only 5M $), and then bitcoin dead. after that, sell the second hand chips, can get 30% money back.

That's exactly is the point.... But when I started talking about ASICs - with guarantees developers given me quotes for 90nm in range of 500 Mhz .. 1 Ghz ...  That they will re-do design, re-order wafers in case of failure. And when I was talking about pushing limits to what Intel does with their chips - many said - sorry - we do not have right experience to do that. So the same thing stopped me going with ASIC. And also having current BitCoin size - seems almost nobody interested to seriously throw money in into such risky perspective.

Then - exactly - costs only 5M$ to get 51% of majority. For system with 40M$ market cap it is ok, and way better than banks. But if someone would like to invest say 1M$ to build big project using BitCoin - he face with the question - okay, my project will grow, and then will grow BitCoin cap. and then making 51% attack would be more feasible. Imagine if product, say like better, functional system like skype would emerge within BitCoin ... and its market cap goes to $2 billions...  would Microsoft pay that $5M to disrupt it ?

BitCoin is actually enabler for very interesting AND NEW p2p technology, that internet lacked from its beginning - solution of problem that currently solved by advertising online, that can be built and blow off many very big projects, doing them obsolete . But once BitCoin would start doing that - it would face real battle ..... As this basically would mean making whole business model of TOP-10 internet companies obsolete... That is actually much worse than single Bank of America... So that BF-110 was also estimation - how well BitCoin is prepared for that battle... Unfortunately not very well, a lot of work ahead. Most pity that it seems that these owners of $40M worth of Bitcoins don't really get how this thing important is, and why things like Scrypt-modified versions etc would not help much here, as BitCoin blockchain protection should lie tightly on Moore's law curve.

[Raize]

Keep in mind, you have to add 11 TH/s to get anywhere near a 51% attack, and at that point you would be mining ~3600 Bitcoin per day. If you are generating that much, it is actually in your best interest to *not* attack the network, and let someone else develop ASIC as the price increases because demand will remain the same but supply will slow down.

I know a number of people talk about what will happen when the reward halves, but what would happen if a large investor developed ASIC to control a significant stake of the Bitcoin network? Wouldn't it essentially be the same result if difficulty doubled as if the reward halved?

[ngzhang]

<let's get it shorter.>

we are trying to solve the power problems and heat dissipation by multiple ways, if they work, i guarantee will tell you( in private). because I admire you about your detailed introduction about your design, we are really doing the same thing, but i have no plan to share it (before).

about the ASIC design, a 90nm ASIC can run a 32bit adder over 7GHz. but you need a "elite research group" instead of some " bad engineer group". but you see, in our design, a SHA-2 core is really small and simple, this architecture is relatively easy to do the optimize. the smaller, the better. i nearly for sure place 200+ 128-cycle hash cores is better than now 80+ of 64 cycle cores (maybe this is our next design).

one way here to resist 51% attack is to increase the total hash speed fast. now we need to find a way. i think a mass of small mining ASICs (in public' hands) is a good choice.

Keep in mind, you have to add 11 TH/s to get anywhere near a 51% attack, and at that point you would be mining ~3600 Bitcoin per day. If you are generating that much, it is actually in your best interest to *not* attack the network, and let someone else develop ASIC as the price increases because demand will remain the same but supply will slow down.

I know a number of people talk about what will happen when the reward halves, but what would happen if a large investor developed ASIC to control a significant stake of the Bitcoin network? Wouldn't it essentially be the same result if difficulty doubled as if the reward halved?

a better way is mining for them self at ordinary day, and do a accurate attack when some large transform processing..... 

[bitfury]

<let's get it shorter.>

we are trying to solve the power problems and heat dissipation by multiple ways, if they work, i guarantee will tell you( in private). because I admire you about your detailed introduction about your design, we are really doing the same thing, but i have no plan to share it (before).

Well, possibly we can meet and discuss it. Because it is unlikely that it would be EXACTLY the same, very unlikely. As the design I made - I know that it is not absolutely the best one that could be done, and there's room for improvement. However efforts required are not justified, especially with epic failure about powering that logics inside. Also all path of design evolution is even more interesting than design itself, as I have for example interesting approach for parallel design with W-expander around DSP48. I've aimed about 350-370 Mhz clock originally - so this IS DEFINITELY point of failure, and if I would relax clock and target it at about 300 Mhz - it _could_ be implemented more efficiently. Also there's interesting possibility to mix parallel computation and serial rolled computation in 1:3 etc. (that's of what I had before).

about the ASIC design, a 90nm ASIC can run a 32bit adder over 7GHz. but you need a "elite research group" instead of some " bad engineer group". but you see, in our design, a SHA-2 core is really small and simple, this architecture is relatively easy to do the optimize. the smaller, the better. i nearly for sure place 200+ 128-cycle hash cores is better than now 80+ of 64 cycle cores (maybe this is our next design).

one way here to resist 51% attack is to increase the total hash speed fast. now we need to find a way. i think a mass of small mining ASICs (in public' hands) is a good choice.

Yes, making BitCoin ASIC available from different suppliers is nice idea. But someone has to invest funds into it. And it seems that community has no interest to invest say 10% of owned BTC to finish this moment up... About "elite research group" - that's exactly what I mentioned about.... All you can get say for $500k to produce ASIC would be unlikely "elite"... I suppose that AMD, Nvidia, Intel, military consume resources of elite research groups at much higher rates, than single investor would afford. Then if when elite group would do ASIC at high costs concentrate efforts on backwards 90-nm ? It should be AT LEAST 45-nm then... As this would rock... And true ASIC of course, not things like structured asic or fpga hardcopies.

ABOUT ASIC - One interesting thing that I have researched - single-bit design. I.e. instead of carry chains you use D-flip flop for carry and D-flip flop for result. Then it would require 32 times less wires for W-expander. Allows constant-optimization. This would be smallest CORE, but with one IF - IF you are capable to design long digital delay lines (i.e. like SRL16 in spartan) within chip. I know that it is pretty doable. But nobody I contacted can work at that level, and basically it is unlikely what you will find in cell library from TSMC for example. This carefully designed thing can beat everything and rise calculations speed at silicon maximum. I doubt however that there's many _developers_ who would even understand what I wrote about here and zero who can do that not in theory but with more or less guaranteed result in hardware.

Keep in mind, you have to add 11 TH/s to get anywhere near a 51% attack, and at that point you would be mining ~3600 Bitcoin per day. If you are generating that much, it is actually in your best interest to *not* attack the network, and let someone else develop ASIC as the price increases because demand will remain the same but supply will slow down.

I know a number of people talk about what will happen when the reward halves, but what would happen if a large investor developed ASIC to control a significant stake of the Bitcoin network? Wouldn't it essentially be the same result if difficulty doubled as if the reward halved?

a better way is mining for them self at ordinary day, and do a accurate attack when some large transform processing..... 

well. it is pretty doable (about 51% for bitcoins) following way (also point for FPGA at current period vs ASIC) -
 I have request for video transcoding at large scale - people inquiry whether I can beat with cost of these chips installations of servers/gpus for that. Typical need - tranform video file from formats:

(S)VCD (Super Video CD);
DVD, including encrypted DVD;
MPEG-1/2 (ES/PS/PES/VOB);
AVI file format;
MOV/MP4 format; Ogg/OGM files; Matroska.

codecs:

MPEG-1 (VCD) and MPEG-2 (SVCD/DVD/DVB) video;
MPEG-4 ASP including DivX and Xvid;
MPEG-4 AVC aka H.264;
DV video;
MJPEG, AVID, VCR2, ASV2;
FLI/FLC.

into:

MP4 H264 AAC

at bitrates:

'1080p' 4M (720p < height <= 1080p)
'720p' 2M (480p < height <= 720p)
'480p' 1M (height = 480p)
'480p-' 512k (360p < height < 480p)
'360p'  512k (height = 360p)
'360p-' 256k (240p < height < 360p)
'240p'  164k (height <= 240p)

that's for flash tube web sites...

So if farm can do this work - and process multiple petabytes of videos more efficiently than on own server hardware or like purchased work on clouds - then they will be definitely willing to invest more, as this is not only bitcoin-targetted then, and when ASIC comes in play - this farm would still be useful for other computations.

The problem is - that supporting all of that codes is ton of work. And also designing more or less universal board for computations is tough part as well. But it would open more financing for FPGAs - say on demand it transcode videos, and then in idle calculates bitcoin. If later it could be possible to run rendering there - it would be even more beneficial, however that's yet higher ton of work, and it is quite difficult to estimate feasibility of FPGA vs GPU for rendering.

If this is doable - such farm could be nice step into ASIC development for bitcoin world, still investments into it would be secured well and much less risky.

[Inspector 2211]

One interesting thing that I have researched - single-bit design. I.e. instead of carry chains you use D-flip flop for carry and D-flip flop for result. Then it would require 32 times less wires for W-expander. Allows constant-optimization. This would be smallest CORE, but with one IF - IF you are capable to design long digital delay lines (i.e. like SRL16 in spartan) within chip. I know that it is pretty doable. But nobody I contacted can work at that level, and basically it is unlikely what you will find in cell library from TSMC for example. This carefully designed thing can beat everything and rise calculations speed at silicon maximum. I doubt however that there's many _developers_ who would even understand what I wrote about here and zero who can do that not in theory but with more or less guaranteed result in hardware.

A carryless adder, 32 bits in + 32 bits in results in 64 bits out in a non-canonical "2 output bits for each output bit" representation?
The problem with this approach is, it's not compatible with the XOR operation, not even with rotate and shift operations.
So, yes, while you can build a large multiplier that way, converting the result to a canonical representation as the final step,
you cannot build SHA-256 that way. I have investigated it, and it's not possible.

If you have been talking about something else entirely, I apologize.

[Inspector 2211]

One interesting thing that I have researched - single-bit design. I.e. instead of carry chains you use D-flip flop for carry and D-flip flop for result. Then it would require 32 times less wires for W-expander. Allows constant-optimization. This would be smallest CORE, but with one IF - IF you are capable to design long digital delay lines (i.e. like SRL16 in spartan) within chip. I know that it is pretty doable. But nobody I contacted can work at that level, and basically it is unlikely what you will find in cell library from TSMC for example. This carefully designed thing can beat everything and rise calculations speed at silicon maximum. I doubt however that there's many _developers_ who would even understand what I wrote about here and zero who can do that not in theory but with more or less guaranteed result in hardware.

A carryless adder, 32 bits in + 32 bits in results in 64 bits out in a non-canonical "2 output bits for each output bit" representation?
The problem with this approach is, it's not compatible with the XOR operation, not even with rotate and shift operations.
So, yes, while you can build a large multiplier that way, converting the result to a canonical representation as the final step,
you cannot build SHA-256 that way. I have investigated it, and it's not possible.

If you have been talking about something else entirely, I apologize.

Example (3 bit inputs instead of 32 bit inputs):
Let's calculate (A+B) XOR (C+D)
A=5, B=7, C=7, D=7
A carry adder yields A+B=4 (3-bit result) and C+D=6 (3-bit result),  4 XOR 6 is 2.
A carryless adder yields A+B=10|01|10 (noncanonical binary) and C+D=10|10|10 (noncanonical binary)
Xoring that while still in noncanonical binary yields 00|11|00
Canonizing that yields 110 (canonical binary) = 6 (decimal)

In other words, the XOR operation is not compatible with a non-canonical binary representation.

[bitfury]

One interesting thing that I have researched - single-bit design. I.e. instead of carry chains you use D-flip flop for carry and D-flip flop for result. Then it would require 32 times less wires for W-expander. Allows constant-optimization. This would be smallest CORE, but with one IF - IF you are capable to design long digital delay lines (i.e. like SRL16 in spartan) within chip. I know that it is pretty doable. But nobody I contacted can work at that level, and basically it is unlikely what you will find in cell library from TSMC for example. This carefully designed thing can beat everything and rise calculations speed at silicon maximum. I doubt however that there's many _developers_ who would even understand what I wrote about here and zero who can do that not in theory but with more or less guaranteed result in hardware.

A carryless adder, 32 bits in + 32 bits in results in 64 bits out in a non-canonical "2 output bits for each output bit" representation?
The problem with this approach is, it's not compatible with the XOR operation, not even with rotate and shift operations.
So, yes, while you can build a large multiplier that way, converting the result to a canonical representation as the final step,
you cannot build SHA-256 that way. I have investigated it, and it's not possible.

If you have been talking about something else entirely, I apologize.

Not exactly. I mentioned case when you do adding in 32 clocks.... One bit at one clock edge. So one D-trigger holds output, and other D-trigger holds carry, which fed back to adder on next clock.

So you get ONE wire instead of 32 wires for round expander fully unrolled. Still design is pipelined.

But you need really long and compact shift registers without access to internal bits of course. These are required to do rotation operations (basically by delaying for 32 clocks all variables in calculation, but doing different delays for RORs). And then really long delays for W round (that would be 224-bit delay line and 256-bit delay line).

I've tried to experiment this with BRAMs - it is nice - when you have 32 rounds of round expander around single BRAM :-)
but actually static RAM is nowhere near efficiency and density of such shift registers implemented in silicon.

As this register would work only in dynamics, basically you need only capacitor to hold bit and circuit to charge next capacitor on clock pulse. It will not work at slow clocks then of course. And as far as I know it is extremely hard to implement such circuit in silicon (basically because I have spoken not with elite ASIC developers indeed).

If that approach would save 3-4 times transistor count compared to serie of flip-flops, the design then would shine :-)

[Inspector 2211]

One interesting thing that I have researched - single-bit design. I.e. instead of carry chains you use D-flip flop for carry and D-flip flop for result. Then it would require 32 times less wires for W-expander. Allows constant-optimization. This would be smallest CORE, but with one IF - IF you are capable to design long digital delay lines (i.e. like SRL16 in spartan) within chip. I know that it is pretty doable. But nobody I contacted can work at that level, and basically it is unlikely what you will find in cell library from TSMC for example. This carefully designed thing can beat everything and rise calculations speed at silicon maximum. I doubt however that there's many _developers_ who would even understand what I wrote about here and zero who can do that not in theory but with more or less guaranteed result in hardware.

A carryless adder, 32 bits in + 32 bits in results in 64 bits out in a non-canonical "2 output bits for each output bit" representation?
The problem with this approach is, it's not compatible with the XOR operation, not even with rotate and shift operations.
So, yes, while you can build a large multiplier that way, converting the result to a canonical representation as the final step,
you cannot build SHA-256 that way. I have investigated it, and it's not possible.

If you have been talking about something else entirely, I apologize.

Not exactly. I mentioned case when you do adding in 32 clocks.... One bit at one clock edge. So one D-trigger holds output, and other D-trigger holds carry, which fed back to adder on next clock.

So you get ONE wire instead of 32 wires for round expander fully unrolled. Still design is pipelined.

But you need really long and compact shift registers without access to internal bits of course. These are required to do rotation operations (basically by delaying for 32 clocks all variables in calculation, but doing different delays for RORs). And then really long delays for W round (that would be 224-bit delay line and 256-bit delay line).

I've tried to experiment this with BRAMs - it is nice - when you have 32 rounds of round expander around single BRAM :-)
but actually static RAM is nowhere near efficiency and density of such shift registers implemented in silicon.

As this register would work only in dynamics, basically you need only capacitor to hold bit and circuit to charge next capacitor on clock pulse. It will not work at slow clocks then of course. And as far as I know it is extremely hard to implement such circuit in silicon (basically because I have spoken not with elite ASIC developers indeed).

If that approach would save 3-4 times transistor count compared to serie of flip-flops, the design then would shine :-)

Ah, I see what you mean.
Maybe a less radical approach, adding 4 bits per clock, would be more practical. A 4-bit adder fits inside one slice.
I'll think about it...

>one capacitor to hold bit

I the old days, you could buy such chips: Called CCD or charge-coupled device.
Steve Wozniak based the video memory of the Apple I on such a device. It not only stored the all the characters in the video buffer (1024 bytes IIRC), but generated the video signal as well, as its content rotated constantly. A new character would be inserted by breaking the loop for a moment.

[kano]

Hmm so bitfury might have quite a bit of incentive in this FPGA vs ASIC discussion
https://bitcointalk.org/index.php?topic=3889.msg915037#msg915037
(weapon of choice? )

[bitfury]

Hmm so bitfury might have quite a bit of incentive in this FPGA vs ASIC discussion
https://bitcointalk.org/index.php?topic=3889.msg915037#msg915037
(weapon of choice? )

https://bitcointalk.org/index.php?topic=76351.msg925049#msg925049

That's for ngzhang and all folks - I've run some comparison of FPGA vs ASIC Hardcopy...
Artix7 allows tricks like LX150 unlike Cyclone V though. So by following that thread,
you can understand why claims about 28nm being obsolete are questionable.

[bleza]

subscribed
count me in for 4 or 5 boards 

[ngzhang]

got 4 samples today....

[spiccioli]

got 4 samples today....

show some pics or it didn't happen

spiccioli

[arklan]

got 4 samples today....

oh, you TEASE.

[ngzhang]

got 4 samples today....

show some pics or it didn't happen

spiccioli

 

samples have full of small design bugs, already make a TODO list.

unfortunately, the firmware side is a bit delayed. i could only do the test by previous icarus bitsteam. hours for no error now. i hope they can make a breakthrough in the near future.

this afternoon, i tested the on-board power module at school's lab . it can provide a 16A continues current for each FPGA core, 25A peak. form 7~14A is a wide high-efficiency Zone (>85%). looks like Lancelot can become a very good development platform for various of third party bitsteams.

tomorrow i will take some photos. it's black night now:D

[Turbor]

got 4 samples today....

show some pics or it didn't happen

spiccioli

 

samples have full of small design bugs, already make a TODO list.

unfortunately, the firmware side is a bit delayed. i could only do the test by previous icarus bitsteam. hours for no error now. i hope they can make a breakthrough in the near future.

this afternoon, i tested the on-board power module at school's lab . it can provide a 16A continues current for each FPGA core, 25A peak. form 7~14A is a wide high-efficiency aone (>85%). looks like Lancelot can become a very good development platform for various of third party bitsteams.

tomorrow i will take some photos. it's black night now:D

Cool, looking forward for some pics.

[Dexter770221]

My bitcoins can't wait to go to your wallet

[fuxianhui888]

pics look really nice,

[allinvain]

pics look really nice,

Where where where  



Edit...found it  Very nice indeed!

[fuxianhui888]

pics look really nice,

Where where where  



Edit...found it  Very nice indeed!

I like his camera ,

[rgzen]

Hello,
I want to know how much will the dev kit cost.
Thanks.

[ngzhang]

Hello,
I want to know how much will the dev kit cost.
Thanks.

69$.
include a platform cable USB, a USB stick for software, some link cables.

[ngzhang]

waiting is boring ...

[rjk]

Wow that is awesome. Is it just for your testing purposes, or will they be for sale?

[ngzhang]

Wow that is awesome. Is it just for your testing purposes, or will they be for sale?

do you want one? 

[rjk]

Wow that is awesome. Is it just for your testing purposes, or will they be for sale?

do you want one? 

Not me personally, but I imagine that some of the guys with large clusters might make use of them. What's the maximum power draw for each port, and the total maximum?

[ngzhang]

Wow that is awesome. Is it just for your testing purposes, or will they be for sale?

do you want one? 

Not me personally, but I imagine that some of the guys with large clusters might make use of them. What's the maximum power draw for each port, and the total maximum?

each port is a 3.81mm Euro terminal block. 10A max.
total depends on your ATX power, i think 400W is OK.

[eckmar]

What is the price?

Sunny regards from the Island,
 Ecki

[ngzhang]

Wow that is awesome. Is it just for your testing purposes, or will they be for sale?

do you want one? 

I do.  Are you selling these?

What is the price?

Sunny regards from the Island,
 Ecki

ok, i only made about 10 of them for my testing purpose.
but there are already a plan when lancelot come out, i will let this adapter as a order-able accessory.
price? i don't know now. need some cost check first. but i think maybe about 20~30$.

[Beaflag VonRathburg]

Those power adapters are a very nice piece. I wish more companies would come out with items like that.

[rudrigorc2]

Those power adapters are a very nice piece. I wish more companies would come out with items like that.

BLUE PCB!

No more shredding the PSU cables!

[seriouscoin]

Wow that is awesome. Is it just for your testing purposes, or will they be for sale?

do you want one? 

I do.  Are you selling these?

What is the price?

Sunny regards from the Island,
 Ecki

ok, i only made about 10 of them for my testing purpose.
but there are already a plan when lancelot come out, i will let this adapter as a order-able accessory.
price? i don't know now. need some cost check first. but i think maybe about 20~30$.

Or free/included with bulk order of Lancelot?

It makes more sense then

[likuidxd]

I imagine that this is the mother you were speaking of? Looks beautiful! Will this baby be power 20 boards?

[seriouscoin]

I imagine that this is the mother you were speaking of? Looks beautiful! Will this baby be power 20 boards?

no this is just power distributor

The motherboard is for mining with all the lancelot. You dont need a host anymore.

I believe he also make it link without any USB hub? probably built in bus lane

[ngzhang]

I imagine that this is the mother you were speaking of? Looks beautiful! Will this baby be power 20 boards?

certainly not... it's only a small tool for my testing work, cost one night time to design... but soldering them and make the cables really cost me sometime.
the motherboard project will start after 1st batch of lancelot.

[Dhomochevsky]

I asked this sometime back but it was probably missed, and it's still not covered in the original post, so I'll ask again:

Will the new bitstream for Lancelot be compatible with Icarus? It was promised to be this way sometime back, in the old Icarus thread, but there's no mention of it here, in this thread.

If this has already been answered, sorry, must've missed it.

[Dexter770221]

First post:
...
6, other features.
...
k, will compatible with present icarus bitsteam at first.
...

[Dhomochevsky]

That says Lancelot is compatible with the Icarus bitstream, I want to know if the other way around (Icarus compatible with the future Lancelot bitstream) is also true .

[ngzhang]

That says Lancelot is compatible with the Icarus bitstream, I want to know if the other way around (Icarus compatible with the future Lancelot bitstream) is also true .

The answer is,  Icarus can run Lancelot's first bitstream, but at a lower speed. This is a final upgrade for Icarus system.
Due to lack of some hardware features, Icarus can not run Lancelot 's future bitsteams.

[Dhomochevsky]

Thanks for the clarification.

[Newar]

Looks great!

sub (can't wait...)

[bitlane]

The answer is,  Icarus can run Lancelot's first bitstream, but at a lower speed. This is a final upgrade for Icarus system.
Due to lack of some hardware features, Icarus can not run Lancelot 's future bitsteams.

As I was too lazy to read the entire thread....

Is there any chance you could update the first post to summarize a production update ?
Current 'development' speeds, power consumption etc ?
Projected shipping date(s) for batches etc ?

Thanks and I am looking forward to this.
bitlane.

[ngzhang]

The answer is,  Icarus can run Lancelot's first bitstream, but at a lower speed. This is a final upgrade for Icarus system.
Due to lack of some hardware features, Icarus can not run Lancelot 's future bitsteams.

As I was too lazy to read the entire thread....

Is there any chance you could update the first post to summarize a production update ?
Current 'development' speeds, power consumption etc ?
Projected shipping date(s) for batches etc ?

Thanks and I am looking forward to this.
bitlane.

i will update these information after i can confirm. thanks. 

[bitlane]

i will update these information after i can confirm. thanks.  

Thanks very much.

The future of my mining operation is hinging on the release of Lancelot...lol

I am praying nightly for $500 @ $1/MH/s @ 25W
....as I am certain I am not the only one in touch with God currently in regards to this.
If God is unwilling to answer my prayers, I will have no choice but to contact Satan.

[ngzhang]

i will update these information after i can confirm. thanks.  

Thanks very much.

The future of my mining operation is hinging on the release of Lancelot...lol

I am praying nightly for $500 @ $1/MH/s @ 25W
....as I am certain I am not the only one in touch with God currently in regards to this.
If God is unwilling to answer my prayers, I will have no choice but to contact Satan.

My present work is push it better than 1$/MH/S, and less than 25W.
By present test, running the V3 old bitsteam, Lancelot only consume 15.6W

[rudrigorc2]

i will update these information after i can confirm. thanks.  

Thanks very much.

The future of my mining operation is hinging on the release of Lancelot...lol

I am praying nightly for $500 @ $1/MH/s @ 25W
....as I am certain I am not the only one in touch with God currently in regards to this.
If God is unwilling to answer my prayers, I will have no choice but to contact Satan.

My present work is push it better than 1$/MH/S, and less than 25W.
By present test, running the V3 old bitsteam, Lancelot only consume 15.6W

I am looking forward to using that XILINX cable soon. I dont want to believe Icarus is really meant to die like the mythology, damn !

[bitlane]

My present work is push it better than 1$/MH/S, and less than 25W.
By present test, running the V3 old bitsteam, Lancelot only consume 15.6W

I think I love you.

Please tell me when/where to send money.....lol

[luffy]

I really can't wait!
are you thinking to sell at lower rates before even testing is finished? 

[luffy]

@ngzhang
have you checked this already?
https://bitcointalk.org/index.php?topic=88413.0

[ngzhang]

@ngzhang
have you checked this already?
https://bitcointalk.org/index.php?topic=88413.0

yep, but you know...
these fpgas are  tooooo small...

[seriouscoin]

@ngzhang
have you checked this already?
https://bitcointalk.org/index.php?topic=88413.0

yep, but you know...
these fpgas are  tooooo small...

You should apply to work for BFL.

They're looking for a Mandarin speaking engineer in Asia.

Please work for them.

[ngzhang]

@ngzhang
have you checked this already?
https://bitcointalk.org/index.php?topic=88413.0

yep, but you know...
these fpgas are  tooooo small...

You should apply to work for BFL.

They're looking for a Mandarin speaking engineer in Asia.

Please work for them.

NEVER EVER

[Dhomochevsky]

 

What if they say "Pretty please"?

[EnergyVampire]

sub

Added to Watchlist: https://bitcointalk.org/index.php?topic=90136.0

[exahash]

You should apply to work for BFL.

They're looking for a Mandarin speaking engineer in Asia.

Please work for them.

NEVER EVER

Thank goodness!

[disclaimer201]

You should apply to work for BFL.

They're looking for a Mandarin speaking engineer in Asia.

Please work for them.

NEVER EVER

Thank goodness!

Why should he work someone else? Butterfly Labs suck in comparison.

[CoinDiner]

First off    sorry for the thread hijack!

If anyone from Europe is thinking of getting some of these boards, and NOT using bitcoins to pay , can you let me know how you plan on paying.

Ta

[PawShaker]

You should apply to work for BFL.

They're looking for a Mandarin speaking engineer in Asia.

Please work for them.

NEVER EVER

Thank goodness!

Why should he work someone else? Butterfly Labs suck in comparison.

Please, stay freelance. I do belive in distribution and not concentration of power. Yes, when talented people get together they can create oustanding gifts to the humanity... or dominate the world. For instance I can live without "personal computer", "mouse", "iPhone". I apreciate significance of any of these breakthroughs but none of them is wotrth sacrificing beeing free. The leader is gone, but his company continoues the work of global domination.

[seriouscoin]

@ngzhang
have you checked this already?
https://bitcointalk.org/index.php?topic=88413.0

yep, but you know...
these fpgas are  tooooo small...

You should apply to work for BFL.

They're looking for a Mandarin speaking engineer in Asia.

Please work for them.

NEVER EVER

First, never say never ....oops

Second, we want you to work for BFL so we can have correct info and not BS crap. I'm sure they cant do jack to you because you're in China.

Work for them so you can build better products *HINT HINT*

[Turbor]

First off    sorry for the thread hijack!

If anyone from Europe is thinking of getting some of these boards, and NOT using bitcoins to pay , can you let me know how you plan on paying.

Ta

He has a bank account. Wire transfer works very well.

[ngzhang]

@ngzhang
have you checked this already?
https://bitcointalk.org/index.php?topic=88413.0

yep, but you know...
these fpgas are  tooooo small...

You should apply to work for BFL.

They're looking for a Mandarin speaking engineer in Asia.

Please work for them.

NEVER EVER

First, never say never ....oops

Second, we want you to work for BFL so we can have correct info and not BS crap. I'm sure they cant do jack to you because you're in China.

Work for them so you can build better products *HINT HINT*

bank transfer or paypal is acceptable.
or MTGOX$ redeem code

[rph]

ASICs will fuck all FGPAs to shit.

Only if it's full custom below ~90nm, which means several million dollars in mask costs, a 6-9 month
mfg period, and a pretty good chance that the first chip is useless, unless you know WTF you are
doing and poached a rockstar team of people making $200k+/yr away from companies like
Broadcom, Marvell, Intel, etc. And managed to convince your investors they wouldn't be better
off funding something else for a larger / lower risk market.

Given the odds of BFL pulling that off - I'm going to keep buying FPGAs.
I will fear a true full custom mining ASIC if/when it exists, but the FPGAs
will certainly have paid for themselves way before then.

-rph

[rjk]

Would you agree though, rph, that SHA256 is quite a bit simpler than most designs, and therefore is (even slightly) less likely to need several respins before a good wafer is produced?

[rph]

It helps but logic/RTL verification is one of the easiest steps in a modern ASIC design.
The lower level physical/analog design is what fucks over most amateur ASIC designs.

-rph

[rjk]

It helps but logic/RTL verification is one of the easiest steps in a modern ASIC design.
You derisk that by using - guess what - FPGAs. The lower level physical/analog design
is what fucks over most amateur ASIC designs.

-rph

I see, so the person or company that is designing an ASIC really is responsible for the entire thing, it isn't as simple as handing some completed HDL over to a company who will then interpret them into their process and print some chips.

[2112]

Only if it's full below ~90nm, which means several million dollars in mask costs, a 6-9 month
mfg period, and a pretty good chance that the first chip is useless, unless you know WTF you are
doing

This is a gross overestimate. The folded, not-unrolled design is basically a two 32-bit-wide shift registers with some multi-input adders in a feedback and an adder-comparator on the output. The remaining logic is all standard cells: PLL, ROM and I/O.

SHA-256 is pretty much self-testing: there are no unreachable states and all every state is observable. Any internal fault will eventually show up on the outputs.

The lower level physical/analog design is what fucks over most amateur ASIC designs.

And again dual SHA-256 is a dream assignment for the beginners. It is small and it takes only about 64 or 128 simulated clocks to verify the entire custom circuitry. From my past experience with SPICE and BSIM4 I would venture to guess that I could simulate one clock cycle of an entire SHA-256 round on my Core2Duo laptop in one day.

The additional benefit for the team is that they have design closure achieved from the moment they pass automated DRC verification. All timing and power targets are soft, they have absolutely no interoperability requirements and any hard targets for timing closure or power closure. All they have to do is pick an  internal clock generation cell with variable multiplier.

I would guess that the chances of a "zero yield" first spin are atypically low for this design.

[hardpick]

Only if it's full below ~90nm, which means several million dollars in mask costs, a 6-9 month
mfg period, and a pretty good chance that the first chip is useless, unless you know WTF you are
doing

This is a gross overestimate. The folded, not-unrolled design is basically a two 32-bit-wide shift registers with some multi-input adders in a feedback and an adder-comparator on the output. The remaining logic is all standard cells: PLL, ROM and I/O.

SHA-256 is pretty much self-testing: there are no unreachable states and all every state is observable. Any internal fault will eventually show up on the outputs.

The lower level physical/analog design is what fucks over most amateur ASIC designs.

And again dual SHA-256 is a dream assignment for the beginners. It is small and it takes only about 64 or 128 simulated clocks to verify the entire custom circuitry. From my past experience with SPICE and BSIM4 I would venture to guess that I could simulate one clock cycle of an entire SHA-256 round on my Core2Duo laptop in one day.

The additional benefit for the team is that they have design closure achieved from the moment they pass automated DRC verification. All timing and power targets are soft, they have absolutely no interoperability requirements and any hard targets for timing closure or power closure. All they have to do is pick an  internal clock generation cell with variable multiplier.

I would guess that the chances of a "zero yield" first spin are atypically low for this design.

I think what you are saying is a sha-256 asic is fairly simple and they should get it right the first time ?

[kano]

Only if it's full below ~90nm, which means several million dollars in mask costs, a 6-9 month
mfg period, and a pretty good chance that the first chip is useless, unless you know WTF you are
doing

This is a gross overestimate. The folded, not-unrolled design is basically a two 32-bit-wide shift registers with some multi-input adders in a feedback and an adder-comparator on the output. The remaining logic is all standard cells: PLL, ROM and I/O.

SHA-256 is pretty much self-testing: there are no unreachable states and all every state is observable. Any internal fault will eventually show up on the outputs.

The lower level physical/analog design is what fucks over most amateur ASIC designs.

And again dual SHA-256 is a dream assignment for the beginners. It is small and it takes only about 64 or 128 simulated clocks to verify the entire custom circuitry. From my past experience with SPICE and BSIM4 I would venture to guess that I could simulate one clock cycle of an entire SHA-256 round on my Core2Duo laptop in one day.

The additional benefit for the team is that they have design closure achieved from the moment they pass automated DRC verification. All timing and power targets are soft, they have absolutely no interoperability requirements and any hard targets for timing closure or power closure. All they have to do is pick an  internal clock generation cell with variable multiplier.

I would guess that the chances of a "zero yield" first spin are atypically low for this design.

So, in this arena - price wise what would be a very reasonable estimate of how much it would cost BFL?
(so I know if the major effort to very slightly possibly invalidate sha256 would be worth the while to kill their company)

[Syke]

And again dual SHA-256 is a dream assignment for the beginners. It is small and it takes only about 64 or 128 simulated clocks to verify the entire custom circuitry. From my past experience with SPICE and BSIM4 I would venture to guess that I could simulate one clock cycle of an entire SHA-256 round on my Core2Duo laptop in one day.

The additional benefit for the team is that they have design closure achieved from the moment they pass automated DRC verification. All timing and power targets are soft, they have absolutely no interoperability requirements and any hard targets for timing closure or power closure. All they have to do is pick an  internal clock generation cell with variable multiplier.

I would guess that the chances of a "zero yield" first spin are atypically low for this design.

Since SHA-256 is so easy, why was BFL's FPGA power&performance estimates off by a factor of 5?

[2112]

Since SHA-256 is so easy, why was BFL's FPGA power&performance estimates off by a factor of 5?

I'm going to guess that they made the same mistake as the open source designers from another thread.

Since the design is so easy to get functionally correct they didn't bother to create the testbench for simulation and didn't run the full timing simulation.

Then they saved additional time by doing the probabilistic static power estimation, not the accurate power estimation that is driven by the simulation results from the testbench.

I'm also not sure about Altera's licensing and pricing model. There may be an additional license charge for the post-simulation power analyzer.

[mrb]

Since SHA-256 is so easy, why was BFL's FPGA power&performance estimates off by a factor of 5?

I know I am nitpicking, but they were off by "only" a factor of 4... A single draws 66W(*) from the 12V input --ignoring inefficiencies of the power adapter-- and 62W without counting the 2 (or sometimes 3) fans.

(*) Average measured from my batch with a clamp meter.

[pieppiep]

4 times the power and 20% less speed iirc, combined a factor of 5 in Mh/$

[mrb]

4 times the power and 20% less speed iirc, combined a factor of 5 in Mh/J (mrb: fixed unit)

Nope.

Announced: 1Gh/s at 20W = 50 Mh/J
Actual: 832Mh/s at 66W = 12.6 Mh/J

Difference in efficiency per Joule is a factor of 4. (Again I am not counting the power adapter inefficiencies which bumps the 66W to 80W or so at the wall).

[2112]

I think what you are saying is a sha-256 asic is fairly simple and they should get it right the first time ?

Yeah. This is pretty much a student project.

So, in this arena - price wise what would be a very reasonable estimate of how much it would cost BFL?
(so I know if the major effort to very slightly possibly invalidate sha256 would be worth the while to kill their company)

No idea. I always worked in a long-term R&D teams. I don't know anyone who does merchant one-shot jobs.

[arklan]

me thinks we got slightly off topic here...

Zhang, how's things with lancelot?

[ngzhang]

ok, report is here:
good news:
fixed all small bugs on the present Lancelot PCB, waiting for heat-sink sample for a final check. will push it to production stage. that means Lancelot will come out in batch in ~3 weeks. 
bad news:
bitsteam build meet with some difficulties. no ETA can be  estimate. 

should i make Lancelot as a hardware platform only? you know there are a mass of 3-rd party mining bitsteams, and running really fast. is it good for me to sell Lancelot at a extreme low price and cooperate with those bitsteam makers?  Lancelot have the best power module(14A continuous and 25A peak, 85% efficiency, for each FPGA) and  encryption support (eFuse key  storage and volatile memory key storage). and opensourced. 


about the mining ASIC:

it's really easy to make a mining ASIC, but hard to make a "good" mining ASIC. that's  my point of view.

PS: please feel free to discuss or off topic in my thread. i'm a chinese and in chinese forums, all threads are off topic. it's  a usually situation for me. 

[seriouscoin]

ok, report is here:
good news:
fixed all small bugs on the present Lancelot PCB, waiting for heat-sink sample for a final check. will push it to production stage. that means Lancelot will come out in batch in ~3 weeks. 
bad news:
bitsteam build meet with some difficulties. no ETA can be  estimate. 

should i make Lancelot as a hardware platform only? you know there are a mass of 3-rd party mining bitsteams, and running really fast. is it good for me to sell Lancelot at a extreme low price and cooperate with those bitsteam makers?  Lancelot have the best power module(14A continuous and 25A peak, 85% efficiency, for each FPGA) and  encryption support (eFuse key  storage and volatile memory key storage). and opensourced. 


about the mining ASIC:

it's really easy to make a mining ASIC, but hard to make a "good" mining ASIC. that's  my point of view.

PS: please feel free to discuss or off topic in my thread. i'm a chinese and in chinese forums, all threads are off topic. it's  a usually situation for me. 

If you have difficulty with the bitstream, you should work with third party bitstream a deal. And ship Lancelot in a complete working package. Thats the only solution. If you're shipping bare card there will only be a handful of customers.

You need to act quick because mini-rigs are already shipping. If the end product doesnt result a margin that you expected, its wise to cancel it.

Dont rush to production stage without having the bitstream issue sorted out.

Also, i already see your expected price of the Lancelot to be a bit high.

[wildemagic]

bitsteam build meet with some difficulties. no ETA can be  estimate. 

should i make Lancelot as a hardware platform only?

Fine if the hardware is well priced, perhaps with the icarus bitstream in there to get things going.
Dont ship without a bitstream, at least something with expected performance of 400Mhash/sec.

kind regards

[pieppiep]

PS: please feel free to discuss or off topic in my thread. i'm a chinese and in chinese forums, all threads are off topic. it's  a usually situation for me. 

How is the weather over there? It's rainy over here in the Netherlands.

[disclaimer201]

PS: please feel free to discuss or off topic in my thread. i'm a chinese and in chinese forums, all threads are off topic. it's  a usually situation for me. 

How is the weather over there? It's rainy over here in the Netherlands.

No good start of the summer here in Berlin, either. I would be very much interested in buying one or two FPGAs though that I just need to plug in and press go. Preferably the fancy and cost-efficient Lancelot one.

[luffy]

dear friend,
i am afraid that FPGA in 6 months time will turn obsolete! (ASIC time)
i wonder if you should put your efforts to openASIC or other ASIC project!

[ngzhang]

dear friend,
i am afraid that FPGA in 6 months time will turn obsolete! (ASIC time)
i wonder if you should put your efforts to openASIC or other ASIC project!

  let's see what will happen in the next 6 months.

[Dexter770221]

dear friend,
i am afraid that FPGA in 6 months time will turn obsolete! (ASIC time)
i wonder if you should put your efforts to openASIC or other ASIC project!

  let's see what will happen in the next 6 months.

Yep. We will see. I still can't wait to order Lancelot...

[David_Benz]

And these are worthless too!  Thanks asic!

[Garr255]

dear friend,
i am afraid that FPGA in 6 months time will turn obsolete! (ASIC time)
i wonder if you should put your efforts to openASIC or other ASIC project!

  let's see what will happen in the next 6 months.

BFL is supposed to be taking preorders today. ASICs are bringing huge changes to Bitcoin, ones that could even effect non-miners. I believe all of these changes will be for the best in the long run though. Now we can just hope that the openasic project turns something out in the next few months!

[Raize]

BFL is supposed to be taking preorders today. ASICs are bringing huge changes to Bitcoin, ones that could even effect non-miners. I believe all of these changes will be for the best in the long run though. Now we can just hope that the openasic project turns something out in the next few months!

Yes, and they took preorders in Bitcoin primarily, and some estimates now put the amount of Bitcoin trying to be cashed out by their processor at $300,000 worth, which may be difficult for them to process in the near future. Since these preorders cannot be reversed and the estimated cost for an ASIC run is $3-5 million for all three devices and the time for development could be as long as 6 months or more, there is a very high likelihood we may see BFL not have enough money to do ASIC development for several months and the ASIC itself for several more months. In all, it could easily be a year or more before ASIC drops.

I think FPGA devices still have some play, but obviously these are all things to consider when ordering or implementing new designs. I know I would still buy Lancelots if they were developed, though I'd probably still prefer a quad-miner of some sort.

[disclaimer201]

What does the developer say? Do you have a solution for the bitstream yet? I'd love to buy one or two Lancelots rather sooner than later. Do you think it's risky to invest in FPGAs now? I'm not so worried about the energy efficiency but to achieve a high hash rate in order to still be able to compete at all with ASICs next year. I'm assuming the time for ROI is more than one year, or isn't it?

[ngzhang]

BFL is supposed to be taking preorders today. ASICs are bringing huge changes to Bitcoin, ones that could even effect non-miners. I believe all of these changes will be for the best in the long run though. Now we can just hope that the openasic project turns something out in the next few months!

Yes, and they took preorders in Bitcoin primarily, and some estimates now put the amount of Bitcoin trying to be cashed out by their processor at $300,000 worth, which may be difficult for them to process in the near future. Since these preorders cannot be reversed and the estimated cost for an ASIC run is $3-5 million for all three devices and the time for development could be as long as 6 months or more, there is a very high likelihood we may see BFL not have enough money to do ASIC development for several months and the ASIC itself for several more months. In all, it could easily be a year or more before ASIC drops.

I think FPGA devices still have some play, but obviously these are all things to consider when ordering or implementing new designs. I know I would still buy Lancelots if they were developed, though I'd probably still prefer a quad-miner of some sort.

we (my team and some other core people) consider BFL have not spend any money on ASIC development yet. BFL's business flow is: announce dreamlike specs -> taking pre-orders -> find people to development -> if succeed, release and shipment. if fail, run. BFL sell products at super low price because their customer take all risks.
so now BFL is just collecting money for their ASIC project and avoid current delivery pressure (means they are running out cheap FPGAs).
if this business model succeeded, i will classified this as a shame of human intelligence.

and let me explain what is the "now in final stage development" mean. in ASIC design flow, this means RTL design is nearly finish. as a SOC or some other complex ASIC, RTL design and testing will take most of the development time. but mining ASIC is not a RTL complex design, it is a high computing density chip. most of the work is physical design, packaging and thermal design. RTL is less than 10% of the entire work.

What does the developer say? Do you have a solution for the bitstream yet? I'd love to buy one or two Lancelots rather sooner than later. Do you think it's risky to invest in FPGAs now? I'm not so worried about the energy efficiency but to achieve a high hash rate in order to still be able to compete at all with ASICs next year. I'm assuming the time for ROI is more than one year, or isn't it?

nearly finish.
the price will let the ROI in ~6 months.

[seriouscoin]

BFL is supposed to be taking preorders today. ASICs are bringing huge changes to Bitcoin, ones that could even effect non-miners. I believe all of these changes will be for the best in the long run though. Now we can just hope that the openasic project turns something out in the next few months!

Yes, and they took preorders in Bitcoin primarily, and some estimates now put the amount of Bitcoin trying to be cashed out by their processor at $300,000 worth, which may be difficult for them to process in the near future. Since these preorders cannot be reversed and the estimated cost for an ASIC run is $3-5 million for all three devices and the time for development could be as long as 6 months or more, there is a very high likelihood we may see BFL not have enough money to do ASIC development for several months and the ASIC itself for several more months. In all, it could easily be a year or more before ASIC drops.

I think FPGA devices still have some play, but obviously these are all things to consider when ordering or implementing new designs. I know I would still buy Lancelots if they were developed, though I'd probably still prefer a quad-miner of some sort.

we (my team and some other core people) consider BFL have not spend any money on ASIC development yet. BFL's business flow is: announce dreamlike specs -> taking pre-orders -> find people to development -> if succeed, release and shipment. if fail, run. BFL sell products at super low price because their customer take all risks.
so now BFL is just collecting money for their ASIC project and avoid current delivery pressure (means they are running out cheap FPGAs).
if this business model succeeded, i will classified this as a shame of human intelligence.

and let me explain what is the "now in final stage development" mean. in ASIC design flow, this means RTL design is nearly finish. as a SOC or some other complex ASIC, RTL design and testing will take most of the development time. but mining ASIC is not a RTL complex design, it is a high computing density chip. most of the work is physical design, packaging and thermal design. RTL is less than 10% of the entire work.

What does the developer say? Do you have a solution for the bitstream yet? I'd love to buy one or two Lancelots rather sooner than later. Do you think it's risky to invest in FPGAs now? I'm not so worried about the energy efficiency but to achieve a high hash rate in order to still be able to compete at all with ASICs next year. I'm assuming the time for ROI is more than one year, or isn't it?

nearly finish.
the price will let the ROI in ~6 months.

Are you saying the ASIC specs from BFL is very optimistic?

[ngzhang]

Are you saying the ASIC specs from BFL is very optimistic?

maybe, but not optimism as their delivery date.

[luffy]

6 months ROI seems very optimistic indeed!
lets do the maths:
500MH/s (currect difficulty) = 0.26BTC/day * 30 =  7.8BTC/month * 6 = 46.8BTC/6 months
with 1BTC=6 dollars we get 280 dollars
i din't calculate electric power. (it could be 50-60 more dollars!)
are you going to sell Lancelot below 300$ !?

[fuxianhui888]

6 months ROI seems very optimistic indeed!
lets do the maths:
500MH/s (currect difficulty) = 0.26BTC/day * 30 =  7.8BTC/month * 6 = 46.8BTC/6 months
with 1BTC=6 dollars we get 280 dollars
i din't calculate electric power. (it could be 50-60 more dollars!)
are you going to sell Lancelot below 300$ !?

their new goal is get 700 mhash

[arklan]

fux, where'd you see that said? that's news to me.

[DiabloD3]

BFL is supposed to be taking preorders today. ASICs are bringing huge changes to Bitcoin, ones that could even effect non-miners. I believe all of these changes will be for the best in the long run though. Now we can just hope that the openasic project turns something out in the next few months!

Yes, and they took preorders in Bitcoin primarily, and some estimates now put the amount of Bitcoin trying to be cashed out by their processor at $300,000 worth, which may be difficult for them to process in the near future. Since these preorders cannot be reversed and the estimated cost for an ASIC run is $3-5 million for all three devices and the time for development could be as long as 6 months or more, there is a very high likelihood we may see BFL not have enough money to do ASIC development for several months and the ASIC itself for several more months. In all, it could easily be a year or more before ASIC drops.

I think FPGA devices still have some play, but obviously these are all things to consider when ordering or implementing new designs. I know I would still buy Lancelots if they were developed, though I'd probably still prefer a quad-miner of some sort.

we (my team and some other core people) consider BFL have not spend any money on ASIC development yet. BFL's business flow is: announce dreamlike specs -> taking pre-orders -> find people to development -> if succeed, release and shipment. if fail, run. BFL sell products at super low price because their customer take all risks.
so now BFL is just collecting money for their ASIC project and avoid current delivery pressure (means they are running out cheap FPGAs).
if this business model succeeded, i will classified this as a shame of human intelligence.

and let me explain what is the "now in final stage development" mean. in ASIC design flow, this means RTL design is nearly finish. as a SOC or some other complex ASIC, RTL design and testing will take most of the development time. but mining ASIC is not a RTL complex design, it is a high computing density chip. most of the work is physical design, packaging and thermal design. RTL is less than 10% of the entire work.

What does the developer say? Do you have a solution for the bitstream yet? I'd love to buy one or two Lancelots rather sooner than later. Do you think it's risky to invest in FPGAs now? I'm not so worried about the energy efficiency but to achieve a high hash rate in order to still be able to compete at all with ASICs next year. I'm assuming the time for ROI is more than one year, or isn't it?

nearly finish.
the price will let the ROI in ~6 months.

I agree with this assessment.

[jl2012]

Is it possible to use Lancelot for something else, such as Litecoin mining, protein folding, or looking for large prime numbers?

[Energizer]

BFL is supposed to be taking preorders today. ASICs are bringing huge changes to Bitcoin, ones that could even effect non-miners. I believe all of these changes will be for the best in the long run though. Now we can just hope that the openasic project turns something out in the next few months!

Yes, and they took preorders in Bitcoin primarily, and some estimates now put the amount of Bitcoin trying to be cashed out by their processor at $300,000 worth, which may be difficult for them to process in the near future. Since these preorders cannot be reversed and the estimated cost for an ASIC run is $3-5 million for all three devices and the time for development could be as long as 6 months or more, there is a very high likelihood we may see BFL not have enough money to do ASIC development for several months and the ASIC itself for several more months. In all, it could easily be a year or more before ASIC drops.

I think FPGA devices still have some play, but obviously these are all things to consider when ordering or implementing new designs. I know I would still buy Lancelots if they were developed, though I'd probably still prefer a quad-miner of some sort.

we (my team and some other core people) consider BFL have not spend any money on ASIC development yet. BFL's business flow is: announce dreamlike specs -> taking pre-orders -> find people to development -> if succeed, release and shipment. if fail, run. BFL sell products at super low price because their customer take all risks.
so now BFL is just collecting money for their ASIC project and avoid current delivery pressure (means they are running out cheap FPGAs).
if this business model succeeded, i will classified this as a shame of human intelligence.

and let me explain what is the "now in final stage development" mean. in ASIC design flow, this means RTL design is nearly finish. as a SOC or some other complex ASIC, RTL design and testing will take most of the development time. but mining ASIC is not a RTL complex design, it is a high computing density chip. most of the work is physical design, packaging and thermal design. RTL is less than 10% of the entire work.

What does the developer say? Do you have a solution for the bitstream yet? I'd love to buy one or two Lancelots rather sooner than later. Do you think it's risky to invest in FPGAs now? I'm not so worried about the energy efficiency but to achieve a high hash rate in order to still be able to compete at all with ASICs next year. I'm assuming the time for ROI is more than one year, or isn't it?

nearly finish.
the price will let the ROI in ~6 months.

Sorry ngzang! I totaly disagree with you! once again you are attacking BFL! you've done the same 6 months ago before they start shipping BFL singles! I've followed your direction at that time and invested in Icarus more than BFL singles! Now please take a close look at my position wich is similar to any of your clients/fans: 12 Icarus boards that will be worthless in couple of months and 2 BFL Singles that been paid to be upgraded to ASIC in 3 months. I know that by now you probably have invested a lot of time and effort in Lancelot and am sure its gonna be a piece of art as Icarus is! But that doesn't give you the right to turn your clients/fans into the wrong direction! BFL ASIC is real and it will hit the network soon! it may be delayed a couple of months but be sure it will be eating the network in the first month of 2013 if not earlier!

Now the question is, instead of attacking BFL. what can you do for your clients/fans? Have you ever thought of offering your clients a trade in program for Icarus to Lancelot like BFL did?

[hashking]

BFL is supposed to be taking preorders today. ASICs are bringing huge changes to Bitcoin, ones that could even effect non-miners. I believe all of these changes will be for the best in the long run though. Now we can just hope that the openasic project turns something out in the next few months!

Yes, and they took preorders in Bitcoin primarily, and some estimates now put the amount of Bitcoin trying to be cashed out by their processor at $300,000 worth, which may be difficult for them to process in the near future. Since these preorders cannot be reversed and the estimated cost for an ASIC run is $3-5 million for all three devices and the time for development could be as long as 6 months or more, there is a very high likelihood we may see BFL not have enough money to do ASIC development for several months and the ASIC itself for several more months. In all, it could easily be a year or more before ASIC drops.

I think FPGA devices still have some play, but obviously these are all things to consider when ordering or implementing new designs. I know I would still buy Lancelots if they were developed, though I'd probably still prefer a quad-miner of some sort.

we (my team and some other core people) consider BFL have not spend any money on ASIC development yet. BFL's business flow is: announce dreamlike specs -> taking pre-orders -> find people to development -> if succeed, release and shipment. if fail, run. BFL sell products at super low price because their customer take all risks.
so now BFL is just collecting money for their ASIC project and avoid current delivery pressure (means they are running out cheap FPGAs).
if this business model succeeded, i will classified this as a shame of human intelligence.

and let me explain what is the "now in final stage development" mean. in ASIC design flow, this means RTL design is nearly finish. as a SOC or some other complex ASIC, RTL design and testing will take most of the development time. but mining ASIC is not a RTL complex design, it is a high computing density chip. most of the work is physical design, packaging and thermal design. RTL is less than 10% of the entire work.

What does the developer say? Do you have a solution for the bitstream yet? I'd love to buy one or two Lancelots rather sooner than later. Do you think it's risky to invest in FPGAs now? I'm not so worried about the energy efficiency but to achieve a high hash rate in order to still be able to compete at all with ASICs next year. I'm assuming the time for ROI is more than one year, or isn't it?

nearly finish.
the price will let the ROI in ~6 months.

Sorry ngzang! I totaly disagree with you! once again you are attacking BFL! you've done the same 6 months ago before they start shipping BFL singles! I've followed your direction at that time and invested in Icarus more than BFL singles! Now please take a close look at my position wich is similar to any of your clients/fans: 12 Icarus boards that will be worthless in couple of months and 2 BFL Singles that been paid to be upgraded to ASIC in 3 months. I know that by now you probably have invested a lot of time and effort in Lancelot and am sure its gonna be a piece of art as Icarus is! But that doesn't give you the right to turn your clients/fans into the wrong direction! BFL ASIC is real and it will hit the network soon! it may be delayed a couple of months but be sure it will be eating the network in the first month of 2013 if not earlier!

Now the question is, instead of attacking BFL! what can you do for your clients/fans? Did you even think about offering your clients a trade in program for Icarus to Lancelot? you didn't! but BFL did!

Do you really think BFL is giving you a deal with the trade in.  First off, they kept everyone's funds for months without shipping anything.  Then when they start shipping a small amount of the equipment, they tell everyone they are going to sell ASICS.  It doesn't take a smart person to figure it out but they just made you lock up more money for who knows how long this time.  I'm sure BFL could have sold their ASICS products for less money but then they wouldn't make you feel like you are getting a deal.  BFL is full of S***.  

[Energizer]

BFL is supposed to be taking preorders today. ASICs are bringing huge changes to Bitcoin, ones that could even effect non-miners. I believe all of these changes will be for the best in the long run though. Now we can just hope that the openasic project turns something out in the next few months!

Yes, and they took preorders in Bitcoin primarily, and some estimates now put the amount of Bitcoin trying to be cashed out by their processor at $300,000 worth, which may be difficult for them to process in the near future. Since these preorders cannot be reversed and the estimated cost for an ASIC run is $3-5 million for all three devices and the time for development could be as long as 6 months or more, there is a very high likelihood we may see BFL not have enough money to do ASIC development for several months and the ASIC itself for several more months. In all, it could easily be a year or more before ASIC drops.

I think FPGA devices still have some play, but obviously these are all things to consider when ordering or implementing new designs. I know I would still buy Lancelots if they were developed, though I'd probably still prefer a quad-miner of some sort.

we (my team and some other core people) consider BFL have not spend any money on ASIC development yet. BFL's business flow is: announce dreamlike specs -> taking pre-orders -> find people to development -> if succeed, release and shipment. if fail, run. BFL sell products at super low price because their customer take all risks.
so now BFL is just collecting money for their ASIC project and avoid current delivery pressure (means they are running out cheap FPGAs).
if this business model succeeded, i will classified this as a shame of human intelligence.

and let me explain what is the "now in final stage development" mean. in ASIC design flow, this means RTL design is nearly finish. as a SOC or some other complex ASIC, RTL design and testing will take most of the development time. but mining ASIC is not a RTL complex design, it is a high computing density chip. most of the work is physical design, packaging and thermal design. RTL is less than 10% of the entire work.

What does the developer say? Do you have a solution for the bitstream yet? I'd love to buy one or two Lancelots rather sooner than later. Do you think it's risky to invest in FPGAs now? I'm not so worried about the energy efficiency but to achieve a high hash rate in order to still be able to compete at all with ASICs next year. I'm assuming the time for ROI is more than one year, or isn't it?

nearly finish.
the price will let the ROI in ~6 months.

Sorry ngzang! I totaly disagree with you! once again you are attacking BFL! you've done the same 6 months ago before they start shipping BFL singles! I've followed your direction at that time and invested in Icarus more than BFL singles! Now please take a close look at my position wich is similar to any of your clients/fans: 12 Icarus boards that will be worthless in couple of months and 2 BFL Singles that been paid to be upgraded to ASIC in 3 months. I know that by now you probably have invested a lot of time and effort in Lancelot and am sure its gonna be a piece of art as Icarus is! But that doesn't give you the right to turn your clients/fans into the wrong direction! BFL ASIC is real and it will hit the network soon! it may be delayed a couple of months but be sure it will be eating the network in the first month of 2013 if not earlier!

Now the question is, instead of attacking BFL! what can you do for your clients/fans? Did you even think about offering your clients a trade in program for Icarus to Lancelot? you didn't! but BFL did!

Do you really think BFL is giving you a deal with the trade in.  First off, they kept everyone's funds for months without shipping anything.  Then when they start shipping a small amount of the equipment, they tell everyone they are going to sell ASICS.  It doesn't take a smart person to figure it out but they just made you lock up more money for who knows how long this time.  I'm sure BFL could have sold their ASICS products for less money but then they wouldn't make you feel like you are getting a deal.  BFL is full of S***.  

Yes I do! and am not the only one!

[disclaimer201]

BFL is supposed to be taking preorders today. ASICs are bringing huge changes to Bitcoin, ones that could even effect non-miners. I believe all of these changes will be for the best in the long run though. Now we can just hope that the openasic project turns something out in the next few months!

Yes, and they took preorders in Bitcoin primarily, and some estimates now put the amount of Bitcoin trying to be cashed out by their processor at $300,000 worth, which may be difficult for them to process in the near future. Since these preorders cannot be reversed and the estimated cost for an ASIC run is $3-5 million for all three devices and the time for development could be as long as 6 months or more, there is a very high likelihood we may see BFL not have enough money to do ASIC development for several months and the ASIC itself for several more months. In all, it could easily be a year or more before ASIC drops.

I think FPGA devices still have some play, but obviously these are all things to consider when ordering or implementing new designs. I know I would still buy Lancelots if they were developed, though I'd probably still prefer a quad-miner of some sort.

we (my team and some other core people) consider BFL have not spend any money on ASIC development yet. BFL's business flow is: announce dreamlike specs -> taking pre-orders -> find people to development -> if succeed, release and shipment. if fail, run. BFL sell products at super low price because their customer take all risks.
so now BFL is just collecting money for their ASIC project and avoid current delivery pressure (means they are running out cheap FPGAs).
if this business model succeeded, i will classified this as a shame of human intelligence.

and let me explain what is the "now in final stage development" mean. in ASIC design flow, this means RTL design is nearly finish. as a SOC or some other complex ASIC, RTL design and testing will take most of the development time. but mining ASIC is not a RTL complex design, it is a high computing density chip. most of the work is physical design, packaging and thermal design. RTL is less than 10% of the entire work.

What does the developer say? Do you have a solution for the bitstream yet? I'd love to buy one or two Lancelots rather sooner than later. Do you think it's risky to invest in FPGAs now? I'm not so worried about the energy efficiency but to achieve a high hash rate in order to still be able to compete at all with ASICs next year. I'm assuming the time for ROI is more than one year, or isn't it?

nearly finish.
the price will let the ROI in ~6 months.

Sorry ngzang! I totaly disagree with you! once again you are attacking BFL! you've done the same 6 months ago before they start shipping BFL singles! I've followed your direction at that time and invested in Icarus more than BFL singles! Now please take a close look at my position wich is similar to any of your clients/fans: 12 Icarus boards that will be worthless in couple of months and 2 BFL Singles that been paid to be upgraded to ASIC in 3 months. I know that by now you probably have invested a lot of time and effort in Lancelot and am sure its gonna be a piece of art as Icarus is! But that doesn't give you the right to turn your clients/fans into the wrong direction! BFL ASIC is real and it will hit the network soon! it may be delayed a couple of months but be sure it will be eating the network in the first month of 2013 if not earlier!

Now the question is, instead of attacking BFL! what can you do for your clients/fans? Did you even think about offering your clients a trade in program for Icarus to Lancelot? you didn't! but BFL did!

Do you really think BFL is giving you a deal with the trade in.  First off, they kept everyone's funds for months without shipping anything.  Then when they start shipping a small amount of the equipment, they tell everyone they are going to sell ASICS.  It doesn't take a smart person to figure it out but they just made you lock up more money for who knows how long this time.  I'm sure BFL could have sold their ASICS products for less money but then they wouldn't make you feel like you are getting a deal.  BFL is full of S***.  

Yes I do! and am not the only one!

Funny how one can see the factual as hypothetical (your FPGA units making you money for some time now) and the hypothetical as factual (past BFL promises replaced with future BFL promises while already being out of real money with nothing to show for it). You should be thankful for the Icarus boards for they are the only that make you money at the moment and probably will be for a long time even if BFL does ship Asics sometime next spring.

[hashking]

BFL is supposed to be taking preorders today. ASICs are bringing huge changes to Bitcoin, ones that could even effect non-miners. I believe all of these changes will be for the best in the long run though. Now we can just hope that the openasic project turns something out in the next few months!

Yes, and they took preorders in Bitcoin primarily, and some estimates now put the amount of Bitcoin trying to be cashed out by their processor at $300,000 worth, which may be difficult for them to process in the near future. Since these preorders cannot be reversed and the estimated cost for an ASIC run is $3-5 million for all three devices and the time for development could be as long as 6 months or more, there is a very high likelihood we may see BFL not have enough money to do ASIC development for several months and the ASIC itself for several more months. In all, it could easily be a year or more before ASIC drops.

I think FPGA devices still have some play, but obviously these are all things to consider when ordering or implementing new designs. I know I would still buy Lancelots if they were developed, though I'd probably still prefer a quad-miner of some sort.

we (my team and some other core people) consider BFL have not spend any money on ASIC development yet. BFL's business flow is: announce dreamlike specs -> taking pre-orders -> find people to development -> if succeed, release and shipment. if fail, run. BFL sell products at super low price because their customer take all risks.
so now BFL is just collecting money for their ASIC project and avoid current delivery pressure (means they are running out cheap FPGAs).
if this business model succeeded, i will classified this as a shame of human intelligence.

and let me explain what is the "now in final stage development" mean. in ASIC design flow, this means RTL design is nearly finish. as a SOC or some other complex ASIC, RTL design and testing will take most of the development time. but mining ASIC is not a RTL complex design, it is a high computing density chip. most of the work is physical design, packaging and thermal design. RTL is less than 10% of the entire work.

What does the developer say? Do you have a solution for the bitstream yet? I'd love to buy one or two Lancelots rather sooner than later. Do you think it's risky to invest in FPGAs now? I'm not so worried about the energy efficiency but to achieve a high hash rate in order to still be able to compete at all with ASICs next year. I'm assuming the time for ROI is more than one year, or isn't it?

nearly finish.
the price will let the ROI in ~6 months.

Sorry ngzang! I totaly disagree with you! once again you are attacking BFL! you've done the same 6 months ago before they start shipping BFL singles! I've followed your direction at that time and invested in Icarus more than BFL singles! Now please take a close look at my position wich is similar to any of your clients/fans: 12 Icarus boards that will be worthless in couple of months and 2 BFL Singles that been paid to be upgraded to ASIC in 3 months. I know that by now you probably have invested a lot of time and effort in Lancelot and am sure its gonna be a piece of art as Icarus is! But that doesn't give you the right to turn your clients/fans into the wrong direction! BFL ASIC is real and it will hit the network soon! it may be delayed a couple of months but be sure it will be eating the network in the first month of 2013 if not earlier!

Now the question is, instead of attacking BFL! what can you do for your clients/fans? Did you even think about offering your clients a trade in program for Icarus to Lancelot? you didn't! but BFL did!

Do you really think BFL is giving you a deal with the trade in.  First off, they kept everyone's funds for months without shipping anything.  Then when they start shipping a small amount of the equipment, they tell everyone they are going to sell ASICS.  It doesn't take a smart person to figure it out but they just made you lock up more money for who knows how long this time.  I'm sure BFL could have sold their ASICS products for less money but then they wouldn't make you feel like you are getting a deal.  BFL is full of S***.  

Yes I do! and am not the only one!

Lol, and that is why the suckers keep lining up at the door. 

[Energizer]

BFL is supposed to be taking preorders today. ASICs are bringing huge changes to Bitcoin, ones that could even effect non-miners. I believe all of these changes will be for the best in the long run though. Now we can just hope that the openasic project turns something out in the next few months!

Yes, and they took preorders in Bitcoin primarily, and some estimates now put the amount of Bitcoin trying to be cashed out by their processor at $300,000 worth, which may be difficult for them to process in the near future. Since these preorders cannot be reversed and the estimated cost for an ASIC run is $3-5 million for all three devices and the time for development could be as long as 6 months or more, there is a very high likelihood we may see BFL not have enough money to do ASIC development for several months and the ASIC itself for several more months. In all, it could easily be a year or more before ASIC drops.

I think FPGA devices still have some play, but obviously these are all things to consider when ordering or implementing new designs. I know I would still buy Lancelots if they were developed, though I'd probably still prefer a quad-miner of some sort.

we (my team and some other core people) consider BFL have not spend any money on ASIC development yet. BFL's business flow is: announce dreamlike specs -> taking pre-orders -> find people to development -> if succeed, release and shipment. if fail, run. BFL sell products at super low price because their customer take all risks.
so now BFL is just collecting money for their ASIC project and avoid current delivery pressure (means they are running out cheap FPGAs).
if this business model succeeded, i will classified this as a shame of human intelligence.

and let me explain what is the "now in final stage development" mean. in ASIC design flow, this means RTL design is nearly finish. as a SOC or some other complex ASIC, RTL design and testing will take most of the development time. but mining ASIC is not a RTL complex design, it is a high computing density chip. most of the work is physical design, packaging and thermal design. RTL is less than 10% of the entire work.

What does the developer say? Do you have a solution for the bitstream yet? I'd love to buy one or two Lancelots rather sooner than later. Do you think it's risky to invest in FPGAs now? I'm not so worried about the energy efficiency but to achieve a high hash rate in order to still be able to compete at all with ASICs next year. I'm assuming the time for ROI is more than one year, or isn't it?

nearly finish.
the price will let the ROI in ~6 months.

Sorry ngzang! I totaly disagree with you! once again you are attacking BFL! you've done the same 6 months ago before they start shipping BFL singles! I've followed your direction at that time and invested in Icarus more than BFL singles! Now please take a close look at my position wich is similar to any of your clients/fans: 12 Icarus boards that will be worthless in couple of months and 2 BFL Singles that been paid to be upgraded to ASIC in 3 months. I know that by now you probably have invested a lot of time and effort in Lancelot and am sure its gonna be a piece of art as Icarus is! But that doesn't give you the right to turn your clients/fans into the wrong direction! BFL ASIC is real and it will hit the network soon! it may be delayed a couple of months but be sure it will be eating the network in the first month of 2013 if not earlier!

Now the question is, instead of attacking BFL! what can you do for your clients/fans? Did you even think about offering your clients a trade in program for Icarus to Lancelot? you didn't! but BFL did!

Do you really think BFL is giving you a deal with the trade in.  First off, they kept everyone's funds for months without shipping anything.  Then when they start shipping a small amount of the equipment, they tell everyone they are going to sell ASICS.  It doesn't take a smart person to figure it out but they just made you lock up more money for who knows how long this time.  I'm sure BFL could have sold their ASICS products for less money but then they wouldn't make you feel like you are getting a deal.  BFL is full of S***.  

Yes I do! and am not the only one!

Funny how one can see the factual as hypothetical (your FPGA units making you money for some time now) and the hypothetical as factual (past BFL promises replaced with future BFL promises while already being out of real money with nothing to show for it). You should be thankful for the Icarus boards for they are the only that make you money at the moment and probably will be for a long time even if BFL does ship Asics sometime next spring.

I totally agree with you! Today Icarus is extremely profitable and will continue to be up until the block reward switches to 25 BTC or ASIC hits the network! But there is a missing part in your equation! what if BFL really delivers ASIC in October? or even January? By then Icarus will produce between minimum 1 maximum 5% BTC of what its currently producing! and if am lucky enough I would be able to sell it out for 100 USD! The value that I will lose in the hardware will be higher than the mined BTC value in the coming months!

I forgot to tell you that I've just bought 6 Icarus boards last month @ 500$ including shipment and tax! The hypothetical vision makes more sense for me here! If the factual vision makes more sense for you or anyone who is still interested in Icarus, I offer my newly arrived 6 Icarus boards @ 380 USD!

[Energizer]

BFL is supposed to be taking preorders today. ASICs are bringing huge changes to Bitcoin, ones that could even effect non-miners. I believe all of these changes will be for the best in the long run though. Now we can just hope that the openasic project turns something out in the next few months!

Yes, and they took preorders in Bitcoin primarily, and some estimates now put the amount of Bitcoin trying to be cashed out by their processor at $300,000 worth, which may be difficult for them to process in the near future. Since these preorders cannot be reversed and the estimated cost for an ASIC run is $3-5 million for all three devices and the time for development could be as long as 6 months or more, there is a very high likelihood we may see BFL not have enough money to do ASIC development for several months and the ASIC itself for several more months. In all, it could easily be a year or more before ASIC drops.

I think FPGA devices still have some play, but obviously these are all things to consider when ordering or implementing new designs. I know I would still buy Lancelots if they were developed, though I'd probably still prefer a quad-miner of some sort.

we (my team and some other core people) consider BFL have not spend any money on ASIC development yet. BFL's business flow is: announce dreamlike specs -> taking pre-orders -> find people to development -> if succeed, release and shipment. if fail, run. BFL sell products at super low price because their customer take all risks.
so now BFL is just collecting money for their ASIC project and avoid current delivery pressure (means they are running out cheap FPGAs).
if this business model succeeded, i will classified this as a shame of human intelligence.

and let me explain what is the "now in final stage development" mean. in ASIC design flow, this means RTL design is nearly finish. as a SOC or some other complex ASIC, RTL design and testing will take most of the development time. but mining ASIC is not a RTL complex design, it is a high computing density chip. most of the work is physical design, packaging and thermal design. RTL is less than 10% of the entire work.

What does the developer say? Do you have a solution for the bitstream yet? I'd love to buy one or two Lancelots rather sooner than later. Do you think it's risky to invest in FPGAs now? I'm not so worried about the energy efficiency but to achieve a high hash rate in order to still be able to compete at all with ASICs next year. I'm assuming the time for ROI is more than one year, or isn't it?

nearly finish.
the price will let the ROI in ~6 months.

Sorry ngzang! I totaly disagree with you! once again you are attacking BFL! you've done the same 6 months ago before they start shipping BFL singles! I've followed your direction at that time and invested in Icarus more than BFL singles! Now please take a close look at my position wich is similar to any of your clients/fans: 12 Icarus boards that will be worthless in couple of months and 2 BFL Singles that been paid to be upgraded to ASIC in 3 months. I know that by now you probably have invested a lot of time and effort in Lancelot and am sure its gonna be a piece of art as Icarus is! But that doesn't give you the right to turn your clients/fans into the wrong direction! BFL ASIC is real and it will hit the network soon! it may be delayed a couple of months but be sure it will be eating the network in the first month of 2013 if not earlier!

Now the question is, instead of attacking BFL! what can you do for your clients/fans? Did you even think about offering your clients a trade in program for Icarus to Lancelot? you didn't! but BFL did!

Do you really think BFL is giving you a deal with the trade in.  First off, they kept everyone's funds for months without shipping anything.  Then when they start shipping a small amount of the equipment, they tell everyone they are going to sell ASICS.  It doesn't take a smart person to figure it out but they just made you lock up more money for who knows how long this time.  I'm sure BFL could have sold their ASICS products for less money but then they wouldn't make you feel like you are getting a deal.  BFL is full of S***.  

Yes I do! and am not the only one!

Lol, and that is why the suckers keep lining up at the door.  

Do you mean the lending service door?

[bulanula]

I totally agree with you! Today Icarus is extremely profitable and will continue to be up until the block reward switches to 25 BTC or ASIC hits the network! But there is a missing part in your equation! what if BFL really delivers ASIC in October? or even January? By then Icarus will produce between minimum 1 maximum 5% BTC of what its currently producing! and if am lucky enough I would be able to sell it out for 100 USD! The value that I will lose in the hardware will be higher than the mined BTC value in the coming months!

I forgot to tell you that I've just bought 6 Icarus boards last month @ 500$ including shipment and tax! The hypothetical vision makes more sense for me here! If the factual vision makes more sense for you or anyone who is still interested in Icarus, I offer my newly arrived 6 Icarus boards @ 380 USD!

At least someone sees the light.

These spartans are only worth like $100 on the market now with 28nm FPGA coming.

This dude is making a killing.

Buy FPGA now and you are literally throwing your money in the wind ... never will be ROI paid back.

When you get break even ( mine enough BTC to pay off device cost in USD ) then you still have not made any profit since these devices are worth like $0.

Good luck trying to sell them when ASIC hits and more power to you trying to sell your crappy FPGA to industry that is now using all new 28nm FPGA.

This is not GPUs mate. This FPGA stuff is now totally useless with ASIC coming.

I doubt BFL ASIC is not going to come since they have like $400k in sales already.

Good luck losing your money on SPARTA !!!

[punin]

I forgot to tell you that I've just bought 6 Icarus boards last month @ 500$ including shipment and tax! The hypothetical vision makes more sense for me here! If the factual vision makes more sense for you or anyone who is still interested in Icarus, I offer my newly arrived 6 Icarus boards @ 380 USD!

Where are you located? I'll take them.

[Coinoisseur]

take a close look at my position wich is similar to any of your clients/fans: 12 Icarus boards that will be hashing from the day I receive them until the day they die or are shelved/sold and 2 BFL Singles that been paid to be upgraded to ASIC whenever BFL has some to sell and I get a good place in line. I know that by now you probably have invested a lot of time and effort in Lancelot and am sure its gonna be a piece of art as Icarus is! But that doesn't give you the right to turn your clients/fans into the wrong direction! BFL ASIC announcement is real and it may hit the network as long as it isn't canceled, BFL stays around as a going concern, and nothing unforeseen changes the hashing landscape! it may be delayed for an indeterminate time period but be sure it will be eating the network once it exists and starts hashing!

Now the question is, instead of attacking BFL. what can you do for your clients/fans? Have you ever thought of offering your clients a trade in program for Icarus to Lancelot like BFL did?

Made some changes in bold that I think better demonstrate the degree of certainty that is potential ASIC availability.

[Energizer]

I've created a new thread to sell my Icarus boards:
https://bitcointalk.org/index.php?topic=90956.0

[seriouscoin]

So this project is never done huh ? 

Its now July already.

[wildemagic]

Boards were completed, but bitstream issues were encountered, I think in the light of *** announcement hes wound down the project.

kind regards

[bulanula]

Boards were completed, but bitstream issues were encountered, I think in the light of *** announcement hes wound down the project.

kind regards

So now *** automatically gets censored to *** in this forum subsection

[wildemagic]

So now *** automatically gets censored to *** in this forum subsection

No its just that every thread seems to mention ***
So astute persons self censor in the face of every thread containing *** either in the heading or the body.

I dont like to mention *** in a thread that clearly isnt about *** <grins>

kind regards

[Dexter770221]

If this is only a bitstream issue i sugest to start selling without bitstream for those that want to order development version. They will easy download bitstream later. And now loded it with Icarus bitstream.
It's really not long when BFL wil release their ASIC's so this project needs to be realesed very soon. Other way only few person will buy it. Perssonaly I buy it only becuse it can be used for something else and I have few projects in my work where FPGA's can have their jobs to be done.
Development boards costs enormous amount of money so Lancelot is real candy on the cake.
ngzang HURRY UP.

[wildemagic]

i sugest to start selling without bitstream for those that want to order development version

If it were just a case of installing the icarus bitstream, even the 200mhz version, then I think ngzhang may have already done this.
Perhaps there are other issues too.

kind regards

[midnightmagic]

I'm a huge ngzhang fan; the open-source nature of Icarus is the biggest reason why I think Icarus was such a special project.

I just wanted to say that we are making a fundamental assumption here: that BFL is doing its own design work. It is possible that it simply acquired the work that another company was already doing, and thus got the jump on development efforts. (For example, it might be that LargeCoin is much further along, developmentally, and they either partnered with or were bought out by, BFL with an agreement about money influx.) So it is very possible that even though BFL hasn't actually put any money into real ASIC design, they are using their reputation from the prior minirigs and singles to help LargeCoin, which got a lot of flak for an unfair business plan.

[wildemagic]

[stuff]

Seriously?  Perhaps this is better posted in the speculation sub-forum since it has nothing to do with the icarus hardware.

kind regards

[ChiangYay]

I  think the point is:
if ngzang can not come up with an ASIC project soon he will be out of the market in about 8 months like all the others FGPAs producers.
I'm very sorry for him because I'm a big fan and I would be happy see a ngzang ASIC.
It would be nice if the community could help him to find a financier instead of pushing him to hurry in a project without hope, he will waste only money and time.
I'm sorry if I disappoint anyone with my post but the strategy of BFL is working.

Dexter you are also saying "Perssonaly I buy it only becuse it can be used for something else"
In other words he should produce in hurry a device that will not be competitive , and that will ruin him, so you could use it for something else.
Good luck.

ChiangYay

If this is only a bitstream issue i sugest to start selling without bitstream for those that want to order development version. They will easy download bitstream later. And now loded it with Icarus bitstream.
It's really not long when BFL wil release their ASIC's so this project needs to be realesed very soon. Other way only few person will buy it. Perssonaly I buy it only becuse it can be used for something else and I have few projects in my work where FPGA's can have their jobs to be done.
Development boards costs enormous amount of money so Lancelot is real candy on the cake.
ngzang HURRY UP.

[disclaimer201]

Ngzang, can Lancelot be equipped with cache and programmed to mine Litecoins, too? I'm still in for buying in that case!

[Icoin]

I  think the point is:
if ngzang can not come up with an ASIC project soon he will be out of the market in about 8 months like all the others FGPAs producers.
I'm very sorry for him because I'm a big fan and I would be happy see a ngzang ASIC.
It would be nice if the community could help him to find a financier instead of pushing him to hurry in a project without hope, he will waste only money and time.
I'm sorry if I disappoint anyone with my post but the strategy of BFL is working.

Dexter you are also saying "Perssonaly I buy it only becuse it can be used for something else"
In other words he should produce in hurry a device that will not be competitive , and that will ruin him, so you could use it for something else.
Good luck.

I doubt that BFL will come up with a ASICS anytime soon, in my opinion thats just a marketing strategy. Even if they would come up with ASIC - the next generation FPGA (28 nm) is allready on the market (You know if the ASICS will be merged mining capable?).

Thats why the GMP https://cryptostocks.com/securities/9 will work with boards that incoroporates Spartan 6 or even Artix 7 the bitstream problem will be solved, the hardware design of Lancelot looks great and is very usable, aswell as the fact that Lancelot is an open project BFL is not.

[wildemagic]

<sigh> another hijack about ***.  There are plenty of other threads with *** speculation.

kind regards

[disclaimer201]

<sigh> another hijack about ***.  There are plenty of other threads with *** speculation.

kind regards

What's so bad about that? People want to know if it makes sense to even invest in FPGA's anymore at all at this point.
Give me a reason that I don't have to throw away my investment after difficulty skyrockets...so far there were very few things you can do with FPGAs, if any.
And taking that risk is just not a smart business decision.

[wildemagic]

[stuff]

erm, read back dude, I was talking about the two thread hijackers, your thread was actually quite interesting.
I think once difficulty raises too high ppl will get real interested in rolling bitstreams that will do litecoin.

kind regards

[ChiangYay]

I  think the point is:
if ngzang can not come up with an ASIC project soon he will be out of the market in about 8 months like all the others FGPAs producers.
I'm very sorry for him because I'm a big fan and I would be happy see a ngzang ASIC.
It would be nice if the community could help him to find a financier instead of pushing him to hurry in a project without hope, he will waste only money and time.
I'm sorry if I disappoint anyone with my post but the strategy of BFL is working.

Dexter you are also saying "Perssonaly I buy it only becuse it can be used for something else"
In other words he should produce in hurry a device that will not be competitive , and that will ruin him, so you could use it for something else.
Good luck.

I doubt that BFL will come up with a ASICS anytime soon, in my opinion thats just a marketing strategy. Even if they would come up with ASIC - the next generation FPGA (28 nm) is allready on the market (You know if the ASICS will be merged mining capable?).

Thats why the GMP https://cryptostocks.com/securities/9 will work with boards that incoroporates Spartan 6 or even Artix 7 the bitstream problem will be solved, the hardware design of Lancelot looks great and is very usable, aswell as the fact that Lancelot is an open project BFL is not.

You don't know what Artix 7 is and how much it cost. 
 
You are just a spammer using this thread to market your GMP B.S.

[Icoin]

You don't know what Artix 7 is and how much it cost.
 
You are just a spammer using this thread to market your GMP B.S.

http://en.wikipedia.org/wiki/Xilinx
The Artix-7 family delivers 50 percent lower power and 35 percent lower cost compared to the Spartan-6 family and is based on the unified Virtex-series architecture. Xilinx claims that Artix-7 FPGAs deliver the performance required to address cost-sensitive, high-volume markets previously served by ASSPs, ASICs, and low-cost FPGAs. The Artix family is designed to address the small form factor and low power performance requirements of battery-powered portable ultrasound equipment, commercial digital camera lens control, and military avionics and communications equipment

According to my sources Artix7 (28nm) evaluation versions are allready out on the market and will be fully avalable early next year. The price depends on the casing and features of the chip. (Of course i cant talk about other markets then DACH) but avarage pricing for the comercial grade will be around 200 dollar.

Its not nice to write in a such offensive way, since you dnt seems to have any clou who i am. Of course i promote the GLARI mining project it will use Lancelot boards and we fully stand behind the development of ngzhang.
Instead of arguing that the Artix7 is the wrong chip for the mining purpose and you would suggest an other one, you just attack - that doesnt show yourself in a good light ChiangYay

[ChiangYay]

You don't know what Artix 7 is and how much it cost.
 
You are just a spammer using this thread to market your GMP B.S.

http://en.wikipedia.org/wiki/Xilinx
The Artix-7 family delivers 50 percent lower power and 35 percent lower cost compared to the Spartan-6 family and is based on the unified Virtex-series architecture. Xilinx claims that Artix-7 FPGAs deliver the performance required to address cost-sensitive, high-volume markets previously served by ASSPs, ASICs, and low-cost FPGAs. The Artix family is designed to address the small form factor and low power performance requirements of battery-powered portable ultrasound equipment, commercial digital camera lens control, and military avionics and communications equipment

According to my sources Artix7 (28nm) evaluation versions are allready out on the market and will be fully avalable early next year. The price depends on the casing and features of the chip. (Of course i cant talk about other markets then DACH) but avarage pricing for the comercial grade will be around 200 dollar.

Its not nice to write in a such offensive way, since you dnt seems to have any clou who i am. Of course i promote the GLARI mining project it will use Lancelot boards and we fully stand behind the development of ngzhang.
Instead of arguing that the Artix7 is the wrong chip for the mining purpose and you would suggest an other one, you just attack - that doesnt show yourself in a good light ChiangYay

 
It's better to check what have already been said about Artix 7 expansively on the forum before  showing  just a search on Vikipedia.
>> low power performance requirements of battery-powered portable ultrasound equipment, commercial digital camera lens control, and military avionics and communications equipment<<
Here we are talking of Ghash/s not  digital camera lens etc..

For your info read this as an example from somebody working for a large company that is a huge user of Xilinx FPGAs
https://bitcointalk.org/index.php?topic=91710.msg1011562#msg1011562

[However, based on this pricing Xilinx has shown us for the Virtex 7 devices, I would expect the low volume price of the V7 2000 device (their largest ever) to be at least $10,000 in low volume.  The low volume price for the largest V6 device right now is over 12k.  I'd guess once the V7-2000T finally goes in to production, even if you could get the deep discounts, you'd probably have to pay 3-5k each.]

I know who you are. You are a spammer with nothing in your hand only bubbles. Even a monkey watching your site and the pictures can understand that.
https://cryptostocks.com/securities/9
 
Now go back to sale Stevia Rebaudiana Seeds from Paraguay somewhere else.  
https://bitcointalk.org/index.php?topic=92077.msg1014475#msg1014475

Nobody here is so stupid to buy a share  of your ghost company and we like Bitcoin not Stevia Rebaudiana Seeds.
Stop trolling and spamming in this serious thread.

[DiabloD3]

You don't know what Artix 7 is and how much it cost.
 
You are just a spammer using this thread to market your GMP B.S.

http://en.wikipedia.org/wiki/Xilinx
The Artix-7 family delivers 50 percent lower power and 35 percent lower cost compared to the Spartan-6 family and is based on the unified Virtex-series architecture. Xilinx claims that Artix-7 FPGAs deliver the performance required to address cost-sensitive, high-volume markets previously served by ASSPs, ASICs, and low-cost FPGAs. The Artix family is designed to address the small form factor and low power performance requirements of battery-powered portable ultrasound equipment, commercial digital camera lens control, and military avionics and communications equipment

According to my sources Artix7 (28nm) evaluation versions are allready out on the market and will be fully avalable early next year. The price depends on the casing and features of the chip. (Of course i cant talk about other markets then DACH) but avarage pricing for the comercial grade will be around 200 dollar.

Its not nice to write in a such offensive way, since you dnt seems to have any clou who i am. Of course i promote the GLARI mining project it will use Lancelot boards and we fully stand behind the development of ngzhang.
Instead of arguing that the Artix7 is the wrong chip for the mining purpose and you would suggest an other one, you just attack - that doesnt show yourself in a good light ChiangYay

Bull shit. You are full of bull shit.
It's better to check what have already been said about Artix 7 expansively on the forum before  showing  just a search on Vikipedia.
>> low power performance requirements of battery-powered portable ultrasound equipment, commercial digital camera lens control, and military avionics and communications equipment<<
Here we are talking of Ghash/s not  digital camera lens etc..

For your info read this as an example from somebody working for a large company that is a huge user of Xilinx FPGAs
https://bitcointalk.org/index.php?topic=91710.msg1011562#msg1011562

[However, based on this pricing Xilinx has shown us for the Virtex 7 devices, I would expect the low volume price of the V7 2000 device (their largest ever) to be at least $10,000 in low volume.  The low volume price for the largest V6 device right now is over 12k.  I'd guess once the V7-2000T finally goes in to production, even if you could get the deep discounts, you'd probably have to pay 3-5k each.]

I know who you are. You are a spammer with nothing in your hand only bubbles. Even a monkey watching your site and the pictures can understand that.
https://cryptostocks.com/securities/9
 
Now go back to sale Stevia Rebaudiana Seeds from Paraguay somewhere else.  
https://bitcointalk.org/index.php?topic=92077.msg1014475#msg1014475

Nobody here is so stupid to buy a share  of your ghost company and we like Bitcoin not Stevia Rebaudiana Seeds.
Stop trolling and spamming in this serious thread.

Angry neighborhood bastard mod here.

Cool it.

[ChiangYay]

Right. I will.

[ngzhang]

UP.

add some information. 

sorry guys, i'm extremely busy these days... my adviser give me tons of work to do, and i review the HDL codes with other developers to mid-night everyday. 

will catch up with all emails and messages next week.

[Dexter770221]

Finally some info. Can't wait to preorder

[arklan]

very good to hear.

[Energizer]

Is the 550 MH/s bitstream compatible with Icarus?

[wildemagic]

Is the 550 MH/s bitstream compatible with Icarus?

Im going to go out on a limb here and say a big NO.

550MH/s on icarus would require a 275 on what was a 190 clock device.  Ngzhang already said that 200mhz was not recommended.

Unless there is some other wigery going on that increases hashrate efficiency greatly without clock increases.

kind regards

[ngzhang]

Is the 550 MH/s bitstream compatible with Icarus?

Im going to go out on a limb here and say a big NO.

550MH/s on icarus would require a 275 on what was a 190 clock device.  Ngzhang already said that 200mhz was not recommended.

Unless there is some other wigery going on that increases hashrate efficiency greatly without clock increases.

kind regards

The answer is a big YES.
But only for MY Icarus customers. 

[wildemagic]

But only for MY Icarus customers. 

Are icarus users that didnt buy directly from you excluded? If so, thats a pity.

The answer is a big YES.

I probably should have specified in my previous post that Its doubtful that the bitstream will do 550MH/s on icarus, not that it wouldnt work on icarus (which you have already confirmed that it would)

kind regards

[tucenaber]

The answer is a big YES.
But only for MY Icarus customers. 

What does this mean? Who are the customers that are not yours? I'm confused. I was part of the last "group order" and that was handled by Xiangfu by your choice. I really hope you consider me your customer

[kano]

At a guess? - the other boards using (or trying to use) the Icarus bitstream?

[ngzhang]

At a guess? - the other boards using (or trying to use) the Icarus bitstream?

smart 

[Energizer]

So when will the new bitstream be available for Icarus?

[tidus_13]

At a guess? - the other boards using (or trying to use) the Icarus bitstream?

smart 

like yohan´s Quad XC6SLX150 ... so it means that only will work for Icarus board...Nice!

[Beaflag VonRathburg]

7/17 has come and passed. I'm interested to hear about the first production run.

[Trance104]

I'd be interested in purchasing one if/when these are ready.

[Raize]

Update? ngzhang?

[wildemagic]

Update? ngzhang?

From his profile :

Last Active: 23-07-2012, 22:07:55
Last  Post: 15-07-2012, 00:46:00

on: 12-07-2012, 17:40:47 :

will have a final bitsteam update next week(i hope). and completely change the architecture.
please wait for that before do any optimization effort.

Its only been 14 days since that announcement, I think we can hold off on the ropes and pitchforks for a bit <grins>

kind regards

[Raize]

No pitchforks here, I'm not upset! Just excited and interested in hearing how everything turned out. This has an application for present Icarus boards if I'm understanding what he's saying about the bitstream correctly.

[kano]

Update? ngzhang?

From his profile :

Last Active: 23-07-2012, 22:07:55
Last  Post: 15-07-2012, 00:46:00

on: 12-07-2012, 17:40:47 :

will have a final bitsteam update next week(i hope). and completely change the architecture.
please wait for that before do any optimization effort.

Its only been 14 days since that announcement, I think we can hold off on the ropes and pitchforks for a bit <grins>

kind regards

... and no one has given him any money yet either ...
So certainly no reason to be impatient ...

[ngzhang]

Update? ngzhang?

From his profile :

Last Active: 23-07-2012, 22:07:55
Last  Post: 15-07-2012, 00:46:00

on: 12-07-2012, 17:40:47 :

will have a final bitsteam update next week(i hope). and completely change the architecture.
please wait for that before do any optimization effort.

Its only been 14 days since that announcement, I think we can hold off on the ropes and pitchforks for a bit <grins>

kind regards

... and no one has given him any money yet either ...
So certainly no reason to be impatient ...

yeah, so i don't like  to withdraw any pre-order money to give me any more pressure when i focus on doing something.

these days:
still very busy at multiple works. 70% is school work, and i put all my spare time on lancelot project. to 3~4:00AM everyday.

i work together with the software guys, now the new bitsteam is doing the optimization work. we must push it to 500-550MH/s.

hardware is ready 5 days ago.

a reason of delay is one of the software guy go to USA, we only have another 1 people to do the work. (not including me) a good news is he will come back at 2/8, but we want to release the bitsteam earlier.

apologize for any misbehavior about didn't replay the PMs or mails.

PS:

accept bitsteam developer orders form now.

[Raize]

Don't worry, we're just interested in keeping updated. Thanks for letting us know what is going on. Hopefully when your guy gets back from the US you'll be set! I'm glad you're not taking preorders till you are ready.

[Dexter770221]

PS:

accept bitsteam developer orders form now.

So, I may order DEV KIT now? Do I need to email to you?

[mrb]

these days:
still very busy at multiple works. 70% is school work, and i put all my spare time on lancelot project. to 3~4:00AM everyday.

i work together with the software guys, now the new bitsteam is doing the optimization work. we must push it to 500-550MH/s.

hardware is ready 5 days ago.

At 250-275 Mh/s per FPGA, I presume you designed it using the "sea-of-tiny hashers" model, like bitfury did. If that's the case, good work! I wonder why not more people try to implement this obviously superior implementation (/me looks at the Cairnsmore1 devs...)

[2112]

I wonder why not more people try to implement this obviously superior implementation (/me looks at the Cairnsmore1 devs...)

It appears to trigger slow convergence in the place and route phases. The unrolled implementation has the similar problem, but less bad.

It seems like the heuristics in the global optimization phases can't find an usable gradient which could be used to guide the optimizer. So it kind of wanders in a fog over the terrain consisting of small hills and shallow valleys.

[ngzhang]

I wonder why not more people try to implement this obviously superior implementation (/me looks at the Cairnsmore1 devs...)

It appears to trigger slow convergence in the place and route phases. The unrolled implementation has the similar problem, but less bad.

It seems like the heuristics in the global optimization phases can't find an usable gradient which could be used to guide the optimizer. So it kind of wanders in a fog over the terrain consisting of small hills and shallow valleys.

yep, so we must use manually PAR. this really cost a LOT of man hour which is very very expensive.

PS:

i will check and answer personal messages after i finish the bitsteam work, unless you placed a developer order.

[ngzhang]

add order details and some new pictures.

for Chinese readers only:

目前只接受开发者订单，也就是说现在是没有bitsteam的。如果你没有bitsteam的开发能力，那么只能用icarus的bitsteam，或者用不起来。
每人最多一个。

[luffy]

this is great! any pictures from dev kit?

[disclaimer201]

If it can only mine btc, I don't see how it can still be profitable right now to be honest. Some of those Z-Tex boards have 128MB memory, so if I'd even switch to FPGA now, it would have to be at least LTC compatible. Look at some of the people with their Minirigs in the wild threads. Several guys already with 150+Gh/s Minirigs. Not even talking about Asics.

[wildemagic]

If it can only mine btc, I don't see how it can still be profitable right now to be honest. Some of those Z-Tex boards have 128MB memory, so if I'd even switch to FPGA now, it would have to be at least LTC compatible. Look at some of the people with their Minirigs in the wild threads. Several guys already with 150+Gh/s Minirigs. Not even talking about Asics.

@500mh/s you would make about $3 per day, using 25-30w of power costs about 10-15c per day.
How are you doing your calculations?

[luffy]

i think he is talking long term with asics on their way and dif goes sky high!
he could be right, fpgas should be able to be used for alt currencies also!

[disclaimer201]

If it can only mine btc, I don't see how it can still be profitable right now to be honest. Some of those Z-Tex boards have 128MB memory, so if I'd even switch to FPGA now, it would have to be at least LTC compatible. Look at some of the people with their Minirigs in the wild threads. Several guys already with 150+Gh/s Minirigs. Not even talking about Asics.

@500mh/s you would make about $3 per day, using 25-30w of power costs about 10-15c per day.
How are you doing your calculations?

I am making my calculations on the fact that BTC difficulty is skyrocketing for the past weeks already and continues to go up quickly. Furthermore, there are very few months left until the reward halves. So good luck paying off your FPGA at all, particularly when BFL delivers Asics at some point in the next 6 months which is rather likely. Next btc difficulty adjustment in a few days alone will decrease your 2.85$ income to . Even if difficulty stays at today's level, you will need 175 days to pay off one FPGA. And making an investment into FPGA right now isn't worthwhile if you can't make a profit with them in 2013. They will have zero resale value when difficulty doubles or quadruples. If I hadn't come across Litecoin, and if working Lancelots would have been actually available two months ago, I might have decided differently.

[Nemesis]

Definitely too late. PPL buy this for fun and experiment. But dont expect to have any bulk order.

[Energizer]

If it can only mine btc, I don't see how it can still be profitable right now to be honest. Some of those Z-Tex boards have 128MB memory, so if I'd even switch to FPGA now, it would have to be at least LTC compatible. Look at some of the people with their Minirigs in the wild threads. Several guys already with 150+Gh/s Minirigs. Not even talking about Asics.

@500mh/s you would make about $3 per day, using 25-30w of power costs about 10-15c per day.
How are you doing your calculations?

I am making my calculations on the fact that BTC difficulty is skyrocketing for the past weeks already and continues to go up quickly. Furthermore, there are very few months left until the reward halves. So good luck paying off your FPGA at all, particularly when BFL delivers Asics at some point in the next 6 months which is rather likely. Next btc difficulty adjustment in a few days alone will decrease your 2.85$ income to . Even if difficulty stays at today's level, you will need 175 days to pay off one FPGA. And making an investment into FPGA right now isn't worthwhile if you can't make a profit with them in 2013. They will have zero resale value when difficulty doubles or quadruples. If I hadn't come across Litecoin, and if working Lancelots would have been actually available two months ago, I might have decided differently.

You can check the countdown to 25 BTC per block reward here: http://serason.com/projects/emccharts/countdown.php

We are only 4 months away from 25 BTC block reward. Lancelot and Icarus wouldn't be of zero value in 2013, it will be evaluated as a dev-kit. So I suggest anyone buying lancelot to buy the complete div kit, to be able to sell it to developers "away from BTC mining market".

[luffy]

well don't be afraid of halving (25btc/block). the market has already started to pre-adjust btc's value and who knows the value at that day!
all systems go to equilibrium anyway

[loshia]

Gys's
What do you suggest? All of you know that starting something new is always risky and will always be.
Waiting for the asics? It is just a fiction...Watching bitcoin market and not investing anything? Just saying IF i bought i would...No sense. By GPU's? I do not have power plants and my electricity is not for free
It is just not serious. When reward becomes 25 BTC per block may be the price could be 20 USD per BTC:) OR it could be zero...So both of us will be F......d Gpu's FPGA Asics and every one else. What will be resel value of Fried GPU's when resell market is full of them if BTC collapses? So everyone should take its decision alone....I just do not see a point to spam the topic with BTC economics Asic stuff and all irreverent information. Let us concentrate on what we do have here. I see the situation in the flowing way:

1. Ngzhang and his team are good at what they do (both software and hardware) Let Icaurus owners confirm. Unfortunately i am not one of them
2. They are responsive and keep their promises
3. The prices are good compared to competitors
4. They are easy to communicate with

What else do we need?

Once again let us discuss here only lancelot related stuff please

No offense
I wish good luck to everybody and good profit also:)

[Energizer]

ngzhang've welcomed off topic subjects here long time ago! anyways, when will the new bitstream be available for Icarus? what are the procedures involved in the upgrade?

[2112]

I have non-mining questions:

1) You replaced Prolific PL2303HXD with FTDI FT232R, is that right?
2) Are all 8 DBUS pins from FT232R connected to the FPGA U1?
3) How about 5 CBUS pins? I see TXD1 and RXD1 LEDs so 2 are already used. Where are the remaining 3 connected? I'm hoping for RD# and WR# bit-bang strobes.
4) What is the number of connections between U1 and U2?
5) What is U3?
6) What is U9 and the HOT LED?
7) I see two Winbond chips U4 & U5. Are those SPI configuration memory?
Assume that FPGA is configured for loopback only and not for any work. Did you test that the FT232R works reliably at the full 3Mbps serial communication speed?

Thanks in advance.

[loshia]

ngzhang've welcomed off topic subjects here long time ago! anyways, when will the new bitstream be available for Icarus? what are the procedures involved in the upgrade?

Excise me...If off topic is welcomed please do take my apologies:)

[ngzhang]

I have non-mining questions:

1) You replaced Prolific PL2303HXD with FTDI FT232R, is that right?
2) Are all 8 DBUS pins from FT232R connected to the FPGA U1?
3) How about 5 CBUS pins? I see TXD1 and RXD1 LEDs so 2 are already used. Where are the remaining 3 connected? I'm hoping for RD# and WR# bit-bang strobes.
4) What is the number of connections between U1 and U2?
5) What is U3?
6) What is U9 and the HOT LED?
7) I see two Winbond chips U4 & U5. Are those SPI configuration memory?
Assume that FPGA is configured for loopback only and not for any work. Did you test that the FT232R works reliably at the full 3Mbps serial communication speed?

Thanks in advance.

short answer:
1, yes!
2, TXD,RXD,CTS,RTS
3,
4, clock buffer
6, TMP102 temperature sensor
7, yes
8, no.

 
sch and PCB design files will release to github this week.

[2112]

2, TXD,RXD,CTS,RTS
3, ? ? ?

sch and PCB design files will release to github this week.

"Oh boy!" for not connecting all available pins from the FT232R to the FPGA.

Any non-mining application would need more communication bandwidth. The easies way would be to route all 8 DBUS signals for parallel byte communication. Then the CBUS signals can be configured in EEPROM to expose the RD# & WR# strobe signals. It all works together to allow easy implementation of bit-bang I/O. And it is easy both on the host side software in the computer and easy on SLICE resources on the FPGA.

It is just 6 traces more, but the value of the board as a development kit increases immensely. The default 115200bps maximum speed in UART is a serious limitation for non-mining uses.

I'll wait for the schematic and constraint files to ask further questions.

I have some other development board with FTDI chip and I will write a quick loopback test software for Windows and a trivial loopback Xilinx project.

[ngzhang]

2, TXD,RXD,CTS,RTS
3, ? ? ?

sch and PCB design files will release to github this week.

"Oh boy!" for not connecting all available pins from the FT232R to the FPGA.

Any non-mining application would need more communication bandwidth. The easies way would be to route all 8 DBUS signals for parallel byte communication. Then the CBUS signals can be configured in EEPROM to expose the RD# & WR# strobe signals. It all works together to allow easy implementation of bit-bang I/O. And it is easy both on the host side software in the computer and easy on SLICE resources on the FPGA.

It is just 6 traces more, but the value of the board as a development kit increases immensely. The default 115200bps maximum speed in UART is a serious limitation for non-mining uses.

I'll wait for the schematic and constraint files to ask further questions.

I have some other development board with FTDI chip and I will write a quick loopback test software for Windows and a trivial loopback Xilinx project.

maybe after this project, when i have some free time. i will build a small FPGA(LX16 FT256) dev board with DDR2 RAM and FT232 connect as you describe and sell it at a ultra low price(50$) for learning.

[2112]

maybe after this project, when i have some free time. i will build a small FPGA(LX16 FT256) dev board with DDR2 RAM and FT232 connect as you describe and sell it at a ultra low price(50$) for learning.

As a dev board user I can tell you the following: market is full of single FPGA dev boards. The uniqueness and greatness of your designs (Icarus & Lancelot) lies in them being paired FPGAs with non-trivial interconnectivity. The only problem with them is that they have a bent straw instead of a pipe for the external communication.

I'm even thinking of getting a Lancelot and paying someone to rework the FT232R connections using additional 10 wires soldered to the unpopulated GPIO vias. But this is something above my manual skill and resources, and because of that it will have to wait.

If you ever find a need to do Lancelot v2 (like Icarus v2) then just please remember to route all the available signals from the comm chip to the FPGA.

And for your future designs please consider using the high-speed USB chips instead of full-speed USB and having one comm pipe per FPGA. So the Lancelot v5 would have FT2232H (dual high-speed USB). The market for the multi-FPGA boards its there already:

https://bitcointalk.org/index.php?topic=78239.msg973019#msg973019

I just realised that I have given such a pitch already years ago. I was an early advocate of dual Pentium (Classic) and dual Celeron (with SMP mod) motherboards. Those who listened were very well prepared for the arrival of multicore CPUs. Something similar will happen with FPGAs.

[Luke-Jr]

And please please set the iVendor/iProduct USB descriptors so miners can autodetect it sanely!

[2112]

And please please set the iVendor/iProduct USB descriptors so miners can autodetect it sanely!

I would recommend against that, unless some driver fairy can obtain a WHQL signature for the modified VID/PID. Trying to run with unsigned drivers under 64-bit Windows is an unnecessary hassle.

The market gained would be some open-source extremists. The market lost would be those who can't or wouldn't modify their Windows installations. Let the US-ians fight the monster from Redmond.

[Luke-Jr]

And please please set the iVendor/iProduct USB descriptors so miners can autodetect it sanely!

I would recommend against that, unless some driver fairy can obtain a WHQL signature for the modified VID/PID. Trying to run with unsigned drivers under 64-bit Windows is an unnecessary hassle.

The market gained would be some open-source extremists. The market lost would be those who can't or wouldn't modify their Windows installations. Let the US-ians fight the monster from Redmond.

He doesn't have to change VID/PID to set iVendor/iProduct.

[2112]

He doesn't have to change VID/PID to set iVendor/iProduct.

I don't think you are making yourself clear. Please post the link to the FTDI application notes that describe the change you are requesting.

http://www.ftdichip.com/Support/Documents/AppNotes/AN_121_FTDI_Device_EEPROM_User_Area_Usage.pdf

Are you talking about this?

[Luke-Jr]

He doesn't have to change VID/PID to set iVendor/iProduct.

I don't think you are making yourself clear. Please post the link to the FTDI application notes that describe the change you are requesting.

http://www.ftdichip.com/Support/Documents/AppNotes/AN_121_FTDI_Device_EEPROM_User_Area_Usage.pdf

Are you talking about this?

Sorry, it's iManufacturer not iVendor. Here is a generic USB info on these strings: http://www.beyondlogic.org/usbnutshell/usb5.shtml#DeviceDescriptors

If your FTDI PDF, it's mentioned on page 4 (section 1.1) as "Manufacturer" and "Description" strings.

[loshia]

Guy's
I have just received my Lancelots! They are just a piece of art. I can assure you that ngzhang just rocks:) Everything was done as promised in time. On top of all I have some extra stuff for free.

Thank you very much ngzhang!
I do not have any hesitation that bitstream will be here soon as promised.
ngzhang is an extremely cool guy, who keeps his word.
ngzhang I am still waiting for your BTC address:)

Best

[Luke-Jr]

In case anyone would like to donate a Lancelot for improved BFGMiner support, please PM me.

[Raize]

Guy's
I have just received my Lancelots! They are just a piece of art. I can assure you that ngzhang just rocks:) Everything was done as promised in time. On top of all I have some extra stuff for free.

Thank you very much ngzhang!
I do not have any hesitation that bitstream will be here soon as promised.
ngzhang is an extremely cool guy, who keeps his word.
ngzhang I am still waiting for your BTC address:)

Best

You got them before you paid for them?

[loshia]

No:)
I wished but....as you know there is no free lunch:)

Here are some results:

Just brilliant:)


P]ool management ettings [D]isplay options [Q]uit

 ICA 0:                | 379.9/376.6Mh/s | A:65 R:0 HW:0 U: 4.89/m

 ICA 1:                | 379.7/376.9Mh/s | A:68 R:0 HW:0 U: 5.11/m

 ICA 2:                | 379.8/375.7Mh/s | A:78 R:0 HW:0 U: 5.86/m

 ICA 3:                | 379.4/378.0Mh/s | A:65 R:0 HW:0 U: 4.89/m

[irritant]

still only available for developers?  I'm still learning, maybe developing some day, but not anytime soon

[pazor]

subscribed

[Icoin]

Does someone has a howto to make the Lancelot run on Ubuntu 12.04 x64?

[loshia]

Does someone has a howto to make the Lancelot run on Ubuntu 12.04 x64?

http://en.qi-hardware.com/wiki/Icarus

Just follow it step by step:) All info applies to Lancelot

[Icoin]

Just follow it step by step:) All info applies to Lancelot

thanks for the hint, after compilation of the cgminer i end up with the msg all devices disabled, cannot mine! and when i power on a board i cant see any ttyUSB0 in /dev

In mpblm the boards are recognized it shows me x6500 style serials for each board, but the icarus setup dont work

[loshia]

it works both Icarus and Lancelot believe me. I know from my personal experience.

[Icoin]

ttyUSB0 is not present in /dev on ubuntu 12.04, so it does not work !! If anyone has a workaround for this, since the boards seems to be recognized (when i turn of one lancelot 3 more files appears in /dev but i cant figure which ones that are) and mpblm does see them as x6500 boards there has to be a solution.

it works both Icarus and Lancelot believe me. I know from my personal experience.

I can imagine you made a good expirience, but im quite sure your not using ubuntu 12.04 x64

I tried to compile  ftdi_sio (even when they say there that since ubuntu 11.10 it is included in the kernel) but this ends up in telling me that modversions.h cant be found

[loshia]

Dude,
First use apt-get install. When i was young i was trying to compile everything by myself. I realasied that i can not maintain whole linux distro
I am joking.

Did you read cgminer/Readme
did you apt-get install
libudev headers
        (This is only required for FPGA auto-detection and is linux only)

        libusb headers
        (This is only required for ZTEX support)


Just goolgle about apt-get install ftdi_sio i guess you miss libusb-dev (if there is such thing) or something else which for sure can be installed with apt-get

Good luck
It shall be somewhere inside:)

For your reference my distro is same is yours

uname -a
Linux xxxxxx-GA-990FXA-UD7 3.2.0-29-generic #46-Ubuntu SMP Fri Jul 27 17:03:23 UTC 2012 x86_64 x86_64 x86_64 GNU/Linux

From my system
 dpkg-query -l | grep usb
ii  libusb-0.1-4                           2:0.1.12-20                             userspace USB programming library
ii  libusb-1.0-0                           2:1.0.9~rc3-2ubuntu1                    userspace USB programming library
ii  libusbmuxd1                            1.0.7-2                                 USB multiplexor daemon for iPhone and iPod Touch devices - library
ii  usb-creator-common                     0.2.38                                  create a startup disk using a CD or disc image (common files)
ii  usb-creator-gtk                        0.2.38                                  create a startup disk using a CD or disc image (for GNOME)
ii  usb-modeswitch                         1.2.3+repack0-1ubuntu2                  mode switching tool for controlling "flip flop" USB devices
ii  usb-modeswitch-data                    20120120-0ubuntu1    
        mode switching data for usb-modeswitch
ii  usbmuxd                                1.0.7-2                                 USB multiplexor daemon for iPhone and iPod Touch devices
ii  usbutils                               1:005-1
ii  xserver-xorg-video-sisusb              1:0.9.4-2build2                         X.Org X server -- SiS USB display drive

 dpkg-query -l | grep udev
ii  gir1.2-gudev-1.0                       175-0ubuntu9.1                          libgudev-1.0 introspection data
ii  libgudev-1.0-0                         1:175-0ubuntu9.1                        GObject-based wrapper library for libudev
ii  libudev-dev                            175-0ubuntu9.1                          udev library (development files)
ii  libudev0                               175-0ubuntu9.1                          udev library
ii  system-config-printer-udev             1.3.8+20120201-0ubuntu8.1               Printer auto-configuration facility based on udev
ii  udev                                   175-0ubuntu9.1      

[Icoin]

...For your reference my distro is same is yours

uname -a
Linux xxxxxx-GA-990FXA-UD7 3.2.0-29-generic #46-Ubuntu SMP Fri Jul 27 17:03:23 UTC 2012 x86_64 x86_64 x86_64 GNU/Linux

From my system

i see, but have a look here:

http://pastebin.com/LWyV74T0

there you can allso see from lsusb that:
devices 5 and 6 are x6500
devices 36, 37, 25, 26 are Lancelot

Maybe you see something i dont.

I googeled for apt-get install ftdi_sio by now i have not found anything usable. But thanks for the help

[kano]

ftdi_sio should already be there in the kernel ...

From looking at your pastebin (which gives exactly what I was hoping from dmesg when I spoke to you in IRC ... ) Try:

sudo modprobe ftdi_sio vendor=0x0403 product=0x6001

See if that works.

[flynn]

I just ordered my dev kit
I can't wait to play with it

[Icoin]

sudo modprobe ftdi_sio vendor=0x0403 product=0x6001

gets me:
FATAL: Module ftdi_so not found.

[kano]

sudo modprobe ftdi_sio vendor=0x0403 product=0x6001

gets me:
FATAL: Module ftdi_so not found.

Coz there's supposed to be an i in there?

If not then you have screwed up your 12.04 somehow.
Wipe it and start again.

It is part of the standard kernel

[Icoin]

Coz there's supposed to be an i in there?

You are right the i helped

Thank you kano + Ioshida

1LdwedmvYjyPT7qmRFpRThtd4bEKUdMexD @ http://glari.ch:9332/static/graphs.html

[ngzhang]

Coz there's supposed to be an i in there?

You are right the i helped

Thank you kano + Ioshida

1LdwedmvYjyPT7qmRFpRThtd4bEKUdMexD @ http://glari.ch:9332/static/graphs.html

 Problems solved? 

[kano]

Coz there's supposed to be an i in there?

You are right the i helped

Thank you kano + Ioshida

1LdwedmvYjyPT7qmRFpRThtd4bEKUdMexD @ http://glari.ch:9332/static/graphs.html

 Problems solved? 

Yes

[luffy]

I also got my DEV kit today. Thank you very much, you are a professional!

[ngzhang]

I also got my DEV kit today. Thank you very much, you are a professional!

  looks like EMS is much faster these days.

[luffy]

any news about the bitstream and if you can sell Lancelots with Icarus bitstream?
i think this way the price can be reduced a bit

[kano]

I also got my DEV kit today. Thank you very much, you are a professional!

  looks like EMS is much faster these days.

Got my 'DevOnlyKit' 2 days ago (just the USB kit) - 6 days - still very good

[ngzhang]

any news about the bitstream and if you can sell Lancelots with Icarus bitstream?
i think this way the price can be reduced a bit

about the price, there are 2 method to reduce it:

1, can be significantly reduce when the sales volume increase to 250. at that point i will change to -2C speed grade, and the price will reduce about 10%. but seemingly, the hashing speed will not reduce a lot(nearly the same).
2, buy more. a 30pcs bulk order can enjoy a 400$/ea price.

[eckmar]

about the price, there are 2 method to reduce it:

1, can be significantly reduce when the sales volume increase to 250. at that point i will change to -2C speed grade, and the price will reduce about 10%. but seemingly, the hashing speed will not reduce a lot(nearly the same).
2, buy more. a 30pcs bulk order can enjoy a 400$/ea price.

WHEN do you accept bulk orders for Lancelot?

I fear if the ASICs really will be available in October this year, your announced motherboard for Lancelot may never be produced.

With my 36 Icarus boards running here in my pool, it is a burden to find one which is not running. (Which happens here once a day.)
So I would really appreciate a cluster with a software which is telling me which board is not working...

Any news about the new bit-stream for Icarus?

Sunny regards from the holiday island Koh Samui (Thailand),
 Ecki

[fpf]

Eckmar,

The Lancelot uses the FTDI chip - which does have a serial number for each chip, you can program it by ftprog. That way your host can remember the port assigned to it.

For finding non working Icarus units.. how about checking the idle LED?

Phil

[eckmar]

Hi Phil,

..
For finding non working Icarus units.. how about checking the idle LED?
...

Yes, this is the way I am doing it right now.
Repluging the USB cable will solve the problem normally.
But if you need to do this once a day, it is getting boring, because it is not always the same board.
So you have to check really all Icarus boards every time...

Thanks for the hint with the new Lancelot boards. Sounds promising...

Cu,
 Ecki

[Dexter770221]

Mine arrived today. Hurray!
After 5 days, not too bad. Piece of solid hardware. I'm trying now to force it to work but without any luck. cgminer, bfgminer don't recognize anything. I can see in device manager (Windows) additional COM3 port. I've set it up for 115200 baudrate, in .bat file added -S auto --icarus-options 115200:2:2. I'm more and more stupid

[flynn]

The Dame of the Lake knocked at the door today and gave me that Lancelot board dev kit !

It's amazing. It took me a few minutes to make it working under Linux (debian 6):

- recompile cgminer with --enable-icarus
- search /dev for clues => /dev/ttyUSB0
- cgminer -O zzz:xxx -D -S /dev/ttyUSB0 -o xxxpool.com:8332

--------------------------------------------------------------------------------
 Pool management GPU management Settings Display options Quit
 GPU 0:  75.5C 2182RPM | 325.3/322.9Mh/s | A:232 R:0 HW:0 U:  4.68/m I: 4
 ICA 0:                | 379.4/376.7Mh/s | A:277 R:1 HW:0 U:  5.59/m
--------------------------------------------------------------------------------

Fantastic work, the board is wonderfully built, thank you Ngzhang !

[Dexter770221]

Well, I don't want Linux. Not on minning rig, its been used for other purposes that requires Windows. So, "no go" with Windows?

[Beaflag VonRathburg]

Mine arrived today. Hurray!
After 5 days, not too bad. Piece of solid hardware. I'm trying now to force it to work but without any luck. cgminer, bfgminer don't recognize anything. I can see in device manager (Windows) additional COM3 port. I've set it up for 115200 baudrate, in .bat file added -S auto --icarus-options 115200:2:2. I'm more and more stupid

I could be wrong, but... Last time I checked scan serial wasn't working. Try calling com 3 as you see it in device manager and it should work.

[Luke-Jr]

Might try (with 2.7.5):

Code:

bfgminer -S all

This will scan every serial port it can. Beware if you have non-mining devices on your PC, though!

Unfortunately, ngzhang didn't want to donate a Lancelot so I can provide proper support (he did donate an Icarus - I guess he assumed Lancelot would just work in the same way), so there may not be much I can do if it doesn't work unless someone else wants to donate one.

[rgzen]

My Lancelot board arrived on Monday. I have to say that it works fine.

@Dexter770221:
It is supposed that works on windows... I don´t have probe it but in fact ngzhang has write instructions to do it work on windows.
Because I had some problems recognizing the hardware and at the end the reason was the USB cable (A-type male to miniUSB male) I suggest you to change the cable and continue trying  .

[kano]

Mine arrived today. Hurray!
After 5 days, not too bad. Piece of solid hardware. I'm trying now to force it to work but without any luck. cgminer, bfgminer don't recognize anything. I can see in device manager (Windows) additional COM3 port. I've set it up for 115200 baudrate, in .bat file added -S auto --icarus-options 115200:2:2. I'm more and more stupid

It will of course (as you said) show up in the device manager unless there is a driver problem.
Since it was COM3, the extra option would be
-S COM3

The --icarus-options 115200:2:2 you specified is the default I set in the code anyway, so you don't need to do that one.

If there is more than one of them it is -S COMn -S COMn and for any of them if n > 9 it's -S \\.\COMn

[Dexter770221]

Thanks for the tips. It's working now. Cgminer downloded from ckovilas git will not hash with Icarus (Lancelot). Only version from Kano github does that.

EDIT: bfgminer also works! It needed only change from -S auto to -S COM3.

[kano]

Thanks for the tips. It's working now. Cgminer downloded from ckovilas git will not hash with Icarus (Lancelot). Only version from Kano github does that.

EDIT: bfgminer also works! It needed only change from -S auto to -S COM3.

With cgminer that just depends on what you are running.

With the latest 2.7.5 that was just released:

When running windows:
If you only have FPGA and no GPUs, ckolivas has now added an extra FPGA only version in the windows binary download
(I made an ICA/BFL only windows version up until 2.7.4a but I don't need to do that now coz it's in ckolivas official version)
In ckolivas Windows 7zip file it now contains: cgminer.exe and cgminer-fpgaonly.exe
So I won't need to put a 2.7.5a.exe in my downloads

For others running linux:
It depends on your linux version.
ckolivas builds his on the equivalent of ubuntu 12.04 so it wont work if you have an older 11.04 or 11.10 linux
That's why I have an 'a' version in my git downloads that I compile on 11.04 (it also works on Fedora 16 and 17)
I haven't made 2.7.5a yet - I'll do that shortly.

[Icoin]

The DVB fundet Qcool Element (Water cooling adapter for Lancelot) goes prototype phase.
http://www.glari.ch:3000/projects/qcool
https://cryptostocks.com/securities/14

[loshia]

Guy's
While waiting for ngzang Lancelot bitstream i wana play with one of my boards  and try different bitstreams. I just wana be prepared for the moment when ngzang will release the official bitstream. However i have never done that before. I have a couple of questions and i would be thankful to anyone who can give me some info:

1. I have Lancelot dev kit available.
2. Are the instructions published for Icarus http://en.qi-hardware.com/wiki/Icarus#Flash_by_using_iMPACT,  http://dl.dropbox.com/u/28686048/Icarus/prgm-fpga.png, https://github.com/ngzhang/Icarus/blob/master/Downloads/bitsteam/guide%20for%20flash%20update.txt good to be used with Lancelot?
2. Have someone tried https://github.com/ngzhang/Icarus/tree/master/Downloads/bitsteam/200MHz_for_test or https://github.com/ngzhang/Icarus/tree/master/Downloads/bitsteam/V4 with lancelot?
3. What other "unofficial" bitsreams are available for Lancelot
4. How can i flash "temporally" bitstreams - i mean mcs files. As far i understood flashing mcs do not last power off/on? Probably this is the bet way for me to try.
5. I am using cgminer 2.7.5

Thank you very much in advance

[kano]

N.B. if you put a faster bitstream than 380MH/s in Icarus or Lancelot, you MUST at least use --icarus-timing short
Otherwise cgminer will slow down the device.

The default settings are to delay for 11.2 seconds before aborting work, and if the bitstream is only 1.5% faster than the 380Mh/s bitstream then the delay of 11.2 seconds will mean it will be idle for a short amount of time at the end of the nonce range each time it doesn't find a share in a full nonce range

The --icarus-timing options allow you to tell cgminer to work out the correct timing (using short or long) or specify the correct timing once you know it
See the API-README for details.

[loshia]

N.B. if you put a faster bitstream than 380MH/s in Icarus or Lancelot, you MUST at least use --icarus-timing short
Otherwise cgminer will slow down the device.

The default settings are to delay for 11.2 seconds before aborting work, and if the bitstream is only 1.5% faster than the 380Mh/s bitstream then the delay of 11.2 seconds will mean it will be idle for a short amount of time at the end of the nonce range each time it doesn't find a share in a full nonce range

The --icarus-timing options allow you to tell cgminer to work out the correct timing (using short or long) or specify the correct timing once you know it
See the API-README for details.

I know:)
I have read that already --icarus-timing. Th question was if someone have done it already. I just do not want to "kill" my board if i make something wrong while flashing it:)

[loshia]

Guys,
I am tiring to map my lancelets to particular names in order to be able to know which cgminer ICAxx corresponds to which board. I am using xubuntu 12.04.
I have tried following (udev rules):
ATTR{idVendor}=="0403",ATTR{idProduct}=="6001",ATTR{serial}=="A101LSVA",SYMLINK="ttyLancelot2"

When I tested it the serial A101LSVA corresponded to /dev/ttyUSB2 with board attached and working

However /dev/ttyLancelot2 always was symlinked  to /dev/bus/usb/003/026 or something and cgminer refused to work. When I manually symlinked /dev/ttyLancelot2 to /dev/ttyUSB2 all was fine. How to make udev to symlink to /dev/ttyUSBxx instead of /dev/bus/usb/xxx/xxx
10X

[spiccioli]

Guys,
I am tiring to map my lancelets to particular names in order to be able to know which cgminer ICAxx corresponds to which board. I am using xubuntu 12.04.
I have tried following (udev rules):
ATTR{idVendor}=="0403",ATTR{idProduct}=="6001",ATTR{serial}=="A101LSVA",SYMLINK="ttyLancelot2"

When I tested it the serial A101LSVA corresponded to /dev/ttyUSB2 with board attached and working

However /dev/ttyLancelot2 always was symlinked  to /dev/bus/usb/003/026 or something and cgminer refused to work. When I manually symlinked /dev/ttyLancelot2 to /dev/ttyUSB2 all was fine. How to make udev to symlink to /dev/ttyUSBxx instead of /dev/bus/usb/xxx/xxx
10X

loscia,

I did it like this for my CM1 boards:

https://bitcointalk.org/index.php?topic=78239.msg1091298;topicseen#msg1091298

spiccioli.

[loshia]

10X
That is what i was looking for:)
I will try it later and let you know the result!
Thank you
PS:

What do you think of HW err patch listed here?
https://bitcointalk.org/index.php?topic=78239.1760
Assuming i am having only ICA boards attached it can not brake anything right? And will count HW errors. Actually i applied it already and seems good.

[kano]

10X
That is what i was looking for:)
I will try it later and let you know the result!
Thank you
PS:

What do you think of HW err patch listed here?
https://bitcointalk.org/index.php?topic=78239.1760
Assuming i am having only ICA boards attached it can not brake anything right? And will count HW errors. Actually i applied it already and seems good.

... https://bitcointalk.org/index.php?topic=28402.msg1158924#msg1158924

[loshia]

spiccioli,
udev works charming:) you made my day thank you

kano,

I just cloned
https://github.com/kanoi/cgminer/

It turns out that if (hash2_32[7] != 0) means hw_error not like the patch i found:)
Share below target is not always hw_err right? Anyway thank you for your work. I am running your code right now and i will let you know how it goes. Bad thing is that i have HW errors counters>0 I am joking..I guess i have to live with them like everybody else here.
Everyone was talking abut HW error rate - % - Now i can calculate and graph it:)

Best

[spiccioli]

spiccioli,
udev works charming:) you made my day thank you

loshia,

you're welcome.

spiccioli

[kano]

spiccioli,
udev works charming:) you made my day thank you

kano,

I just cloned
https://github.com/kanoi/cgminer/

It turns out that if (hash2_32[7] != 0) means hw_error not like the patch i found:)
Share below target is not always hw_err right? Anyway thank you for your work. I am running your code right now and i will let you know how it goes. Bad thing is that i have HW errors counters>0 I am joking..I guess i have to live with them like everybody else here.
Everyone was talking abut HW error rate - % - Now i can calculate and graph it:)

Best

Yeah the catch now is that there are 2 tests required.

The first test is the simple one - all nonces returned by mining devices are 1 diff - so they MUST be "hash2_32[7] == 0"
If not - then yep that's a hardware error.
If it is '0' then it is not a hardware error.

The 2nd test is the difficulty level.
Now that pools are giving out >1 diff work, that 2nd test comes in to play - if that second test fails, it is simply just a normal share but not high enough difficulty - so no error.
e.g. with a 10 diff pool, 90% of the shares found by any mining device will be the wrong difficulty and thus ignored (but not an error)

Meanwhile My 2 Icarus after a bit over 2 days:

Code:

 cgminer version 2.7.5c - Started: [2012-09-05 13:15:08]
--------------------------------------------------------------------------------
 (5s):1395.4 (avg):1491.6 Mh/s | Q:3487  A:61173  R:406  HW:30  E:1754%  U:20.7/m
 TQ: 0  ST: 7  SS: 16  DW: 388  NB: 360  LW: 161062  GF: 18  RF: 9  WU: 20.9
 Connected to Nowhere with LP as user Miku
 Block: 0000015d263f4a611b3d1b72a98f5dfe...  Started: [14:22:16]
--------------------------------------------------------------------------------
 [P]ool management [G]PU management [S]ettings [D]isplay options [Q]uit
 GPU 0:  73.0C 3501RPM | 366.1/366.7Mh/s | A:14975 R: 97 HW: 0 U: 5.08/m I: 9
 GPU 1:  71.0C 2084RPM | 365.9/365.8Mh/s | A:14958 R: 92 HW: 0 U: 5.07/m I: 9
 ICA 0:                | 379.6/379.5Mh/s | A:15589 R:110 HW:18 U: 5.29/m
 ICA 1:                | 379.6/379.6Mh/s | A:15651 R:107 HW:12 U: 5.31/m

So I'm getting a bit under 0.1%

[loshia]

Kano,
I have noticed a couple things:
1. You are running both GPU and FPGA on your cgminer. Is it a good idea to have them both on single miner? Are there some potential problems because of that? Currently i am having two cgminers running - one with GPU disabled and icaurs enabled and second cgminer with GPU enabled and icaurs disabled
2. Your cgminer version is 2.7.5c is it just a string bumped up right? what i am asking is if https://github.com/kanoi/cgminer/ contains your latest code?
3. Your HW errors are a lot less than mines:) However i am not done with hardware setup yet - i have to polish it, Voltage drop of the second crappy PSU is big about 1.3 volts. I suspect some of the usb cables that came along with the usb hubs i bought. They just look like a pice of garbige compared to ngzang USB cables that came along with lancelots.  In general  my HW errors for all Lancelots are < 0.3%, but i have some boards with almost 3%. It is just one night run of course.

10X

[kano]

Cgminer is threaded - so it is actually better to run 1 cgminer than 2.

The threading basically means it's no real difference, however if your pool supports roll-n-time, it's better to have one cgminer talking to the pool than having 2 of them (see my E: 1754% value) - the rolling covers all 4 devices easily enough - whereas with 2 cgminers you will be getting twice as much work from the pool.

I do however, also run 2 cgminers - the 2nd one just has 1 BFL.
Since BFL's suck when it comes to dealing with LP's, I prefer to point that at a pool I know will get minimal Rejects

Yes 2.7.5c is my current git (I haven't added anything in the past 2 days) but I skipped 'b'
I always add letters on the end for my versions so I know where they came from (in this case it is 2.7.5 + my changes = my git master)
When I add more code before 2.7.6 comes out, it will become 2.7.5d or 2.7.5e or something like that
(I now only use 'a' for the Ubuntu 11.04 executable of each official release, that I make)

[loshia]

Thanks kano!
Just a side question. I am using bitminter for the moment. as far as i know roll-n-time will come shortly but there is no support for cgminer yet. Pool works great. Can you tell me which pool do you use with roll-n-time enabled for cgminer please? I hope it is not top secret of course:)

[kano]

Thanks kano!
Just a side question. I am using bitminter for the moment. as far as i know roll-n-time will come shortly but there is no support for cgminer yet. Pool works great. Can you tell me which pool do you use with roll-n-time enabled for cgminer please? I hope it is not top secret of course:)

At the moment, OzCoin and EMC

Oh  ... and in case you didn't realise ... the cgminer API command 'stats' will also tell you for each pool you have in your list that has done at least one getwork

[flynn]

Guy's
While waiting for ngzang Lancelot bitstream i wana play with one of my boards  and try different bitstreams. I just wana be prepared for the moment when ngzang will release the official bitstream. However i have never done that before. I have a couple of questions and i would be thankful to anyone who can give me some info:

1. I have Lancelot dev kit available.
2. Are the instructions published for Icarus http://en.qi-hardware.com/wiki/Icarus#Flash_by_using_iMPACT,  http://dl.dropbox.com/u/28686048/Icarus/prgm-fpga.png, https://github.com/ngzhang/Icarus/blob/master/Downloads/bitsteam/guide%20for%20flash%20update.txt good to be used with Lancelot?
2. Have someone tried https://github.com/ngzhang/Icarus/tree/master/Downloads/bitsteam/200MHz_for_test or https://github.com/ngzhang/Icarus/tree/master/Downloads/bitsteam/V4 with lancelot?
3. What other "unofficial" bitsreams are available for Lancelot
4. How can i flash "temporally" bitstreams - i mean mcs files. As far i understood flashing mcs do not last power off/on? Probably this is the bet way for me to try.
5. I am using cgminer 2.7.5

Thank you very much in advance

I am following the same path very slowly.

I have ngzhang's dev kit JTAG cable working - just follow the Xilinx instructions and under Linux you probably need this : http://rmdir.de/~michael/xilinx/

Connect the small board with a big white arrow on the xilinx JTAG cable, then connect the cable with the 7 colored wires to it.

Connect the loose wires to the Lancelot board in this order : from left: VCC/GND/TCK/TDO/TDI/TMS
that is, RED/BLACK/YELLOW/WHITE/PURPLE/GREEN   ignore the GREY wire (INIT)

Start IMPACT => you can see the two LX150;
I didn't dare downloading anything yet tho, I also wonder what is the exact bitstream currently running, my guess is https://github.com/ngzhang/Icarus/tree/master/Downloads/bitsteam/V3

[loshia]

flynn,
Thanks for the update. The wise thing we can do is to wait for ngzang instructions - personal opinion. I think if we do something wrong we can "kill" the boards . More over there are some switches on the pcb prog1 and prog2. I personally do not have enough knowledge to look at the pcb files and find out what they are used for.
If someone else has the guts to try it and share the info with us will be great;)

[ngzhang]

come to say i'm still alive.

and this is 40 64cycle cores @ ~4ns...



 

i must say the development process is a disaster, i never want to do it again.

[loshia]

I mast say that i am not an expert but it seems that there is a lot of room available to fill Apart of the joke i have red somewhere that some of the guys do use "self made" tools to be able to achieve big density. The info was here if i remember correctly but link is dead
http://www.bitfury.org/xc6slx150.html

[ngzhang]

I mast say that i am not an expert but it seems that there is a lot of room available to fill Apart of the joke i have red somewhere that some of the guys do use "self made" tools to be able to achieve big density. The info was here if i remember correctly but link is dead
http://www.bitfury.org/xc6slx150.html

yeah we also write a lot of private tools, in order to help us fight with stupid XILINX tool chain.

[loshia]

I am sure that you  will do it! At the end whatever it costs it will worth it. Believe me. The feeling after job well done can not be replaced with anything else expect with well-well done
Just a side question - do you plan core (or cg miner) to be able auto adjust the clock watching the error rate? Will be some temps reading be available? and PWM fan control and speed monitoring.
I know that it is too much for a start (first version) but i am asking in general for future bitstream upgrades
10X

[flynn]

i must say the development process is a disaster, i never want to do it again.

Rofl - feeling your pain.

How do you build these nice graphs ?

[mrb]

I mast say that i am not an expert but it seems that there is a lot of room available to fill Apart of the joke i have red somewhere that some of the guys do use "self made" tools to be able to achieve big density. The info was here if i remember correctly but link is dead
http://www.bitfury.org/xc6slx150.html

yeah we also write a lot of private tools, in order to help us fight with stupid XILINX tool chain.

Sometimes I feel the FPGA development world could benefit massively from clean-slate-designed open source tools to do the logic synthesis, mapping, placement, routing, etc.

Right now, there is not much competition between Xilinx and Altera to improve their software tools, because the competition is mostly centered around the hardware capabilities of their chips, not the quality of the software stack.

[flynn]

and this is 40 64cycle cores @ ~4ns...

Wait.

40x64 cycles cores @ 250Mhz = 20xfull hashers @250Mhz = 5GH/s per chip

Who needs ASICs, really ...

[ngzhang]

and this is 40 64cycle cores @ ~4ns...

Wait.

40x64 cycles cores @ 250Mhz = 20xfull hashers @250Mhz = 5GH/s per chip

Who needs ASICs, really ...

finally will be 80cores there, maybe 70+ at first.

speed = core amount / 64 * freq

but i think we will face same power issues when impact the high frequency. but i think 250MHs pre chip at first and 350MHs after carefully optimization is a optimistic estimate.

on XILINX -7 series, it will get a 30% better core density (means: use 30% less luts for a single core), and at least 50% frequency improve. means ~ 800-1G hash pre XC7A200T chip. this performance is close to a normal 0.11~0.13 um ASIC. the cost consist in sales volume.

I mast say that i am not an expert but it seems that there is a lot of room available to fill Apart of the joke i have red somewhere that some of the guys do use "self made" tools to be able to achieve big density. The info was here if i remember correctly but link is dead
http://www.bitfury.org/xc6slx150.html

yeah we also write a lot of private tools, in order to help us fight with stupid XILINX tool chain.

Sometimes I feel the FPGA development world could benefit massively from clean-slate-designed open source tools to do the logic synthesis, mapping, placement, routing, etc.

Right now, there is not much competition between Xilinx and Altera to improve their software tools, because the competition is mostly centered around the hardware capabilities of their chips, not the quality of the software stack.

if you are a " VOL customer", XILINX will open more bottom layer information and give you more support. then you could implement wanted substructures.

[Dexter770221]

Wow, great job. Looks really dense 64 cycle 2 stage core?

[ngzhang]

Wow, great job. Looks really dense 64 cycle 2 stage core?

yeah， every 64cycle pre bitcoin hash.
 
present we must place the other half chip... the same work as the first half, but the stupid tool is getting stuck. nobody could imagine the difficulty unless they made similar work before.

[loshia]

Ngzang,

Is there any thing we can do to help you out? I mean to provide you some CPU power or other resource that you are missing?

Best

[flynn]

Ngzhang,

And about the power dissipation problems, did you consider inserting a Peltier module between the chips and the heatsink ?

[ngzhang]

Ngzang,

Is there any thing we can do to help you out? I mean to provide you some CPU power or other resource that you are missing?

Best

CPU power is not a big problem there.

Ngzhang,

And about the power dissipation problems, did you consider inserting a Peltier module between the chips and the heatsink ?

a semiconductor cooling chip will significantly improve the speed （if we finally implement the auto speed adjust feature), but will cause a huge energy consumption.

[ngzhang]

Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.

[flynn]

Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.

Thank you ngzhang. That means your developing fpga nightmare is over, right?

[nedbert9]

Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.

I like ngzhang's style.

[Cablez]

Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.

I like ngzhang's style.

Quoted just because of so much win!!!

[luffy]

Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.

what are we looking at? exactly? :p

[psilan]

What is a large amount of money? 100k?

[macbook-air]

Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.

According rumors from Chinese source. Mr. Zhang is developing ASIC miners each running at 60 Ghash/s for US$1400. Existing Iracus and Lancelot users could sell their devices back (Iracus=$300, Lancelot=$400) in exchange for the new ASIC miner.

[kano]

http://i.minus.com/itzBd3W9qEQXQ.jpg

Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.

According rumors from Chinese source. Mr. Zhang is developing ASIC miners each running at 60 Ghash/s for US$1400. Existing Iracus and Lancelot users could sell their devices back (Iracus=$300, Lancelot=$400) in exchange for the new ASIC miner.

Awwww - I like my Icarus boards - best mining devices I've had.
Would be a pity to get rid of them now that I can even mess with programming them in the distant future since I bought the dev kit ...

... though as I have mentioned to other ASIC developers
ngzhang - send me one when you have them working and I'll have cgminer code hashing on it as fast as possible ready for release to the general public

[Dexter770221]

ngzhang - send me one when you have them working and I'll have cgminer code hashing on it as fast as possible ready for release to the general public

LAN or WiFi connection. No PC needed. But only 100MH/W thats the nail to coffin for this project...
Can wait to test new btstream

[ngzhang]

ngzhang - send me one when you have them working and I'll have cgminer code hashing on it as fast as possible ready for release to the general public

LAN or WiFi connection. No PC needed. But only 100MH/W thats the nail to coffin for this project...
Can wait to test new btstream

  i noticed that nobody mentioned power consume value at this time. so i decide to remove that rough estimate value too.

[flynn]

So If I understand this correctly, we can expect a new bitstream for our Lancelots very soon ?

[Dexter770221]

For those who ordered dev kit. There's trojan (Dynamer) on USB stick in file patch.exe, Altium Designer folder. Microsoft Security Essential reports that way. Don't have other antiviruses, so please confirm (or confirm that is not ) if you have any.

When that new bitstream will be achievable?

[flynn]

For those who ordered dev kit. There's trojan (Dynamer) on USB stick in file patch.exe, Altium Designer folder. Microsoft Security Essential reports that way. Don't have other antiviruses, so please confirm (or confirm that is not ) if you have any.

When that new bitstream will be achievable?

clamscan *
patch.exe: Trojan.Win32.Crack FOUND

ouch

[tnkflx]

For those who ordered dev kit. There's trojan (Dynamer) on USB stick in file patch.exe, Altium Designer folder. Microsoft Security Essential reports that way. Don't have other antiviruses, so please confirm (or confirm that is not ) if you have any.

When that new bitstream will be achievable?

clamscan *
patch.exe: Trojan.Win32.Crack FOUND

ouch

Upload to VirusTotal and check the output. This might be a false positive.

[flynn]

For those who ordered dev kit. There's trojan (Dynamer) on USB stick in file patch.exe, Altium Designer folder. Microsoft Security Essential reports that way. Don't have other antiviruses, so please confirm (or confirm that is not ) if you have any.

When that new bitstream will be achievable?

clamscan *
patch.exe: Trojan.Win32.Crack FOUND

ouch

Upload to VirusTotal and check the output. This might be a false positive.

ok

AhnLab-V3    Win-Trojan/Keygen.64512    20120612
... (snip for readability, ok it's confirmed that it's looking bad)
VirusBuster    Trojan.Keygen!XY128t5G1XY    20120612

[tnkflx]

Eh... If the patch.exe is a crack/keygen for Altium Designer this kind of sounds logical

[julz]

Eh... If the patch.exe is a crack/keygen for Altium Designer this kind of sounds logical

yeah.. that was my assumption... so  ssshhh!

[luffy]

what s the status of the new bitstream?
ok we will have asics but until then are we talking about 500Mh per board? (icarus,lancelot)
thanks

[Icoin]

ngzhang is it possible use the Lancelot board for other purposes like mining? I mean can it be used for controlling a ECA Reactor and pumps like Volt and Amps, and the Data from meters like PH Electrode, ORP Electrode, Conductivity Electrode and even output it to a small display/touchscreen?

[jl2012]

ngzhang is it possible use the Lancelot board for other purposes like mining? I mean can it be used for controlling a ECA Reactor and pumps like Volt and Amps, and the Data from meters like PH Electrode, ORP Electrode, Conductivity Electrode and even output it to a small display/touchscreen?

I don't think Lancelot is good at these. But you can do all these with a $35 Raspberry Pi through USB

[Dexter770221]

It is good, but developing bitstream will be slower than writing some C program. Or you may implement some softcore CPU and write program for it. For both solutions you need some A/D converters.

[jasinlee]

The new water cooling unit that dvb is funding, will you be working with them directly to integrate it onto the lancelot boards?

[Icoin]

The new water cooling unit that dvb is funding, will you be working with them directly to integrate it onto the lancelot boards?

The Qcool element is simply mountable on the Lancelot board the same way the actual cooler is mounted.

[jasinlee]

Any pricing available yet?

[Icoin]

Any pricing available yet?

Since DVB just sponsors the QCool watercool adapter for Lancelot and is not involved in sales, i can only say that the price will be probably between 4 and 8 BTC. It is sure that the price will be lower when more QCool elements can be produced at once.

[loshia]

ngzang,
Is it safe to try 200 MHZ test bitstrem with lancelot. What i am asking if is  possible to "kill" the board while priograming it? Waht is the original bitsream flashed inside lancelots (for recovering purpose)
Shall we expect your bitstream to be available soon?
10X
PS:Week is passing and we do have half of the big news as prommised - the core picture only

[flynn]

Before we get anything better, the Icarus 200Mhz-test bitstream is working fine on my Lancelot =>

 ICA 0:                | 399.4/397.4Mh/s | A:207 R:1 HW:0 U:3.50/m

[loshia]

Before we get anything better, the Icarus 200Mhz-test bitstream is working fine on my Lancelot =>

 ICA 0:                | 399.4/397.4Mh/s | A:207 R:1 HW:0 U:3.50/m

flynn,
Which version of cgminer are you using? I am not quite sure that it works beter because utilty is too low it should be aroung > 5.5
Old versions of cgminer were not showing any HW errors. Pls double check the results and compare your hashrate with your pool stats...

[flynn]

flynn,
Which version of cgminer are you using? I am not quite sure that it works beter because utilty is too low it should be aroung > 5.5
Old versions of cgminer were not showing any HW errors. Pls double check the results and compare your hashrate with your pool stats...

cgminer 2.4.2

I am unable to download the latest version from github rightnow, it seems broken or something. I'll retry later
Meanwhile I put back the old bitstream :
  ICA 0:                | 378.7/372.6Mh/s | A:20 R:0 HW:0 U: 7.03/m

[loshia]

flynn,
Which version of cgminer are you using? I am not quite sure that it works beter because utilty is too low it should be aroung > 5.5
Old versions of cgminer were not showing any HW errors. Pls double check the results and compare your hashrate with your pool stats...

cgminer 2.4.2

I am unable to download the latest version from github rightnow, it seems broken or something. I'll retry later
Meanwhile I put back the old bitstream :
  ICA 0:                | 378.7/372.6Mh/s | A:20 R:0 HW:0 U: 7.03/m

The old one is OK what you can see is the U: 7.03/m - That is fine...When you run it for longer U  will be about 5-5.5

[flynn]

Err,

ngzhang ? Weren't you supposed to deliver a faster bitstream for the Lancelot any time ?

[tucenaber]

He seems to have moved on to catch bigger fish. A shame really.

[makomk]

Hmmmm... I haven't blown up any FPGAs lately. This is bitstream-compatible with Icarus, right?

[flynn]

Hmmmm... I haven't blown up any FPGAs lately. This is bitstream-compatible with Icarus, right?

AFAIK yes;

[loshia]

Hmmmm... I haven't blown up any FPGAs lately. This is bitstream-compatible with Icarus, right?

AFAIK yes;

Yes it is. The difference between cm1 and icarus should be


https://github.com/ngzhang/Icarus/blob/master/FPGA_project/Src/fpgaminer_top.ucf
# UCF for a Nexys2 500K board
NET "osc_clk" LOC = "J1";

# serial port receive & transmit
NET "RxD" LOC = "D1";
NET "TxD" LOC = "B1";

# TTL level serial port: ja3 = rxd, ja2 = txd
NET "extminer_txd<0>" LOC = "D22";
NET "extminer_rxd<0>" LOC = "B22";

there is a chance your bitstream to work on one core only....

makomk, what do you think about that? Will your bitstream work?

[Dexter770221]

Don't bother loshia. Spartan3 500k will not perform faster than 2MH/s....

[loshia]

Don't bother loshia. Spartan3 500k will not perform faster than 2MH/s....

it is spartan 6 and it is performing...The git file source has been edited probably and what i see is commented

[Dexter770221]

Digilent Nexys2 500k board:
http://www.kamami.pl/index.php?ukey=product&productID=59725

[flynn]

bump ...

[luffy]

is the new bitstream project just stale or cancel?

[irritant]

can anyone confirm?

[Dexter770221]

No one exept ngzhang, but it seems that he is no longer visit this topic. Shame, really shame. And its always about money...

[Energizer]

If you are interested in buying Icarus boards to mine today, then upgrade it to ASIC whenever avalon ASIC is available, check my Icarus sale thread here: https://bitcointalk.org/index.php?topic=115154.0

[Icoin]

LancelotQC runs with around 32°C on the original bistream. i would like to run the x6500 overclocker bitstream, does someone know if that bitstream is adjustable for lancelot??
http://www.fpgamining.com/documentation/firmware
http://www.fpgamining.com/content/03-documentation/03-firmware/x6500-overclocker-0402.bit

[hardcore-fs]

400MH/S from DUAL spartan6 with two cores each. That is FUCKING tragic.

I'm moving my 'demo' single XUPV5 with SINGLE core FROM 160MH/s to 200MH/s later today.
so based on that, two XUPV5 should give me 400MH/s,   therefore  Two spartan 6 with dual core should be hitting 800MH/s!!!

Plus the shit XUPV5 is only hitting 43 deg. C with an ambient of 25 Deg. C.

HC.

[makomk]

I'm moving my 'demo' single XUPV5 with SINGLE core FROM 160MH/s to 200MH/s later today.
so based on that, two XUPV5 should give me 400MH/s,   therefore  Two spartan 6 with dual core should be hitting 800MH/s!!!

Nope, single core each. Spartan-6 chips are actually quite a bit worse at Bitcoin mining than comparably-sized Virtex ones, it's just that the price difference more than makes up for it.

[punin]

Spartan-6 chips are actually quite a bit worse at Bitcoin mining than comparably-sized Virtex ones, it's just that the price difference more than makes up for it.

Word. I'm running -3I chips and max out at 300Mhps per chip.

[ngzhang]

https://github.com/ngzhang/Lancelot

all hardware documents released.

also released a 460~ 520 MH/s bitsteam for Lancelot.

for test purpose only. please carefully test it with the bit file before flash the MCS file into the EEPROM.

Temporarily no technical support for the new bitsteam, Busy with Avalon.

[flynn]

Wow ! very good news ! Thank you Ngzhang !

I'll try that asap


ps: it's named "42" of course

[flynn]

With cgminer 2.4.2 (which I know is not showing HW errors) and --icarus-timing=90

GPU 0:  70.0C 1893RPM | 327.7/342.3Mh/s | A:24 R:0 HW:0 U:  4.22/m I: 4
 ICA 0:                             | 344.2/451.4Mh/s | A:43 R:0 HW:0 U:  7.56/m

I have no idea if this is good or bad

[ngzhang]

With cgminer 2.4.2 (which I know is not showing HW errors) and --icarus-timing=90

GPU 0:  70.0C 1893RPM | 327.7/342.3Mh/s | A:24 R:0 HW:0 U:  4.22/m I: 4
 ICA 0:                             | 344.2/451.4Mh/s | A:43 R:0 HW:0 U:  7.56/m

I have no idea if this is good or bad

U 7.56/m means 550MH/s

[flynn]

With cgminer 2.4.2 (which I know is not showing HW errors) and --icarus-timing=90

GPU 0:  70.0C 1893RPM | 327.7/342.3Mh/s | A:24 R:0 HW:0 U:  4.22/m I: 4
 ICA 0:                             | 344.2/451.4Mh/s | A:43 R:0 HW:0 U:  7.56/m

I have no idea if this is good or bad

U 7.56/m means 550MH/s

Then this is good

ALtho, it's probably an illusion from some statistical variance

GPU 0:  70.0C 1894RPM | 326.8/331.8Mh/s | A:141 R:1 HW:0 U:  4.22/m I: 4
 ICA 0:                            | 282.6/424.1Mh/s | A:200 R:2 HW:0 U:  5.99/m

That's 430 MH/s

[luffy]

are you talking about icarus or lancelot?
it seems i have misplaced the paper included in the development kit and i don;t know how to connect JTAG to Lancelot
moreover the JTAG cable has 7 pins but the board only 6?!

[flynn]

are you talking about icarus or lancelot?
it seems i have misplaced the paper included in the development kit and i don;t know how to connect JTAG to Lancelot
moreover the JTAG cable has 7 pins but the board only 6?!

Lancelot
For the connection =>

https://bitcointalk.org/index.php?topic=79835.msg1167844#msg1167844

(board seen with JTAG at the bottom left)

[luffy]

thanks flynn,
you are the man!

[ngzhang]

paste a guide here.

warning:
1, not recommend for icarus board. but you try if you can take the risks.
2, if the board running abnormal, please switch back to the 380M bitsteam.
3, if the board invalid rate is higher than 10%, please switch back to the 380M bitsteam.
4, not guarantee every Lancelot board can normally operation with this bitsteam.
5, recommend you to use 42.bit for Interim test, it will lost if you turn off the board.

features:
1, fully auto speed regulation. about 460~520MH/s on Lancelot board.

how to update:
1, install XILINX Lab tooles (or ISE). i use V13.4. V14.2 may have some strange issues.
2, find and open "iMPACT" tool. press "cancel" if any dialog box popup.
3, connect the Platform Cable, power the board. the indicator light on the cable turn green.
4, click " Boundary Scan".  click "Initialize Chain". press "cancel" if any dialog box popup.
5, click "SPI/BPI ?" icon at the top of xc6slx150 device. and assign the MCS file. delect "SPI PROM", "W25Q64BV/CV", "1".
6, repeat step 5 for the other FPGA.
7, right click FLASH icon and select program.
8, wait for at least 8 min, than it will success.
9, turn off Icarus, and tun on. you will find the FLASH is already updated.
10, do  7~9 for the other FPGA.
11, finish.

Tips:
1, will significantly increase heat and power. about 23W pre board. so you need a power adaper can provide 12V@2A continuously.
2, cooling is very important. please DO NOT remove the original heat-sink and fan, they are enough for the top. use another fan blow from the side. the PCB it self is a heat-sink too.
3, not recommend for voltage adjustment. but if you want to do so, i don't block.
4, a typical invalid rate is 5%.
5, Job interval time can use about 6~7S for a better performance.
6, the speed measure is not accurate this time. please check the "shares pre hour" for a speed measures.
7, the JTAG pin is at bottom left of the board. from left to right: VCC/GND/TCK/TDO/TDI/TMS

[flynn]

@luffy : you're welcome


I updated to the latest version of cgminer,

GPU 0:                | 349.9M/348.2Mh/s | A:80 R:0 HW:0 U: 5.66/m I: 5
 ICA 0:                | 613.3M/422.6Mh/s | A:86 R:0 HW:1 U: 6.08/m

Just about no hardware error, gain is ~ +20% (420 MH/s instead of 380)
Maybe it doesn't go higher because I don't have a fan blowing on the side, I'll try that tomorrow and will report if it makes a difference.

Do you think I can program the PROMs of the board now ?

[Edit] I just Flashed both chips. This works better than V3 at any rate

[luffy]

A:3670 R:57 HW:79 U:4.9
not working for me
going back to default bitstream

[flynn]

A:3670 R:57 HW:79 U:4.9
not working for me
going back to default bitstream

Try to flash only one FPGA ? Maybe only one of the two is making all the errors

[libertybuck]

> 1, not recommend for icarus board. but you try if you can take the risks.

I tested it with my Icarus. Could got 350 MHash or so. (Tested under RG7Miner). Finally I rolled it back to version V3.

[loshia]

That sounds great!

Ngzhang you are the one to be trusted!

Thank you very much!!!

I will test it in the evening.
Just a side question. Where we can get default Lancelot Bitstream just in case? Is it same bitstream used with icarus V3?
10X

[ngzhang]

That sounds great!

Ngzhang you are the one to be trusted!

Thank you very much!!!

I will test it in the evening.
Just a side question. Where we can get default Lancelot Bitstream just in case? Is it same bitstream used with icarus V3?
10X

yep，same as icarus V3.
by my test, 95% boards will get a at least 20% promotion, over 50% get more than 30%.
add some core voltage will help, default Lancelot core voltage is 1.16V, you can change it to 1.26V by change R56 and R47 to 9.1K. certainly, there are risks and more heat.

A:3670 R:57 HW:79 U:4.9
not working for me
going back to default bitstream

maybe some new slower bitsteam for icarus will announce soon.

A:3670 R:57 HW:79 U:4.9
not working for me
going back to default bitstream

Try to flash only one FPGA ? Maybe only one of the two is making all the errors

don't do that.

about why is V42: it's the 42 version last month... 

will continue improve it, but .. i hope will some more smoothly. 

[loshia]

Super!
------------------------
add some core voltage will help, default Lancelot core voltage is 1.16V, you can change it to 1.26V by change R56 and R47 to 9.1K. certainly, there are risks and more heat.
------------------------
Can you give us some info what additional boost are you getting when changing the resistors. Heat and power are no issue since winter is comming:)
I just want to know the numbers to make my decision. For instance difference in performance "%" between your best board with 42 bitstream stock resistors compared to same board with  R56 and R47 to 9.1K?

10X

[flynn]

Try to flash only one FPGA ? Maybe only one of the two is making all the errors

don't do that.

about why is V42: it's the 42 version last month...  

Why can't we have a different bitstream on each FPGA ? apart from the timing (--icarus-timing default=xx) I don't see why it wouldn't work ?

42 : I was of course referring to the hitchhiker's guide to the galaxy

[rgzen]

Hello,
I have installed 13.2 and when I try to do the flash I receive this message:
ERROR:iMPACT - The assigned file exceeds the capacity of the largest flash device supported for indirect flash programming using iMPACT.

Any answer for this??

[libertybuck]

I faced the same issue. It was because you trying to flash a corrupt bitstream file.

I suggest you download the whole Lancelot project file as a zip file and then unzip it locally in this way you could got a correct bitstream file.

[ngzhang]

sorry guys, i test the bitsteam with the 2nd batch of Lancelot, which is default using 9.09K（9.1K can use） for R56 and R47. (1.24V Vcore)it's about 20~30% improvement compare to V3.

today i find a very few 1st batch Lancelot, with 10K for R56 and R47. (1.16V Vcore) it seems will much slower than the 2nd batch. but on average there is still about 10%~15% improvement.

so if possible, i suggest you to change R56 and R 47 for a additional benefit. notice that the 2 resistors is very important, the soldering quality is important. and do not let Vcore above ~1.3V when idling.

how to know which board is 2nd batch: all 2nd batch board have a soldered black 40PIN header, that 1st batch haven't.

[loshia]

nghzang (or someone else),
i am not good with hardware at all. is it possible just to take a shot of lancelot an mark where two resistors are. otherwise i have a friend to do soldering for me but pcb schematics are beyond our knowledge

 

[luffy]

yes, an image about v1 and v2 differencies and location of resistors will be great!

[rgzen]

I faced the same issue. It was because you trying to flash a corrupt bitstream file.

I suggest you download the whole Lancelot project file as a zip file and then unzip it locally in this way you could got a correct bitstream file.

Oooh! yes that is...
Thanks

[Dexter770221]

After 2 hours of fight with ISE WebPack finally I was able to load new bitstream. Of course, ISE throw on me some idiotic messages insted of simple one that would say "Hey idiot, iMpact do not support slx150 becuse it's a part of WebPack". Reinstall and new lic key done the job right
Mine board achieves 420MH/s (batch 1). Cgminer doubles that and shows 840 . I've run it with option --icarus-timing long. Reported values are also wrong 1.2ns and should be ~2.4ns. After tommorow I will solder ekstra resistors and see if that will improve performance.

[rgzen]

Hello,
I have done some examinations and I think I found the resistors...
I write here for confirm if I am right or not. So I do not guarantee it at all!!!
Could someone confirm it?

(You can see the boxed text in the status bar of the schematics where it is written the name of the component selected with its value)

R47:

http://anonymouse.org/cgi-bin/anon-www.cgi/http://anonymouse.org/cgi-bin/anon-www.cgi/http://img20.imageshack.us/img20/1702/r47h.jpg

R56:

http://anonymouse.org/cgi-bin/anon-www.cgi/http://anonymouse.org/cgi-bin/anon-www.cgi/http://img839.imageshack.us/img839/4534/r56rz.jpg

[libertybuck]

Mine board achieves 420MH/s (batch 1). Cgminer doubles that and shows 840 . 

Oh. So good ?!

Pity that my board is icarus bought from xiangfu. Could not utilize the powerful update.

[luffy]

you should check only the Utility (U:) . my icarus has 5.2 but lancelot with new bitstream 4.9, thus old bitstream is
better. i will see if i can solder new registors, i guess v1 is the board that is shown in the very first picture of this thread
by ngzhang  

[Dexter770221]

U: 5.7 after 1 hour.

[kano]

U: 5.7 after 1 hour.

Assuming it doesn't die, the U value will begin to converge on the expected average after a few days ... on a 1 diff pool.

[libertybuck]

you should check only the Utility (U:) . my icarus has 5.2 but lancelot with new bitstream 4.9, thus old bitstream is
better.

Sir, can you please tell me which version of bitstream your icarus is using ?  V3 or which one ?

[hardcore-fs]

nghzang (or someone else),
i am not good with hardware at all. is it possible just to take a shot of lancelot an mark where two resistors are. otherwise i have a friend to do soldering for me but pcb schematics are beyond our knowledge

 

If someone is in Hong Kong or can donate a "Lancelot"  I can take a look at this and do a tutorial, including an idiots guide to loading/flashing the bitstream, possibly WITHOUT using the ISE.
Then I can sit down and run a set of bench marks.

I'm just sat about waiting for delivery of ASIC boards/ Stock trading, so I need a project to keep me busy.

HC

[luffy]

you should check only the Utility (U:) . my icarus has 5.2 but lancelot with new bitstream 4.9, thus old bitstream is
better.

Sir, can you please tell me which version of bitstream your icarus is using ?  V3 or which one ?

i am not sure but i guess the final batch since Lancelot was already announced
to avoid misunderstandings, i haven't flashed Icarus. It is using the default bitstream.

[loshia]

I just wanna share my result so far...
All Lancelot's are v1 lower core voltage


 ICA  0:                | 758.9M/858.7Mh/s | A:2699 R:0 HW:71 U:  5.62/m
 ICA  1:                | 870.0M/888.8Mh/s | A:2822 R:1 HW:49 U:  5.87/m
 ICA  2:                | 884.2M/889.8Mh/s | A:2780 R:2 HW:26 U:  5.78/m
 ICA  3:                | 880.9M/874.2Mh/s | A:2757 R:0 HW:54 U:  5.74/m
 ICA  4:                | 865.6M/880.2Mh/s | A:2724 R:2 HW:52 U:  5.67/m
 ICA  5:                | 857.9M/876.1Mh/s | A:2748 R:0 HW:35 U:  5.72/m
 ICA  6:                | 873.7M/865.3Mh/s | A:2777 R:0 HW:56 U:  5.78/m
 ICA  7:                | 857.5M/867.4Mh/s | A:2735 R:0 HW:34 U:  5.69/m
 ICA  8:                | 866.8M/866.5Mh/s | A:2790 R:0 HW:54 U:  5.80/m
 ICA  9:                | 708.7M/861.4Mh/s | A:2698 R:0 HW:43 U:  5.61/m
 ICA 10:                | 880.1M/874.1Mh/s | A:2736 R:0 HW:70 U:  5.69/m


Average utilization with stock v3 bitstream was about 5.2 - 5.3 which is about 10% improvement
My next step will be to bump up core voltage to 1.26 as suggested and i will share results..
Nghzang,
Can we bump input voltage a little bit more? Is it safe to stay below 1.3 V as you suggested. Probably 1.295 IDLE will be even better instead of 1.24?

[rgzen]

I have U: 6.6/m after 25 minutes, v1 with resistors changed.

[loshia]

I have U: 6.6/m after 25 minutes, v1 with resistors changed.

Pls let us know what will happen with U 24 hours later. Have you measured Core voltage before/after changing resistors?

[rgzen]

I have U: 6.6/m after 25 minutes, v1 with resistors changed.

Pls let us know what will happen with U 24 hours later. Have you measured Core voltage before/after changing resistors?

Yes I measured before (1.178 and 1.181 aprox) and after (1.238 and 1.236 aprox).

And now it has 50 minutes running and it is at 5.63/m

[loshia]

5.63 seems like no improvment? What about utility before changing the res? Have you measured that?

[rgzen]

I have not notice much improvement without change the resistors. May be a 5 % or so...

[loshia]

That is why i plan to bump voltage on mines little bit more using potentiometer (Zetex voltmod  probably i will get 500K in parallel)
I will do it this weekend and will share the results  - i plan to bumop it around 1.28-1.29 < 1.30 just to be on a safe side as nghzang suggested:)

[luffy]

v1 Lancelot (stock voltage) after 10 hours with --icarus-timing long i get better results:
A:3617 R:59 HW:92 U:5.5

[Dexter770221]

I've done it. Soldered 2x68k in serial on top of original 10k resistor. 1206 packages (I didn't have other values). Voltage jumped from 1.17V to 1.22V. So far so good but I don't see any big improvement... Results later.

[libertybuck]

It is really a magic that all miners are electronic engineers

[kano]

v1 Lancelot (stock voltage) after 10 hours with --icarus-timing long i get better results:
A:3617 R:59 HW:92 U:5.5

Don't forget that long (and short) depends on how idle the computer is.
long of course will keep correcting that forever, but short stops after a while and uses what it's worked out up to then.

The problem with both is that on a variable clock, it will sometimes be too long ... if the clock goes up by even 2%.
If you have a static clock then no issues, but you can then also use what's described below anyway.

However with a variable clock:

The fix is to actually specify the values.

It doesn't matter if they are a little out - that will only affect the MH/s reported ... as long as it's not too far out.

Try this instead:

--icarus-timing 2:70

2 (2ns) (Hs) means it clocks at 435MH/s (instead of 380MH/s) which just means that the MH/s reported will not be correct
1/(2x10^-9) H/s

70 (7.0s) (read_count) will be OK up to 613MH/s
(2^32/(70/10)) H/s

The issue of the '70' value is it MUST be less than the time it takes to check the full nonce range.
The closer it is to the correct time, the lower the overhead of getting more work.
That overhead is, however, very, very small.
It determines how much of each nonce range is checked (unless a share is found) but aborting early doesn't affect the probability of finding shares.
Normally the '70' (read_count) is calculated from the other Hs value
info->Hs = Hs / NANOSEC;
info->fullnonce = info->Hs * (((double)0xffffffff) + 1);
info->read_count = (int)(info->fullnonce * TIME_FACTOR) - 1;
Hs=2 TIME_FACTOR=10 NANOSEC=10^9

The internal usage of the '2' value ensures correct MH/s display when a share isn't found.

P.S. I failed electrical engineering and got a Comp Sci degree

[luffy]

@kano: many thanks, i will try it
@Dexter770221: can you please confirm the registors' location given by rgzen?
thanks

[Dexter770221]

Thanks Kano for the additional info about that timings. Propably "long" will report very close to your calculations. After 12 hours U:5.8 (from 5.7), so it's little improvment, however hardware errors dropped to ~3% (previously was ~5%).
Yes luffy, resistors showed by rgzen are correct one.

[luffy]

ok!
then what resistor can we solder in parallel with the current one in order to get 1.24v-1.28v?
and what are the pins where we measure the VCC voltage?

[loshia]

ok!
then what resistor can we solder in parallel with the current one in order to get 1.24v-1.28v?
and what are the pins where we measure the VCC voltage?

http://www.1728.org/resistrs.htm
Calculation showed about 90-100K
+1 for the question where to measure VCC out core voltage

[Dexter770221]

ngzhang mentioned that this resistor should be somwhere around 9k. R=(R1*R2)/(R1+R2)=(10*100)/(10+100)=1000/110=9.09k. 100k in parallel should be perfect.
When board is placed in front of you as is on rgzen pictures, 4 holes for measure voltage are placed on the right edge of the board. They are visible on bottom picture, near 270uF capacitor and coil.

[loshia]

ngzhang mentioned that this resistor should be somwhere around 9k. R=(R1*R2)/(R1+R2)=(10*100)/(10+100)=1000/110=9.09k. 100k in parallel should be perfect.
When board is placed in front of you as is on rgzen pictures, 4 holes for measure voltage are placed on the right edge of the board. They are visible on bottom picture, near 270uF capacitor and coil.

Hey,
thank you for the update! It seems that you know hardware stuff better than me (i am not expert at all). From what i have seen in pdf (core_power) schematic (i might be wrong of course) we have to measure a voltage VCCINT1V2_A and  VCCINT1V2_B. Is that true? If it is, are the wholes you are referring to equal to "VCCINT1V2_A and  VCCINT1V2_B". If yes, would it be very hard for you just to mark them on the picture, because it is very hard for me to find them out:)
Once again excuse me but as i said i am not an expert at all:)

[Dexter770221]

http://i.minus.com/iOoHctgIXSDTB.JPG - picture from first post (courtesy of ngzhang).
At the edge of the board you can see 4 holes (right side, white squares around it) labeled GND, V.CORE1, V.CORE2, V.AUX. Those are test points for this voltages. V.AUX is 3,3V for IO.

[loshia]

http://i.minus.com/iOoHctgIXSDTB.JPG - picture from first post (courtesy of ngzhang).
At the edge of the board you can see 4 holes (right side, white squares around it) labeled GND, V.CORE1, V.CORE2, V.AUX. Those are test points for this voltages. V.AUX is 3,3V for IO.

Thanks!
I got it...

[rgzen]

Sixteen hours past since the miner started it throws the following:

(5s):526.7 (avg):483.0 Mh/s | Q:1250  A:5336  R:64  HW:0  E:427%  U:5.7/m

According to my calcs it is more less 411 MH/s or around 8% improvement...
I repeat that I have the first version flashed with the V42 bitstream and the resistors changed and --icarus-timing 2:70 with cgminer 2.7.4.
So I am asking... What are your results with other configurations??

PD: And I have too curiosity of know what are exactly the differences between the first and the second version of the board.

[Dexter770221]

After my mod (136k in parallel with 10k resistors, Vcore@1.22V) I'm getting U:5.8, error rate ~3%. It's not big improvement but always it's something. I think that ngzang just posted little modified bitstream with auto adjusted clock, version "handy placed small cores" is still in his possesion and he don't want to share with it...

[rgzen]

hey
can you tell me with the info I have posted how much is my hardware error rate?
It is possible yo be 0%?
thanks

[rgzen]

or it can be R/(A+R)? in this case around 1.2%

[kano]

hey
can you tell me with the info I have posted how much is my hardware error rate?
It is possible yo be 0%?
thanks

cgminer before 2.7.6 doesn't report HW: for the Icarus driver.
So you won't known unless you are using 2.7.6 (where I added it) or later.
... preferably the latest version

[rgzen]

ok, I have upgrade my software.

thanks

[luffy]

i upgarded too. i noticed that even icarus board without any modifications has a few HW hits although none of my VGAs (7950,5870,5970) has any!

[kano]

i upgarded too. i noticed that even icarus board without any modifications has a few HW hits although none of my VGAs (7950,5870,5970) has any!

I get about 0.2% on my 2 original Icarus boards.

The GPU code always reported HW: errors, but the others didn't.
GPU's often get none - usually only get them when over heating of over clocking too far
(I'm not sure if I've ever had a HW error on one my 6950 GPUs in 16 months - the other one fan failed and got replaced so had a few when that happened)

Anyway, I changed it so all devices (except ztex) go through the same (new) HW check code
(after I realised that it wasn't doing that - which I thought it was in the FPGA code)

[loshia]

kano,

It may sound stupid but i am little bit confused of values i see. As you noted with new bitstream and timing 2:70 Mhs reporting will not be correct. To make things easy, assuming that cgminer shows  correct values for my gpu as follows:

MHS av   MHS 3s   Accepted   Hardware Errors Utility   
 391.03   391.16   6,129                    0       5.55/m

For my best lancelot board values are as follows:
MHS av   MHS 3s   Accepted   Hardware Errors        Utility   
506.35   662.20   6,651             131                  6.02

What about calculating Lancelot performance in following way
Lancelot Utility/GPU Utility*GPU MHS av
 6.02/5.55*391.03 = 424 Mhs

What about HW errors - are they taken into account when calculating utility. In my case for Lancelot they are 1.97% (131/6,651*100). Shall i do something like:
424/100*98.03=415.64

Thanks

[kano]

kano,

It may sound stupid but i am little bit confused of values i see. As you noted with new bitstream and timing 2:70 Mhs reporting will not be correct. To make things easy, assuming that cgminer shows  correct values for my gpu as follows:

MHS av   MHS 3s   Accepted   Hardware Errors Utility   
 391.03   391.16   6,129                    0       5.55/m

For my best lancelot board values are as follows:
MHS av   MHS 3s   Accepted   Hardware Errors        Utility   
506.35   662.20   6,651             131                  6.02

What about calculating Lancelot performance in following way
Lancelot Utility/GPU Utility*GPU MHS av
 6.02/5.55*391.03 = 424 Mhs

What about HW errors - are they taken into account when calculating utility. In my case for Lancelot they are 1.97% (131/6,651*100). Shall i do something like:
424/100*98.03=415.64

Thanks

MHS of course will be wrong:
Every time work is aborted (no nonce found before timeout, or an LP occurs) it has to determine how many hashes were done.
The Hs value is used to calculate that
Every time it finds a share ... it knows how many hashes were done since the share value tells that.

However, the number of shares Accepted, Rejected, Stale, HW, U, pretty much everything else is correct.

Yes you can estimate your hash rate from U - but you'd have to run for a few days to ensure it's close.
Even after a few hours it can (rarely) be out by 10% (which is a lot)

anyway yep Hashes/s is simply (2^32) * U/60 (for 1 diff shares)

U is only accepted shares.

A, R, SS and HW are all independent.

To work out the HW % = HW / (A + R + SS + HW)

[loshia]

thank you Kano!

I got the U formula.


What about if pool is not 1 diff shares let us say it is dynamic? If it is static let us say 2 diff shares all is easy - 2^33 right?
Best

[kano]

thank you Kano!

I got the U formula.


What about if pool is not 1 diff shares let us say it is dynamic? If it is static let us say 2 diff shares all is easy - 2^33 right?
Best

U = 60 * accepted shares / elapsed time
However, I also added the difficulty versions of A + R + SS into the API in cgminer
(they are also printed in the summary when you exit)

So to get the correct U based on difficulty it's:
 60 * "Difficulty Accepted" / "Elapsed"
from the API 'summary'

(however note, HW is not difficulty based, it's 1diff share based)

[loshia]

Thank You!

[loshia]

Kano,

I have tried --icarus-timing 2:70. I was running it for two days. I have saved the results.

Today i changed the resistors on a couple of my boards. With 2:70 i see a lot of times two yellow leds (on ones with VCC core increased -changed resistors) - The sign on top of the leds is IDLE. When i run cgminer with icarus-timing long No yellow leds - these broads (changed resistors) are blinking like the rest

Can you comment that pls.
Thank you

I can compare the results after two days or so...

[kano]

Kano,

I have tried --icarus-timing 2:70. I was running it for two days. I have saved the results.

Today i changed the resistors on a couple of my boards. With 2:70 i see a lot of times two yellow leds (on ones with VCC core increased -changed resistors) - The sign on top of the leds is IDLE. When i run cgminer with icarus-timing long No yellow leds - these broads (changed resistors) are blinking like the rest

Can you comment that pls.
Thank you

I can compare the results after two days or so...

What does the API say for 'stats' about the ICA devices? (both for the ones running 'long' and the ones running '2:70')
(There are 16 Icarus specific stats in there)

You of course have to enable the API with --api-listen and can then request API 'stats' from the computer running cgminer at 127.0.0.1 ... or read the API-README

[loshia]

Kano,
Unfortunately i did not saved api-stats with timing 2:70. I am posting results with timing long. If they are not enough i can run some boards with 2:70 and some with long and post back the results tomorrow


Full nonce for moded boards with U ranging between 6.3-6.5 is:
4.413108
4.329242
4.273607
4.347153

HS:

0.000000000999920
0.000000000981032
0.000000000965784
0.000000000984132


Full nonce for rest is with U ranging between 5.5 -5.7 is:
4.989389
4.936110
4.984062
4.896753

HS:
0.000000001134453
0.000000001115143
0.000000001132101
0.000000001110573

Is that info enough?

Best

[kano]

That's suggesting they are running at around 1GH/s so I guess there must be a problem (since the U isn't 1GH/s more like ~460MH/s)
Maybe the new bitstream divides the work up differently?

All 16 values for a device would be more useful ...

Anyway - if those numbers were correct then it would be something like: 1:40

Also, the Icarus code defaults to 2 devices (which you can change with --icarus-options) that divide the nonce-range in half (however the division 'method' based on the number of devices is fixed) - so I'm not sure exactly what the bitstream is doing different to give those numbers you are getting.

... however ... if the bitstream is adjusting the clock ... then yes timing long/short would not give correct results.

long/short timing assumes the clock is fixed - if it isn't it wont work without knowing the clock for each result (and me rewriting the timing code to handle that)

Try 1:40 and see what happens ...

[loshia]

Thanks Kano!
I am trying it and i will post the results
Best

[loshia]

Kano,

Here are results with timing=long for 11 hours

Please note ICA0-ICA3 and ICA26-ICA29 are with changed resistors for sure. There are at lest 3-4 boards from the rest with changed resistors, but unfortunately i can not remember their numbers

Best

	0	GPU0	41672	971221	363.593085	1.400034	0.000000
	1	ICA0	41672	12336	2.510747	0.048282	0.000002	43	4.413108	10	0.000000000999920	0.118484	1600	4274231664	4605	0.008396	160	119	long	true	115200	2	2
	2	ICA1	41672	12473	2.961499	0.214484	0.000002	42	4.329242	10	0.000000000981032	0.115743	1600	4242677362	4541	0.008696	160	62	long	true	115200	2	2
	3	ICA2	41672	12649	5.315056	1.476899	0.000002	41	4.273607	10	0.000000000965784	0.125597	1600	4288070182	4707	0.009180	160	71	long	true	115200	2	2
	4	ICA3	41672	12569	3.502263	0.262402	0.000002	42	4.347153	10	0.000000000984132	0.120340	1600	4292662870	4606	0.008492	160	129	long	true	115200	2	2
	5	ICA4	41672	11004	3.566485	0.946676	0.000002	48	4.958089	10	0.000000001126098	0.121535	1600	4278299352	4115	0.007690	160	115	long	true	115200	2	2
	6	ICA5	41672	10893	3.635474	0.945021	0.000002	48	4.978525	10	0.000000001125178	0.145921	1600	4261545708	4112	0.007901	160	110	long	true	115200	2	2
	7	ICA6	41672	10946	3.711691	0.998559	0.000002	48	4.961865	10	0.000000001124789	0.130935	1600	4272433342	3975	0.007576	160	137	long	true	115200	2	2
	8	ICA7	41672	10928	2.661877	0.121210	0.000002	48	4.967016	10	0.000000001125969	0.131015	1600	4291956988	4096	0.007345	160	97	long	true	115200	2	2
	9	ICA8	41672	10917	2.841205	0.119703	0.000002	48	4.989389	10	0.000000001134453	0.116952	1600	4277281596	4072	0.008135	160	71	long	true	115200	2	2
	10	ICA9	41672	10971	5.718872	1.240576	0.000000	48	4.936110	10	0.000000001115143	0.146609	1600	4290746994	4003	0.007442	160	6	long	true	115200	2	2
	11	ICA10	41672	10752	4.543638	1.384864	0.000002	48	4.984062	10	0.000000001132101	0.121727	1600	4281984372	3965	0.008019	160	130	long	true	115200	2	2
	12	ICA11	41672	11059	2.743326	0.119330	0.000001	47	4.896753	10	0.000000001110573	0.126880	1600	4266670588	4025	0.007508	160	29	long	true	115200	2	2
	13	ICA12	41672	10615	4.528384	1.233007	0.000000	49	5.045424	10	0.000000001130485	0.190026	1600	4278466792	3931	0.007593	160	94	long	true	115200	2	2
	14	ICA13	41672	10748	4.613970	1.352324	0.000002	49	5.037712	10	0.000000001133836	0.167924	1600	4284039906	4016	0.007426	160	18	long	true	115200	2	2
	15	ICA14	41672	10900	2.733590	0.117377	0.000002	49	5.037367	10	0.000000001149880	0.098668	1600	4277803568	4073	0.007798	160	66	long	true	115200	2	2
	16	ICA15	41672	10953	2.718361	0.119965	0.000002	48	4.923011	10	0.000000001111331	0.149882	1600	4260984088	3991	0.007511	160	151	long	true	115200	2	2
	17	ICA16	41672	10950	2.537014	0.141895	0.000002	48	4.981943	10	0.000000001137081	0.098218	1600	4275359084	4045	0.008275	160	43	long	true	115200	2	2
	18	ICA17	41672	12350	3.726626	0.664459	0.000002	42	4.392341	10	0.000000000990362	0.138770	1600	4251259860	4497	0.008671	160	20	long	true	115200	2	2
	19	ICA18	41672	12250	2.975354	0.144306	0.000002	43	4.405313	10	0.000000000996196	0.126682	1600	4288208408	4492	0.008669	160	11	long	true	115200	2	2
	20	ICA19	41672	10650	2.721982	0.144693	0.000002	49	5.093104	10	0.000000001155094	0.132013	1600	4291332084	3830	0.007291	160	152	long	true	115200	2	2
	21	ICA20	41672	10913	2.605371	0.174266	0.000002	48	4.966502	10	0.000000001118462	0.162746	1600	4277245552	3974	0.007577	160	138	long	true	115200	2	2
	22	ICA21	41672	10764	2.726643	0.147668	0.000001	49	5.004606	10	0.000000001116213	0.210508	1600	4277395872	4042	0.007937	160	45	long	true	115200	2	2
	23	ICA22	41672	12375	2.626903	0.145837	0.000001	42	4.360790	10	0.000000000991422	0.102663	1600	4288569702	4461	0.008659	160	140	long	true	115200	2	2
	24	ICA23	41672	10710	3.086680	0.144996	0.000002	49	5.093802	10	0.000000001160190	0.110824	1600	4291315650	3985	0.007460	160	143	long	true	115200	2	2
	25	ICA24	41672	10922	2.751743	0.142671	0.000002	48	4.997611	10	0.000000001127309	0.155857	1600	4246874872	3966	0.007127	160	126	long	true	115200	2	2
	26	ICA25	41672	10864	3.041689	0.141176	0.000002	49	5.016164	10	0.000000001133526	0.147707	1600	4255465354	4046	0.008038	160	50	long	true	115200	2	2
	27	ICA26	41672	12312	3.044015	0.324907	0.000002	43	4.447452	10	0.000000001015595	0.085504	1600	4284001448	4519	0.008444	160	40	long	true	115200	2	2
	28	ICA27	41672	12472	3.749297	0.924476	0.000002	42	4.376254	10	0.000000000989404	0.126796	1600	4284850334	4452	0.008082	160	135	long	true	115200	2	2
	29	ICA28	41672	12406	2.959108	0.141556	0.000002	43	4.419099	10	0.000000000999569	0.125985	1600	4292420886	4649	0.009071	160	9	long	true	115200	2	2
	30	ICA29	41672	12646	3.233519	0.663727	0.000001	42	4.364028	10	0.000000000988383	0.118956	1600	4263208878	4791	0.008888	160	151	long	true	115200	2	2

[luffy]

i think i may have damaged the board while trying to solder the parallel resistors. now the Vin of every fpga
is stuck to 0.59v no matter how many times i try to solder the original smt registors back. the white leds are off,
all the other leds are on. i hope it is a matter of bad soldering and nothing else 

[loshia]

luffy,

Same happened to me also. Although original resistors look OK they were damaged. I suggest to find some 0603 Resistors and replace them. All will be fine. Another approach will be to unsloder them and cheek them with multimeter and  you will see that they are damaged (no resistance). Or you can measure the resistance between two ends of the resistors soldered on PCB. if they are damaged the resistance will be 10 KOhms if they are ok it should be about 5 Kohms

I was trying parallel soldering also. It turned out to be a bad idea because of easy "blowing out"
original ones. Better approach is just to replace them

[hardcore-fs]

DON'T try to continually solder resistors to your PCB.....

Get some VERY THIN FLEXIBLE linking wire, then solder that to the PCB, THEN do your testing by soldering the resistors to the ends of the wire.
That way you only solder your VALUABLE PCB once or twice, but you can solder and abuse your shitty connection wire multiple times.

[libertybuck]

DON'T try to continually solder resistors to your PCB.....

Get some VERY THIN FLEXIBLE linking wire, then solder that to the PCB, THEN do your testing by soldering the resistors to the ends of the wire.
That way you only solder your VALUABLE PCB once or twice, but you can solder and abuse your shitty connection wire multiple times.

Good idea.

[luffy]

thanks guys. i measure them around 3Kohm each. i wonder if i have damaged any neighbour resistor!

[loshia]

Probably you did. I can not be 100% sure but my core voltage was 0.5 like yours when they were 0 kohm each...being 3 kohm each it means that you should get very high VCC core (my oppinion) voltage or something else around is damaged which shall be the case

Try the wire thing as suggested. As stated PCB is easy to damage. If you happen to fix at least one of the cores you will able to measure correct core voltage

[fpf]

Dear N.G.Zhang,

Will the source code for that bitstream be published?
How does the FPGA determine the max. clock rate / hash rate?
Over the I2C temperature sensor that is available on the lancelot boards but not on the icarus boards?
And what does that mean in case of icarus boards.
What functions do the 4 dip switches have now? (Played a bit with them but it seems they lost their old functions and do some weird stuff now)

Regards

FPF

[hardcore-fs]

Probably you did. I can not be 100% sure but my core voltage was 0.5 like yours when they were 0 kohm each...being 3 kohm each it means that you should get very high VCC core (my oppinion) voltage or something else around is damaged which shall be the case

Try the wire thing as suggested. As stated PCB is easy to damage. If you happen to fix at least one of the cores you will able to measure correct core voltage

There are always better solutions (routing/VHDL/Verilog/partitioning optimizations)

Really no one should be playing with the core voltage, UNLESS they have enabled both in-chip/external temp  and external  current  measurement.

Problem is that such things that allow you to fiddle with the core voltage vary significantly from batch to batch & the age of the Chip.

You will find that current and internal die temp start to show signs that you are getting close to the danger zone, whilst you still have time to back them off.
Certainly making mods to a small group of FPGA then retroactively applying the 'fix' to masses of production out in the field, really is only going to end one way, plus such damage is really going to F*** any chances of returning the units for trade in.

The question should be:
Is the mod going to make more bit coins between now and trade in, than the trade in value of the device?

If not then leave it the F***  ALONE!!!

[burnin]

Dear N.G.Zhang,

Will the source code for that bitstream be published?
How does the FPGA determine the max. clock rate / hash rate?
Over the I2C temperature sensor that is available on the lancelot boards but not on the icarus boards?
And what does that mean in case of icarus boards.
What functions do the 4 dip switches have now? (Played a bit with them but it seems they lost their old functions and do some weird stuff now)

Regards

FPF

From what he said before i don't think so.
Would be awesome though.
The Source won't be the only key, i think he did a lot of manual routing stuff.

[blackarrow]

Hi!

We've tried v42 in -3C Xilinx FPGA and it is actually slower than the 200Mhz firmware.

N.G.Zhang, do you consider posting the code for the v42 firmware so we can fiddle with it?

Thank you.

[Dexter770221]

Hi!

We've tried v42 in -3C Xilinx FPGA and it is actually slower than the 200Mhz firmware.

N.G.Zhang, do you consider posting the code for the v42 firmware so we can fiddle with it?

Thank you.

+1!
There's always room for improvements

[induktor]

Hello
What happened to this project? is still alive? can I get dev-boards?, is some firmware already working with cgminer?

I just jumped into this and wanted to start playing with FPGA.
thanks

[wsoei]

Hello
What happened to this project? is still alive? can I get dev-boards?, is some firmware already working with cgminer?

I just jumped into this and wanted to start playing with FPGA.
thanks

you can buy them in this thread:
https://bitcointalk.org/index.php?topic=187549.0

[induktor]

you can buy them in this thread:
https://bitcointalk.org/index.php?topic=187549.0

Thank you!

[teknohog]

https://github.com/ngzhang/Icarus/blob/master/FPGA_project/Src/fpgaminer_top.ucf
# UCF for a Nexys2 500K board
NET "osc_clk" LOC = "J1";

# serial port receive & transmit
NET "RxD" LOC = "D1";
NET "TxD" LOC = "B1";

# TTL level serial port: ja3 = rxd, ja2 = txd
NET "extminer_txd<0>" LOC = "D22";
NET "extminer_rxd<0>" LOC = "B22";

Nice to see my serial clustering code (as originally developed on a Nexys2) is still alive and well