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Author Topic: FPGA development board "Lancelot" - accept bitsteam developer's orders.  (Read 95910 times)
2112
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June 21, 2012, 03:56:00 AM
 #161

Only if it's full below ~90nm, which means several million dollars in mask costs, a 6-9 month
mfg period, and a pretty good chance that the first chip is useless, unless you know WTF you are
doing
This is a gross overestimate. The folded, not-unrolled design is basically a two 32-bit-wide shift registers with some multi-input adders in a feedback and an adder-comparator on the output. The remaining logic is all standard cells: PLL, ROM and I/O.

SHA-256 is pretty much self-testing: there are no unreachable states and all every state is observable. Any internal fault will eventually show up on the outputs.

The lower level physical/analog design is what fucks over most amateur ASIC designs.

And again dual SHA-256 is a dream assignment for the beginners. It is small and it takes only about 64 or 128 simulated clocks to verify the entire custom circuitry. From my past experience with SPICE and BSIM4 I would venture to guess that I could simulate one clock cycle of an entire SHA-256 round on my Core2Duo laptop in one day.

The additional benefit for the team is that they have design closure achieved from the moment they pass automated DRC verification. All timing and power targets are soft, they have absolutely no interoperability requirements and any hard targets for timing closure or power closure. All they have to do is pick an  internal clock generation cell with variable multiplier.

I would guess that the chances of a "zero yield" first spin are atypically low for this design.

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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June 21, 2012, 04:52:35 AM
 #162

Only if it's full below ~90nm, which means several million dollars in mask costs, a 6-9 month
mfg period, and a pretty good chance that the first chip is useless, unless you know WTF you are
doing
This is a gross overestimate. The folded, not-unrolled design is basically a two 32-bit-wide shift registers with some multi-input adders in a feedback and an adder-comparator on the output. The remaining logic is all standard cells: PLL, ROM and I/O.

SHA-256 is pretty much self-testing: there are no unreachable states and all every state is observable. Any internal fault will eventually show up on the outputs.

The lower level physical/analog design is what fucks over most amateur ASIC designs.

And again dual SHA-256 is a dream assignment for the beginners. It is small and it takes only about 64 or 128 simulated clocks to verify the entire custom circuitry. From my past experience with SPICE and BSIM4 I would venture to guess that I could simulate one clock cycle of an entire SHA-256 round on my Core2Duo laptop in one day.

The additional benefit for the team is that they have design closure achieved from the moment they pass automated DRC verification. All timing and power targets are soft, they have absolutely no interoperability requirements and any hard targets for timing closure or power closure. All they have to do is pick an  internal clock generation cell with variable multiplier.

I would guess that the chances of a "zero yield" first spin are atypically low for this design.

I think what you are saying is a sha-256 asic is fairly simple and they should get it right the first time Huh?
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June 21, 2012, 05:09:15 AM
 #163

Only if it's full below ~90nm, which means several million dollars in mask costs, a 6-9 month
mfg period, and a pretty good chance that the first chip is useless, unless you know WTF you are
doing
This is a gross overestimate. The folded, not-unrolled design is basically a two 32-bit-wide shift registers with some multi-input adders in a feedback and an adder-comparator on the output. The remaining logic is all standard cells: PLL, ROM and I/O.

SHA-256 is pretty much self-testing: there are no unreachable states and all every state is observable. Any internal fault will eventually show up on the outputs.

The lower level physical/analog design is what fucks over most amateur ASIC designs.

And again dual SHA-256 is a dream assignment for the beginners. It is small and it takes only about 64 or 128 simulated clocks to verify the entire custom circuitry. From my past experience with SPICE and BSIM4 I would venture to guess that I could simulate one clock cycle of an entire SHA-256 round on my Core2Duo laptop in one day.

The additional benefit for the team is that they have design closure achieved from the moment they pass automated DRC verification. All timing and power targets are soft, they have absolutely no interoperability requirements and any hard targets for timing closure or power closure. All they have to do is pick an  internal clock generation cell with variable multiplier.

I would guess that the chances of a "zero yield" first spin are atypically low for this design.
So, in this arena - price wise what would be a very reasonable estimate of how much it would cost BFL?
(so I know if the major effort to very slightly possibly invalidate sha256 would be worth the while to kill their company)

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June 21, 2012, 06:28:02 AM
 #164

And again dual SHA-256 is a dream assignment for the beginners. It is small and it takes only about 64 or 128 simulated clocks to verify the entire custom circuitry. From my past experience with SPICE and BSIM4 I would venture to guess that I could simulate one clock cycle of an entire SHA-256 round on my Core2Duo laptop in one day.

The additional benefit for the team is that they have design closure achieved from the moment they pass automated DRC verification. All timing and power targets are soft, they have absolutely no interoperability requirements and any hard targets for timing closure or power closure. All they have to do is pick an  internal clock generation cell with variable multiplier.

I would guess that the chances of a "zero yield" first spin are atypically low for this design.

Since SHA-256 is so easy, why was BFL's FPGA power&performance estimates off by a factor of 5?

Buy & Hold
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June 21, 2012, 07:03:06 AM
 #165

Since SHA-256 is so easy, why was BFL's FPGA power&performance estimates off by a factor of 5?
I'm going to guess that they made the same mistake as the open source designers from another thread.

Since the design is so easy to get functionally correct they didn't bother to create the testbench for simulation and didn't run the full timing simulation.

Then they saved additional time by doing the probabilistic static power estimation, not the accurate power estimation that is driven by the simulation results from the testbench.

I'm also not sure about Altera's licensing and pricing model. There may be an additional license charge for the post-simulation power analyzer.

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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June 21, 2012, 07:19:37 AM
 #166

Since SHA-256 is so easy, why was BFL's FPGA power&performance estimates off by a factor of 5?

I know I am nitpicking, but they were off by "only" a factor of 4... A single draws 66W(*) from the 12V input --ignoring inefficiencies of the power adapter-- and 62W without counting the 2 (or sometimes 3) fans.

(*) Average measured from my batch with a clamp meter.
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June 21, 2012, 07:26:26 AM
 #167

4 times the power and 20% less speed iirc, combined a factor of 5 in Mh/$
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June 21, 2012, 07:47:23 AM
 #168

4 times the power and 20% less speed iirc, combined a factor of 5 in Mh/J (mrb: fixed unit)

Nope.

Announced: 1Gh/s at 20W = 50 Mh/J
Actual: 832Mh/s at 66W = 12.6 Mh/J

Difference in efficiency per Joule is a factor of 4. (Again I am not counting the power adapter inefficiencies which bumps the 66W to 80W or so at the wall).
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June 21, 2012, 09:01:10 AM
 #169

I think what you are saying is a sha-256 asic is fairly simple and they should get it right the first time Huh?
Yeah. This is pretty much a student project.
So, in this arena - price wise what would be a very reasonable estimate of how much it would cost BFL?
(so I know if the major effort to very slightly possibly invalidate sha256 would be worth the while to kill their company)
No idea. I always worked in a long-term R&D teams. I don't know anyone who does merchant one-shot jobs.

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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June 21, 2012, 09:41:09 AM
 #170

me thinks we got slightly off topic here... Cheesy

Zhang, how's things with lancelot?
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June 21, 2012, 03:08:21 PM
 #171

ok, report is here:
good news:
fixed all small bugs on the present Lancelot PCB, waiting for heat-sink sample for a final check. will push it to production stage. that means Lancelot will come out in batch in ~3 weeks.  Cheesy
bad news:
bitsteam build meet with some difficulties. no ETA can be  estimate.  Embarrassed

should i make Lancelot as a hardware platform only? you know there are a mass of 3-rd party mining bitsteams, and running really fast. is it good for me to sell Lancelot at a extreme low price and cooperate with those bitsteam makers?  Huh Lancelot have the best power module(14A continuous and 25A peak, 85% efficiency, for each FPGA) and  encryption support (eFuse key  storage and volatile memory key storage). and opensourced.  Huh


about the mining ASIC:

it's really easy to make a mining ASIC, but hard to make a "good" mining ASIC. that's  my point of view.

PS: please feel free to discuss or off topic in my thread. i'm a chinese and in chinese forums, all threads are off topic. it's  a usually situation for me.  Cheesy

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June 21, 2012, 03:18:10 PM
 #172

ok, report is here:
good news:
fixed all small bugs on the present Lancelot PCB, waiting for heat-sink sample for a final check. will push it to production stage. that means Lancelot will come out in batch in ~3 weeks.  Cheesy
bad news:
bitsteam build meet with some difficulties. no ETA can be  estimate.  Embarrassed

should i make Lancelot as a hardware platform only? you know there are a mass of 3-rd party mining bitsteams, and running really fast. is it good for me to sell Lancelot at a extreme low price and cooperate with those bitsteam makers?  Huh Lancelot have the best power module(14A continuous and 25A peak, 85% efficiency, for each FPGA) and  encryption support (eFuse key  storage and volatile memory key storage). and opensourced.  Huh


about the mining ASIC:

it's really easy to make a mining ASIC, but hard to make a "good" mining ASIC. that's  my point of view.

PS: please feel free to discuss or off topic in my thread. i'm a chinese and in chinese forums, all threads are off topic. it's  a usually situation for me.  Cheesy

If you have difficulty with the bitstream, you should work with third party bitstream a deal. And ship Lancelot in a complete working package. Thats the only solution. If you're shipping bare card there will only be a handful of customers.

You need to act quick because mini-rigs are already shipping. If the end product doesnt result a margin that you expected, its wise to cancel it.

Dont rush to production stage without having the bitstream issue sorted out.

Also, i already see your expected price of the Lancelot to be a bit high.
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June 21, 2012, 03:20:24 PM
 #173


bitsteam build meet with some difficulties. no ETA can be  estimate.  Embarrassed

should i make Lancelot as a hardware platform only?

Fine if the hardware is well priced, perhaps with the icarus bitstream in there to get things going.
Dont ship without a bitstream, at least something with expected performance of 400Mhash/sec.

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June 21, 2012, 09:12:37 PM
 #174

PS: please feel free to discuss or off topic in my thread. i'm a chinese and in chinese forums, all threads are off topic. it's  a usually situation for me.  Cheesy
How is the weather over there? It's rainy over here in the Netherlands.
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June 21, 2012, 09:44:33 PM
 #175

PS: please feel free to discuss or off topic in my thread. i'm a chinese and in chinese forums, all threads are off topic. it's  a usually situation for me.  Cheesy
How is the weather over there? It's rainy over here in the Netherlands.

No good start of the summer here in Berlin, either. I would be very much interested in buying one or two FPGAs though that I just need to plug in and press go. Preferably the fancy and cost-efficient Lancelot one.

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June 23, 2012, 08:54:10 PM
 #176

dear friend,
i am afraid that FPGA in 6 months time will turn obsolete! (ASIC time)
i wonder if you should put your efforts to openASIC or other ASIC project! Smiley
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June 23, 2012, 08:56:15 PM
 #177

dear friend,
i am afraid that FPGA in 6 months time will turn obsolete! (ASIC time)
i wonder if you should put your efforts to openASIC or other ASIC project! Smiley

 Grin let's see what will happen in the next 6 months.

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June 23, 2012, 09:20:24 PM
 #178

dear friend,
i am afraid that FPGA in 6 months time will turn obsolete! (ASIC time)
i wonder if you should put your efforts to openASIC or other ASIC project! Smiley

 Grin let's see what will happen in the next 6 months.
Yep. We will see. I still can't wait to order Lancelot...

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Changing one PCB with screwdriver and you have brand new miner in hand... Plug&Play, scalable from one module to thousands.
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you got hacked bitch!


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June 23, 2012, 09:21:40 PM
 #179

And these are worthless too!  Thanks asic!

I am the Bitcoinica Hacker.
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June 23, 2012, 09:41:25 PM
 #180

dear friend,
i am afraid that FPGA in 6 months time will turn obsolete! (ASIC time)
i wonder if you should put your efforts to openASIC or other ASIC project! Smiley

 Grin let's see what will happen in the next 6 months.

BFL is supposed to be taking preorders today. ASICs are bringing huge changes to Bitcoin, ones that could even effect non-miners. I believe all of these changes will be for the best in the long run though. Now we can just hope that the openasic project turns something out in the next few months!

“First they ignore you, then they laugh at you, then they fight you, then you win.”  -- Mahatma Gandhi

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