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Author Topic: FPGA development board "Lancelot" - accept bitsteam developer's orders.  (Read 95921 times)
loshia
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September 07, 2012, 04:57:20 PM
 #321

flynn,
Thanks for the update. The wise thing we can do is to wait for ngzang instructions - personal opinion. I think if we do something wrong we can "kill" the boards Shocked. More over there are some switches on the pcb prog1 and prog2. I personally do not have enough knowledge to look at the pcb files and find out what they are used for.
If someone else has the guts to try it and share the info with us will be great;)

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ngzhang
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September 10, 2012, 06:47:39 PM
 #322

come to say i'm still alive.

and this is 40 64cycle cores @ ~4ns...



 Embarrassed

i must say the development process is a disaster, i never want to do it again.

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September 10, 2012, 07:43:59 PM
 #323

I mast say that i am not an expert but it seems that there is a lot of room available to fill Wink Apart of the joke i have red somewhere that some of the guys do use "self made" tools to be able to achieve big density. The info was here if i remember correctly but link is dead
http://www.bitfury.org/xc6slx150.html

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September 10, 2012, 08:05:51 PM
 #324

I mast say that i am not an expert but it seems that there is a lot of room available to fill Wink Apart of the joke i have red somewhere that some of the guys do use "self made" tools to be able to achieve big density. The info was here if i remember correctly but link is dead
http://www.bitfury.org/xc6slx150.html


yeah we also write a lot of private tools, in order to help us fight with stupid XILINX tool chain.

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loshia
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September 10, 2012, 08:10:54 PM
 #325

I am sure that you  will do it! At the end whatever it costs it will worth it. Believe me. The feeling after job well done can not be replaced with anything else expect with well-well done Smiley
Just a side question - do you plan core (or cg miner) to be able auto adjust the clock watching the error rate? Will be some temps reading be available? and PWM fan control and speed monitoring.
I know that it is too much for a start (first version) but i am asking in general for future bitstream upgrades
10X

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flynn
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September 10, 2012, 10:01:50 PM
 #326

i must say the development process is a disaster, i never want to do it again.

Rofl - feeling your pain.

How do you build these nice graphs ?

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September 11, 2012, 03:21:14 AM
 #327

I mast say that i am not an expert but it seems that there is a lot of room available to fill Wink Apart of the joke i have red somewhere that some of the guys do use "self made" tools to be able to achieve big density. The info was here if i remember correctly but link is dead
http://www.bitfury.org/xc6slx150.html


yeah we also write a lot of private tools, in order to help us fight with stupid XILINX tool chain.

Sometimes I feel the FPGA development world could benefit massively from clean-slate-designed open source tools to do the logic synthesis, mapping, placement, routing, etc.

Right now, there is not much competition between Xilinx and Altera to improve their software tools, because the competition is mostly centered around the hardware capabilities of their chips, not the quality of the software stack.
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September 11, 2012, 06:30:12 AM
 #328

and this is 40 64cycle cores @ ~4ns...

Wait.

40x64 cycles cores @ 250Mhz = 20xfull hashers @250Mhz = 5GH/s per chip Huh

Who needs ASICs, really ... Smiley

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ngzhang
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September 11, 2012, 08:12:45 AM
 #329

and this is 40 64cycle cores @ ~4ns...

Wait.

40x64 cycles cores @ 250Mhz = 20xfull hashers @250Mhz = 5GH/s per chip Huh

Who needs ASICs, really ... Smiley

finally will be 80cores there, maybe 70+ at first.

speed = core amount / 64 * freq

but i think we will face same power issues when impact the high frequency. but i think 250MHs pre chip at first and 350MHs after carefully optimization is a optimistic estimate.

on XILINX -7 series, it will get a 30% better core density (means: use 30% less luts for a single core), and at least 50% frequency improve. means ~ 800-1G hash pre XC7A200T chip. this performance is close to a normal 0.11~0.13 um ASIC. the cost consist in sales volume.

I mast say that i am not an expert but it seems that there is a lot of room available to fill Wink Apart of the joke i have red somewhere that some of the guys do use "self made" tools to be able to achieve big density. The info was here if i remember correctly but link is dead
http://www.bitfury.org/xc6slx150.html


yeah we also write a lot of private tools, in order to help us fight with stupid XILINX tool chain.

Sometimes I feel the FPGA development world could benefit massively from clean-slate-designed open source tools to do the logic synthesis, mapping, placement, routing, etc.

Right now, there is not much competition between Xilinx and Altera to improve their software tools, because the competition is mostly centered around the hardware capabilities of their chips, not the quality of the software stack.


if you are a " VOL customer", XILINX will open more bottom layer information and give you more support. then you could implement wanted substructures.


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Dexter770221
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September 11, 2012, 09:25:48 AM
 #330

Wow, great job. Looks really dense Wink 64 cycle 2 stage core?

Under development Modular UPGRADEABLE Miner (MUM). Looking for investors.
Changing one PCB with screwdriver and you have brand new miner in hand... Plug&Play, scalable from one module to thousands.
ngzhang
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September 11, 2012, 09:49:40 AM
 #331

Wow, great job. Looks really dense Wink 64 cycle 2 stage core?

yeah, every 64cycle pre bitcoin hash.
 
present we must place the other half chip... the same work as the first half, but the stupid tool is getting stuck. nobody could imagine the difficulty unless they made similar work before.

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loshia
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September 11, 2012, 09:57:00 AM
 #332

Ngzang,

Is there any thing we can do to help you out? I mean to provide you some CPU power or other resource that you are missing?

Best

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flynn
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September 11, 2012, 12:19:16 PM
 #333

Ngzhang,

And about the power dissipation problems, did you consider inserting a Peltier module between the chips and the heatsink ?

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ngzhang
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September 11, 2012, 08:43:09 PM
 #334

Ngzang,

Is there any thing we can do to help you out? I mean to provide you some CPU power or other resource that you are missing?

Best



CPU power is not a big problem there.

Ngzhang,

And about the power dissipation problems, did you consider inserting a Peltier module between the chips and the heatsink ?

a semiconductor cooling chip will significantly improve the speed (if we finally implement the auto speed adjust feature), but will cause a huge energy consumption.

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ngzhang
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September 16, 2012, 05:20:49 PM
 #335



Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.

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flynn
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September 16, 2012, 05:36:15 PM
 #336

Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.

Thank you ngzhang. That means your developing fpga nightmare is over, right?

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September 16, 2012, 06:49:41 PM
 #337

Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.

I like ngzhang's style.

Cablez
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September 16, 2012, 08:43:47 PM
 #338

Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.

I like ngzhang's style.



Quoted just because of so much win!!!

Tired of substandard power distribution in your ASIC setup???   Chris' Custom Cablez will get you sorted out right!  No job too hard so PM me for a quote
Check my products or ask a question here: https://bitcointalk.org/index.php?topic=74397.0
luffy
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September 16, 2012, 09:05:55 PM
 #339



Next week will publish big news. not only about Lancelot, also include some other news.
if you have large amount of money, please pay more attention.
what are we looking at? exactly? :p
psilan
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September 17, 2012, 12:56:48 AM
 #340

What is a large amount of money? 100k?

dip
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