FPGA development board "Lancelot" - accept bitsteam developer's orders.

[ngzhang]

I wonder why not more people try to implement this obviously superior implementation (/me looks at the Cairnsmore1 devs...)

It appears to trigger slow convergence in the place and route phases. The unrolled implementation has the similar problem, but less bad.

It seems like the heuristics in the global optimization phases can't find an usable gradient which could be used to guide the optimizer. So it kind of wanders in a fog over the terrain consisting of small hills and shallow valleys.

yep, so we must use manually PAR. this really cost a LOT of man hour which is very very expensive.

PS:

i will check and answer personal messages after i finish the bitsteam work, unless you placed a developer order.

[1714240470]

1714240470

[ngzhang]

add order details and some new pictures.

for Chinese readers only:

目前只接受开发者订单，也就是说现在是没有bitsteam的。如果你没有bitsteam的开发能力，那么只能用icarus的bitsteam，或者用不起来。
每人最多一个。

[luffy]

this is great! any pictures from dev kit?

[disclaimer201]

If it can only mine btc, I don't see how it can still be profitable right now to be honest. Some of those Z-Tex boards have 128MB memory, so if I'd even switch to FPGA now, it would have to be at least LTC compatible. Look at some of the people with their Minirigs in the wild threads. Several guys already with 150+Gh/s Minirigs. Not even talking about Asics.

[wildemagic]

If it can only mine btc, I don't see how it can still be profitable right now to be honest. Some of those Z-Tex boards have 128MB memory, so if I'd even switch to FPGA now, it would have to be at least LTC compatible. Look at some of the people with their Minirigs in the wild threads. Several guys already with 150+Gh/s Minirigs. Not even talking about Asics.

@500mh/s you would make about $3 per day, using 25-30w of power costs about 10-15c per day.
How are you doing your calculations?

[luffy]

i think he is talking long term with asics on their way and dif goes sky high!
he could be right, fpgas should be able to be used for alt currencies also!

[disclaimer201]

If it can only mine btc, I don't see how it can still be profitable right now to be honest. Some of those Z-Tex boards have 128MB memory, so if I'd even switch to FPGA now, it would have to be at least LTC compatible. Look at some of the people with their Minirigs in the wild threads. Several guys already with 150+Gh/s Minirigs. Not even talking about Asics.

@500mh/s you would make about $3 per day, using 25-30w of power costs about 10-15c per day.
How are you doing your calculations?

I am making my calculations on the fact that BTC difficulty is skyrocketing for the past weeks already and continues to go up quickly. Furthermore, there are very few months left until the reward halves. So good luck paying off your FPGA at all, particularly when BFL delivers Asics at some point in the next 6 months which is rather likely. Next btc difficulty adjustment in a few days alone will decrease your 2.85$ income to . Even if difficulty stays at today's level, you will need 175 days to pay off one FPGA. And making an investment into FPGA right now isn't worthwhile if you can't make a profit with them in 2013. They will have zero resale value when difficulty doubles or quadruples. If I hadn't come across Litecoin, and if working Lancelots would have been actually available two months ago, I might have decided differently.

[Nemesis]

Definitely too late. PPL buy this for fun and experiment. But dont expect to have any bulk order.

[Energizer]

If it can only mine btc, I don't see how it can still be profitable right now to be honest. Some of those Z-Tex boards have 128MB memory, so if I'd even switch to FPGA now, it would have to be at least LTC compatible. Look at some of the people with their Minirigs in the wild threads. Several guys already with 150+Gh/s Minirigs. Not even talking about Asics.

@500mh/s you would make about $3 per day, using 25-30w of power costs about 10-15c per day.
How are you doing your calculations?

I am making my calculations on the fact that BTC difficulty is skyrocketing for the past weeks already and continues to go up quickly. Furthermore, there are very few months left until the reward halves. So good luck paying off your FPGA at all, particularly when BFL delivers Asics at some point in the next 6 months which is rather likely. Next btc difficulty adjustment in a few days alone will decrease your 2.85$ income to . Even if difficulty stays at today's level, you will need 175 days to pay off one FPGA. And making an investment into FPGA right now isn't worthwhile if you can't make a profit with them in 2013. They will have zero resale value when difficulty doubles or quadruples. If I hadn't come across Litecoin, and if working Lancelots would have been actually available two months ago, I might have decided differently.

You can check the countdown to 25 BTC per block reward here: http://serason.com/projects/emccharts/countdown.php

We are only 4 months away from 25 BTC block reward. Lancelot and Icarus wouldn't be of zero value in 2013, it will be evaluated as a dev-kit. So I suggest anyone buying lancelot to buy the complete div kit, to be able to sell it to developers "away from BTC mining market".

[luffy]

well don't be afraid of halving (25btc/block). the market has already started to pre-adjust btc's value and who knows the value at that day!
all systems go to equilibrium anyway

[loshia]

Gys's
What do you suggest? All of you know that starting something new is always risky and will always be.
Waiting for the asics? It is just a fiction...Watching bitcoin market and not investing anything? Just saying IF i bought i would...No sense. By GPU's? I do not have power plants and my electricity is not for free
It is just not serious. When reward becomes 25 BTC per block may be the price could be 20 USD per BTC:) OR it could be zero...So both of us will be F......d Gpu's FPGA Asics and every one else. What will be resel value of Fried GPU's when resell market is full of them if BTC collapses? So everyone should take its decision alone....I just do not see a point to spam the topic with BTC economics Asic stuff and all irreverent information. Let us concentrate on what we do have here. I see the situation in the flowing way:

1. Ngzhang and his team are good at what they do (both software and hardware) Let Icaurus owners confirm. Unfortunately i am not one of them
2. They are responsive and keep their promises
3. The prices are good compared to competitors
4. They are easy to communicate with

What else do we need?

Once again let us discuss here only lancelot related stuff please

No offense
I wish good luck to everybody and good profit also:)

[Energizer]

ngzhang've welcomed off topic subjects here long time ago! anyways, when will the new bitstream be available for Icarus? what are the procedures involved in the upgrade?

[2112]

I have non-mining questions:

1) You replaced Prolific PL2303HXD with FTDI FT232R, is that right?
2) Are all 8 DBUS pins from FT232R connected to the FPGA U1?
3) How about 5 CBUS pins? I see TXD1 and RXD1 LEDs so 2 are already used. Where are the remaining 3 connected? I'm hoping for RD# and WR# bit-bang strobes.
4) What is the number of connections between U1 and U2?
5) What is U3?
6) What is U9 and the HOT LED?
7) I see two Winbond chips U4 & U5. Are those SPI configuration memory?
Assume that FPGA is configured for loopback only and not for any work. Did you test that the FT232R works reliably at the full 3Mbps serial communication speed?

Thanks in advance.

[loshia]

ngzhang've welcomed off topic subjects here long time ago! anyways, when will the new bitstream be available for Icarus? what are the procedures involved in the upgrade?

Excise me...If off topic is welcomed please do take my apologies:)

[ngzhang]

I have non-mining questions:

1) You replaced Prolific PL2303HXD with FTDI FT232R, is that right?
2) Are all 8 DBUS pins from FT232R connected to the FPGA U1?
3) How about 5 CBUS pins? I see TXD1 and RXD1 LEDs so 2 are already used. Where are the remaining 3 connected? I'm hoping for RD# and WR# bit-bang strobes.
4) What is the number of connections between U1 and U2?
5) What is U3?
6) What is U9 and the HOT LED?
7) I see two Winbond chips U4 & U5. Are those SPI configuration memory?
Assume that FPGA is configured for loopback only and not for any work. Did you test that the FT232R works reliably at the full 3Mbps serial communication speed?

Thanks in advance.

short answer:
1, yes!
2, TXD,RXD,CTS,RTS
3,
4, clock buffer
6, TMP102 temperature sensor
7, yes
8, no.

 
sch and PCB design files will release to github this week.

[2112]

2, TXD,RXD,CTS,RTS
3, ? ? ?

sch and PCB design files will release to github this week.

"Oh boy!" for not connecting all available pins from the FT232R to the FPGA.

Any non-mining application would need more communication bandwidth. The easies way would be to route all 8 DBUS signals for parallel byte communication. Then the CBUS signals can be configured in EEPROM to expose the RD# & WR# strobe signals. It all works together to allow easy implementation of bit-bang I/O. And it is easy both on the host side software in the computer and easy on SLICE resources on the FPGA.

It is just 6 traces more, but the value of the board as a development kit increases immensely. The default 115200bps maximum speed in UART is a serious limitation for non-mining uses.

I'll wait for the schematic and constraint files to ask further questions.

I have some other development board with FTDI chip and I will write a quick loopback test software for Windows and a trivial loopback Xilinx project.

[ngzhang]

2, TXD,RXD,CTS,RTS
3, ? ? ?

sch and PCB design files will release to github this week.

"Oh boy!" for not connecting all available pins from the FT232R to the FPGA.

Any non-mining application would need more communication bandwidth. The easies way would be to route all 8 DBUS signals for parallel byte communication. Then the CBUS signals can be configured in EEPROM to expose the RD# & WR# strobe signals. It all works together to allow easy implementation of bit-bang I/O. And it is easy both on the host side software in the computer and easy on SLICE resources on the FPGA.

It is just 6 traces more, but the value of the board as a development kit increases immensely. The default 115200bps maximum speed in UART is a serious limitation for non-mining uses.

I'll wait for the schematic and constraint files to ask further questions.

I have some other development board with FTDI chip and I will write a quick loopback test software for Windows and a trivial loopback Xilinx project.

maybe after this project, when i have some free time. i will build a small FPGA(LX16 FT256) dev board with DDR2 RAM and FT232 connect as you describe and sell it at a ultra low price(50$) for learning.

[2112]

maybe after this project, when i have some free time. i will build a small FPGA(LX16 FT256) dev board with DDR2 RAM and FT232 connect as you describe and sell it at a ultra low price(50$) for learning.

As a dev board user I can tell you the following: market is full of single FPGA dev boards. The uniqueness and greatness of your designs (Icarus & Lancelot) lies in them being paired FPGAs with non-trivial interconnectivity. The only problem with them is that they have a bent straw instead of a pipe for the external communication.

I'm even thinking of getting a Lancelot and paying someone to rework the FT232R connections using additional 10 wires soldered to the unpopulated GPIO vias. But this is something above my manual skill and resources, and because of that it will have to wait.

If you ever find a need to do Lancelot v2 (like Icarus v2) then just please remember to route all the available signals from the comm chip to the FPGA.

And for your future designs please consider using the high-speed USB chips instead of full-speed USB and having one comm pipe per FPGA. So the Lancelot v5 would have FT2232H (dual high-speed USB). The market for the multi-FPGA boards its there already:

https://bitcointalk.org/index.php?topic=78239.msg973019#msg973019

I just realised that I have given such a pitch already years ago. I was an early advocate of dual Pentium (Classic) and dual Celeron (with SMP mod) motherboards. Those who listened were very well prepared for the arrival of multicore CPUs. Something similar will happen with FPGAs.

[Luke-Jr]

And please please set the iVendor/iProduct USB descriptors so miners can autodetect it sanely!

[2112]

And please please set the iVendor/iProduct USB descriptors so miners can autodetect it sanely!

I would recommend against that, unless some driver fairy can obtain a WHQL signature for the modified VID/PID. Trying to run with unsigned drivers under 64-bit Windows is an unnecessary hassle.

The market gained would be some open-source extremists. The market lost would be those who can't or wouldn't modify their Windows installations. Let the US-ians fight the monster from Redmond.