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Author Topic: FPGA development board "Lancelot" - accept bitsteam developer's orders.  (Read 95986 times)
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July 26, 2012, 02:35:38 PM
 #241

Don't worry, we're just interested in keeping updated. Thanks for letting us know what is going on. Hopefully when your guy gets back from the US you'll be set! I'm glad you're not taking preorders till you are ready.

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July 26, 2012, 04:21:45 PM
 #242

PS:

accept bitsteam developer orders form now.

So, I may order DEV KIT now? Do I need to email to you?

Under development Modular UPGRADEABLE Miner (MUM). Looking for investors.
Changing one PCB with screwdriver and you have brand new miner in hand... Plug&Play, scalable from one module to thousands.
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July 27, 2012, 03:45:10 AM
 #243

these days:
still very busy at multiple works. 70% is school work, and i put all my spare time on lancelot project. to 3~4:00AM everyday.

i work together with the software guys, now the new bitsteam is doing the optimization work. we must push it to 500-550MH/s.

hardware is ready 5 days ago.

At 250-275 Mh/s per FPGA, I presume you designed it using the "sea-of-tiny hashers" model, like bitfury did. If that's the case, good work! I wonder why not more people try to implement this obviously superior implementation (/me looks at the Cairnsmore1 devs...)
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July 27, 2012, 07:24:42 PM
 #244

I wonder why not more people try to implement this obviously superior implementation (/me looks at the Cairnsmore1 devs...)
It appears to trigger slow convergence in the place and route phases. The unrolled implementation has the similar problem, but less bad.

It seems like the heuristics in the global optimization phases can't find an usable gradient which could be used to guide the optimizer. So it kind of wanders in a fog over the terrain consisting of small hills and shallow valleys.

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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July 28, 2012, 04:08:58 AM
 #245

I wonder why not more people try to implement this obviously superior implementation (/me looks at the Cairnsmore1 devs...)
It appears to trigger slow convergence in the place and route phases. The unrolled implementation has the similar problem, but less bad.

It seems like the heuristics in the global optimization phases can't find an usable gradient which could be used to guide the optimizer. So it kind of wanders in a fog over the terrain consisting of small hills and shallow valleys.

yep, so we must use manually PAR. this really cost a LOT of man hour which is very very expensive.

PS:

i will check and answer personal messages after i finish the bitsteam work, unless you placed a developer order.

CEO of Canaan-creative, Founder of Avalon project.
https://canaan.io/
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August 05, 2012, 08:52:56 AM
 #246

add order details and some new pictures.

for Chinese readers only:

Quote
目前只接受开发者订单,也就是说现在是没有bitsteam的。如果你没有bitsteam的开发能力,那么只能用icarus的bitsteam,或者用不起来。
每人最多一个。

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August 05, 2012, 11:50:47 AM
 #247

this is great! any pictures from dev kit?
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August 05, 2012, 12:52:06 PM
 #248

If it can only mine btc, I don't see how it can still be profitable right now to be honest. Some of those Z-Tex boards have 128MB memory, so if I'd even switch to FPGA now, it would have to be at least LTC compatible. Look at some of the people with their Minirigs in the wild threads. Several guys already with 150+Gh/s Minirigs. Not even talking about Asics.

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August 05, 2012, 01:00:49 PM
 #249

If it can only mine btc, I don't see how it can still be profitable right now to be honest. Some of those Z-Tex boards have 128MB memory, so if I'd even switch to FPGA now, it would have to be at least LTC compatible. Look at some of the people with their Minirigs in the wild threads. Several guys already with 150+Gh/s Minirigs. Not even talking about Asics.

@500mh/s you would make about $3 per day, using 25-30w of power costs about 10-15c per day.
How are you doing your calculations?

.,-._|\     Offgrid 1.7kW Solar and 3G wireless internet powering my mining rig.
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\_,--.x/     [219.5btc of successful trades total] with : rastapool, miernik, flatronw & OneFixt
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August 05, 2012, 01:05:47 PM
 #250

i think he is talking long term with asics on their way and dif goes sky high!
he could be right, fpgas should be able to be used for alt currencies also!
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August 05, 2012, 01:17:47 PM
 #251

If it can only mine btc, I don't see how it can still be profitable right now to be honest. Some of those Z-Tex boards have 128MB memory, so if I'd even switch to FPGA now, it would have to be at least LTC compatible. Look at some of the people with their Minirigs in the wild threads. Several guys already with 150+Gh/s Minirigs. Not even talking about Asics.

@500mh/s you would make about $3 per day, using 25-30w of power costs about 10-15c per day.
How are you doing your calculations?

I am making my calculations on the fact that BTC difficulty is skyrocketing for the past weeks already and continues to go up quickly. Furthermore, there are very few months left until the reward halves. So good luck paying off your FPGA at all, particularly when BFL delivers Asics at some point in the next 6 months which is rather likely. Next btc difficulty adjustment in a few days alone will decrease your 2.85$ income to Huh. Even if difficulty stays at today's level, you will need 175 days to pay off one FPGA. And making an investment into FPGA right now isn't worthwhile if you can't make a profit with them in 2013. They will have zero resale value when difficulty doubles or quadruples. If I hadn't come across Litecoin, and if working Lancelots would have been actually available two months ago, I might have decided differently.

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August 05, 2012, 02:24:18 PM
 #252

Definitely too late. PPL buy this for fun and experiment. But dont expect to have any bulk order.

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August 05, 2012, 02:26:23 PM
 #253

If it can only mine btc, I don't see how it can still be profitable right now to be honest. Some of those Z-Tex boards have 128MB memory, so if I'd even switch to FPGA now, it would have to be at least LTC compatible. Look at some of the people with their Minirigs in the wild threads. Several guys already with 150+Gh/s Minirigs. Not even talking about Asics.

@500mh/s you would make about $3 per day, using 25-30w of power costs about 10-15c per day.
How are you doing your calculations?

I am making my calculations on the fact that BTC difficulty is skyrocketing for the past weeks already and continues to go up quickly. Furthermore, there are very few months left until the reward halves. So good luck paying off your FPGA at all, particularly when BFL delivers Asics at some point in the next 6 months which is rather likely. Next btc difficulty adjustment in a few days alone will decrease your 2.85$ income to Huh. Even if difficulty stays at today's level, you will need 175 days to pay off one FPGA. And making an investment into FPGA right now isn't worthwhile if you can't make a profit with them in 2013. They will have zero resale value when difficulty doubles or quadruples. If I hadn't come across Litecoin, and if working Lancelots would have been actually available two months ago, I might have decided differently.

You can check the countdown to 25 BTC per block reward here: http://serason.com/projects/emccharts/countdown.php

We are only 4 months away from 25 BTC block reward. Lancelot and Icarus wouldn't be of zero value in 2013, it will be evaluated as a dev-kit. So I suggest anyone buying lancelot to buy the complete div kit, to be able to sell it to developers "away from BTC mining market".
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August 05, 2012, 02:57:58 PM
 #254

well don't be afraid of halving (25btc/block). the market has already started to pre-adjust btc's value and who knows the value at that day!
all systems go to equilibrium anyway Wink
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August 05, 2012, 03:03:34 PM
 #255

Gys's
What do you suggest? All of you know that starting something new is always risky and will always be.
Waiting for the asics? It is just a fiction...Watching bitcoin market and not investing anything? Just saying IF i bought i would...No sense. By GPU's? I do not have power plants and my electricity is not for free
It is just not serious. When reward becomes 25 BTC per block may be the price could be 20 USD per BTC:) OR it could be zero...So both of us will be F......d Gpu's FPGA Asics and every one else. What will be resel value of Fried GPU's when resell market is full of them if BTC collapses? So everyone should take its decision alone....I just do not see a point to spam the topic with BTC economics Asic stuff and all irreverent information. Let us concentrate on what we do have here. I see the situation in the flowing way:

1. Ngzhang and his team are good at what they do (both software and hardware) Let Icaurus owners confirm. Unfortunately i am not one of them
2. They are responsive and keep their promises
3. The prices are good compared to competitors
4. They are easy to communicate with

What else do we need?

Once again let us discuss here only lancelot related stuff please

No offense
I wish good luck to everybody and good profit also:)



Please help the Led Boy aka Bicknellski to make us a nice Christmas led tree and pay WASP membership fee here:
https://bitcointalk.org/index.php?topic=643999.msg7191563#msg7191563
And remember Bicknellski is not collecting money from community;D
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August 05, 2012, 03:08:03 PM
 #256

ngzhang've welcomed off topic subjects here long time ago! anyways, when will the new bitstream be available for Icarus? what are the procedures involved in the upgrade?
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August 05, 2012, 03:38:09 PM
 #257

I have non-mining questions:

1) You replaced Prolific PL2303HXD with FTDI FT232R, is that right?
2) Are all 8 DBUS pins from FT232R connected to the FPGA U1?
3) How about 5 CBUS pins? I see TXD1 and RXD1 LEDs so 2 are already used. Where are the remaining 3 connected? I'm hoping for RD# and WR# bit-bang strobes.
4) What is the number of connections between U1 and U2?
5) What is U3?
6) What is U9 and the HOT LED?
7) I see two Winbond chips U4 & U5. Are those SPI configuration memory?
Cool Assume that FPGA is configured for loopback only and not for any work. Did you test that the FT232R works reliably at the full 3Mbps serial communication speed?

Thanks in advance.

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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August 05, 2012, 03:40:40 PM
 #258

ngzhang've welcomed off topic subjects here long time ago! anyways, when will the new bitstream be available for Icarus? what are the procedures involved in the upgrade?
Excise me...If off topic is welcomed please do take my apologies:)


Please help the Led Boy aka Bicknellski to make us a nice Christmas led tree and pay WASP membership fee here:
https://bitcointalk.org/index.php?topic=643999.msg7191563#msg7191563
And remember Bicknellski is not collecting money from community;D
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August 05, 2012, 03:47:47 PM
 #259

I have non-mining questions:

1) You replaced Prolific PL2303HXD with FTDI FT232R, is that right?
2) Are all 8 DBUS pins from FT232R connected to the FPGA U1?
3) How about 5 CBUS pins? I see TXD1 and RXD1 LEDs so 2 are already used. Where are the remaining 3 connected? I'm hoping for RD# and WR# bit-bang strobes.
4) What is the number of connections between U1 and U2?
5) What is U3?
6) What is U9 and the HOT LED?
7) I see two Winbond chips U4 & U5. Are those SPI configuration memory?
Cool Assume that FPGA is configured for loopback only and not for any work. Did you test that the FT232R works reliably at the full 3Mbps serial communication speed?

Thanks in advance.


short answer:
1, yes!
2, TXD,RXD,CTS,RTS
3, Huh
4, clock buffer
6, TMP102 temperature sensor
7, yes
8, no.

 
sch and PCB design files will release to github this week.

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Business contact: love@canaan.io
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August 05, 2012, 04:30:50 PM
 #260

2, TXD,RXD,CTS,RTS
3, ? ? ?

sch and PCB design files will release to github this week.
"Oh boy!" for not connecting all available pins from the FT232R to the FPGA.

Any non-mining application would need more communication bandwidth. The easies way would be to route all 8 DBUS signals for parallel byte communication. Then the CBUS signals can be configured in EEPROM to expose the RD# & WR# strobe signals. It all works together to allow easy implementation of bit-bang I/O. And it is easy both on the host side software in the computer and easy on SLICE resources on the FPGA.

It is just 6 traces more, but the value of the board as a development kit increases immensely. The default 115200bps maximum speed in UART is a serious limitation for non-mining uses.

I'll wait for the schematic and constraint files to ask further questions.

I have some other development board with FTDI chip and I will write a quick loopback test software for Windows and a trivial loopback Xilinx project.

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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