Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)

[hagenees]

Can anybody help to compile miner for ztex-1.11 board, I have no ideas how to make it.

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[asjfdlksfd]

I uploaded the custom MBPM module, which is compatible with the current KC705 mining code, here:
https://mega.co.nz/#!Oh5HTDRB!C0RLYW4yZN8gbg38FfgLpzmKFcseOql3Xx1i_gXTfdM

I have a problem to download from sh... mega .
I cannot allready find the module on github. Is there another source?

Cheers..

[senseless]

I have a problem to download from sh... mega .
I cannot allready find the module on github. Is there another source?

Cheers..

Posted it for you

https://github.com/senseless/Modular-Python-Bitcoin-Miner/tree/testing/modules/fpgamining

[xbaby]

the 300MHz result was just compiled with no timing error. in next few days, I'll program it on board to see if it could really run perfectly.

some update on the latest progress:

    I must say the 300MHz result was achieved with no clock pin constrained. after bind the clock pin to real pin location (and I use a 25MHz crystal), It's very hard to meet above timing parameter. the best result I've achieved is 275MHz by now. a little bit strange.

    And, to make my xc6vlx130t board actually work with a mining pool, I finished some hard work. the jtag_comm.v jtag / host communication code has some issue on Virtex6 BSCAN engine, and I've made a patch for it. currently, the board can work perfectly using the MPBM host software, with hash rate about 280MH/s, and about 11w wall power usage for 1 pcs lx130t FPGA chip.

[blackarrow]

Hi!

My company, Black Arrow Limited is taking Bitcoin mining very seriously. We are currently producing Lancelot boards and have the facilities and experience to manufacture them at the best possible price and the experience to commercialize them.

We want to make faster and cheaper hardware for crypto-currencies.

At the moment we're looking into developing a more efficient (per $) FPGA hashing board than Lancelot (Spartan 6). We are also trying to build a team of FPGA engineers to make this happen.

I see that there are a lot of talented FPGA engineers so if you are interested in joining us, please PM me with your CV or work.

[razorfishsl]

Hi!

My company, Black Arrow Limited is taking Bitcoin mining very seriously. We are currently producing Lancelot boards and have the facilities and experience to manufacture them at the best possible price and the experience to commercialize them.

We want to make faster and cheaper hardware for crypto-currencies.

At the moment we're looking into developing a more efficient (per $) FPGA hashing board than Lancelot (Spartan 6). We are also trying to build a team of FPGA engineers to make this happen.

I see that there are a lot of talented FPGA engineers so if you are interested in joining us, please PM me with your CV or work.

I think you need to do WAY more research... at >2GH/s pay back is currently $10USD a day putting even the cheapest FPGA at several hundred days for ROI.

The issue is NOT VHDL or 'engineering'  but rather the base cost Vrs return on the FPGA.
Absolutely the CHEAPEST way to do FPGA mining is by buying EBAY scrap, but even that is a declining 30days ROI. Putting me safely in the goldilox zone of 100 days.

Even your own Lancelot >4 months before ROI, plus you are talking a DELAY of 2 MONTHS before you can deliver this....
Which makes your ROI 6 months.......

[goxed]

I've been asked a few times about a mining script for the current KC705 firmware.  I wrote a plugin for Modular Python Bitcoin Miner.  Here's the message I sent to someone about it:

I uploaded the custom MBPM module, which is compatible with the current KC705 mining code, here:
https://mega.co.nz/#!Oh5HTDRB!C0RLYW4yZN8gbg38FfgLpzmKFcseOql3Xx1i_gXTfdM

You'll want to download a copy of MPBM's testing branch.  Then extract the above archive into
Code:
modules/fpgamining
such that you end up with:

Code:
modules/fpgamining/kc705_uart/__init__.py
modules/fpgamining/kc705_uart/kc705uartworker.py

Once you start MPBM, you can now add a KC705 Worker by openning up the MPBM web-interface (http://127.0.0.1:8832) and clicking the "Workers" button on the left.  On Windows, I ran MPBM under Cygwin, and the "Port" ended up being /dev/com2 for me.  The Baudrate is 115200.

~fpgaminer

I haven't had a chance to clean it up and put it on the repo yet.

+1

Okay here are the steps for Windows environment that I followed

a) Compile / Implement / Generate bitstream for KC705 board using Xilinx Vivado tool.

b) use iMpact to download the bitstream to 7k325

c) Install cygwin

d) Install python using cygwin installer (setup.exe)

e) download pyserial and install pyserial with python running inside Cygwin

e.1) make sure your kc705 serial port is COM1

f) download MPBM, and add the kc705 uart source in the recommended directories

g) run MPBM

h) create new Kc705 uart worker

i) mine!

[dexX7]

Sorry to hijack this thread with my noobish question, but could someone tell me roughly how many basic logic units (no adders for example) are used here? Thanks and great project!

[asjfdlksfd]

Hi,

I've used the KC705 design for the AVNet MMP KC7T325 to get an running bitstream today.
I've both, the KC705 and the AVNet MMP http://www.em.avnet.com/en-us/design/drc/Pages/Mini-Module-Plus-Development-Kit-Supporting-the-Kintex-7-FPGA-Family.aspx.

I've bougth to of the modules for only 600 € per board which is an good price, but it is not so fast as the KC705.
It will produce after a couple of time much more invalid shares although the temp is nearby the same as by the KC705.

The code itself looks like mostly compatible but only the kc705_pins.xdc has been changed to:

Code:

set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_p}]
set_property IOSTANDARD LVDS [get_ports {sys_clk_p}]
set_property LOC AA10 [get_ports {sys_clk_p}]

set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_n}]
set_property IOSTANDARD LVDS [get_ports {sys_clk_n}]
set_property LOC AB10 [get_ports {sys_clk_n}]

set_property IOSTANDARD LVCMOS25 [get_ports {uart_rx}]
set_property LOC U22 [get_ports {uart_rx}]
set_property IOSTANDARD LVCMOS25 [get_ports {uart_tx}]
set_property LOC V22 [get_ports {uart_tx}]

I couldn't find an design for that modules for vivado so I used as target design simple xc7k325tffg676-1 which I guessed is soldered.

Generally also the code is working on cheap AVNet MMP, too, but not with the effency at 400 MHz. I think it should been decrease by a small value but I've not the experience to do that at the moment with the given hashing clock multiplier.

My last question: I saw that there is already an design finished wich use only less than the half of DSPs so two of the rings could been implemented instead of one, so the mining is doubled?

Cheers...

[goxed]

Hi,

I've used the KC705 design for the AVNet MMP KC7T325 to get an running bitstream today.
I've both, the KC705 and the AVNet MMP http://www.em.avnet.com/en-us/design/drc/Pages/Mini-Module-Plus-Development-Kit-Supporting-the-Kintex-7-FPGA-Family.aspx.

I've bougth to of the modules for only 600 € per board which is an good price, but it is not so fast as the KC705.
It will produce after a couple of time much more invalid shares although the temp is nearby the same as by the KC705.

The code itself looks like mostly compatible but only the kc705_pins.xdc has been changed to:

Code:

set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_p}]
set_property IOSTANDARD LVDS [get_ports {sys_clk_p}]
set_property LOC AA10 [get_ports {sys_clk_p}]

set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_n}]
set_property IOSTANDARD LVDS [get_ports {sys_clk_n}]
set_property LOC AB10 [get_ports {sys_clk_n}]

set_property IOSTANDARD LVCMOS25 [get_ports {uart_rx}]
set_property LOC U22 [get_ports {uart_rx}]
set_property IOSTANDARD LVCMOS25 [get_ports {uart_tx}]
set_property LOC V22 [get_ports {uart_tx}]

I couldn't find an design for that modules for vivado so I used as target design simple xc7k325tffg676-1 which I guessed is soldered.

Generally also the code is working on cheap AVNet MMP, too, but not with the effency at 400 MHz. I think it should been decrease by a small value but I've not the experience to do that at the moment with the given hashing clock multiplier.

My last question: I saw that there is already an design finished wich use only less than the half of DSPs so two of the rings could been implemented instead of one, so the mining is doubled?

Cheers...

I think the problem is that Avnet MMP uses -1 speed grade FPGA while KC705 uses -2 speed grade. Try to configure the clock generator for lower clock speeds for hash_clock down from 400MH to  375MHz, 350MHz, etc.

[goxed]

BTW, can the Minimodule plus work without the baseboard or is the baseboard required to make the MMP work?

[gingernuts]

BTW, can the Minimodule plus work without the baseboard or is the baseboard required to make the MMP work?

It needs some sort of baseboard to supply it with the 8 different power supply voltages it wants - Avnet seem to want $500 for the baseboard and $300 for the PSU board, so it might be worth the effort of designing your own, especially as the MMP FPGA board seems to sell below the cost of a 7k325 FPGA, and seems to come with a license file to unlock the 7k325 device in the Xilinx tools!

The MMP board does look interesting, but it seems to only have 10A 1.0v core supply - can someone please tell me what the current KC705 design is using at 400MH/s?

[asjfdlksfd]

BTW, can the Minimodule plus work without the baseboard or is the baseboard required to make the MMP work?

You need the power for the module and a connection.
If you implement an core for the attached usb plug or the ethernet interface on the MMP board possible you can use the communication over there so only power is needed.
So only jtag communication is additionally needed which looks like been possible only via the baseboard plugs.
The easiest is to use the baseboard + power module. But if you can lead an cheaper own delevoped base board it should been relative easy to create an power distribution board for the needed core and io voltage also, but I'm unsure which all voltages are needed.
The're pdc supports 1.0V 1.2V 1.8V 2.0V 2.5V and 3.3V but not all should been needed.
Jtag could been implement with an standard digilent JTAG-SMT-1 board USB board es well (est. 50$) which avnet and xilinx uses, too.
(needs 2.5V + 3.3V)
usb-uart should been possible over baseboard for easy access via SLL CP2102-GM (avnets chip) or cp2103 (kc705 chip). Power could been come only best from usb port for that chip.

Avnet have all the manuals and sheets available for registred customers here:
http://www.em.avnet.com/en-us/design/drc/pages/supportanddownloads.aspx?RelatedId=605
I'm sorry that I cannot give a direct copy.

If you are interested in one of my MMP modules send an pm.

[asjfdlksfd]

It needs some sort of baseboard to supply it with the 8 different power supply voltages it wants - Avnet seem to want $500 for the baseboard and $300 for the PSU board, so it might be worth the effort of designing your own, especially as the MMP FPGA board seems to sell below the cost of a 7k325 FPGA, and seems to come with a license file to unlock the 7k325 device in the Xilinx tools!

Yea, the license + the complete board could been a good base for an multi mmp baseboard in the way the mmq did.
The costs of the simple chips + bb design for e.g. an up to 4 (or plug board looks not so strange.
The board comes with some external memory so it could been possible to program them as ltc miner, too, but this is only an idea.
To use power modules for core and more it could been possible to use the D12F200A modules which generate 0.8 to 5 V at 40 A which should been enough for 2-3 mmp.
For the DDR and VCAUX possible only one voltage is needed. Which of them I will check later.

[kingcoin]

I've been getting a lot of these errors lately:

Code:

[05/22/2013 04:08:33] ERROR: Unable to getwork. Reason: can't read "state(status)": no such variable

Is this a common/known problem?

[kramble]

I've been getting a lot of these errors lately:

Code:

[05/22/2013 04:08:33] ERROR: Unable to getwork. Reason: can't read "state(status)": no such variable

Is this a common/known problem?

The getwork is timing out (probably the pool server is not responding). It happened a lot with BtCGuild when it was under DDOS attack.  I changed to using a stratum proxy server which is much more stable. Just install the proxy from https://github.com/slush0/stratum-mining-proxy , configure it to point to your preferred pool and start it up. Then (assuming you're using the mine.tcl script) set the config.tcl to connect to localhost:8332 (leave the login details the same as the proxy just passes them through to the pool).

[EDIT] Oops. I just saw your other post at https://bitcointalk.org/index.php?topic=212246.0 so it looks like you're on to this already. Anyway slush's proxy is pretty easy to set up (I'm using it on raspberry-pi linux).
Mark

[goxed]

BTW, can the Minimodule plus work without the baseboard or is the baseboard required to make the MMP work?

It needs some sort of baseboard to supply it with the 8 different power supply voltages it wants - Avnet seem to want $500 for the baseboard and $300 for the PSU board, so it might be worth the effort of designing your own, especially as the MMP FPGA board seems to sell below the cost of a 7k325 FPGA, and seems to come with a license file to unlock the 7k325 device in the Xilinx tools!

The MMP board does look interesting, but it seems to only have 10A 1.0v core supply - can someone please tell me what the current KC705 design is using at 400MH/s?

Xilinx vivado estimates the power draw of the 7K325 Chip is ~11W. It's infact hashing at 500MH/s right now with minor modification to the code. The VCCInt power module is getting a bit hot for my liking at 500MH/s. IMO the voltage reg chips on that module need heatsinks.

[gingernuts]

BTW, can the Minimodule plus work without the baseboard or is the baseboard required to make the MMP work?

It needs some sort of baseboard to supply it with the 8 different power supply voltages it wants - Avnet seem to want $500 for the baseboard and $300 for the PSU board, so it might be worth the effort of designing your own, especially as the MMP FPGA board seems to sell below the cost of a 7k325 FPGA, and seems to come with a license file to unlock the 7k325 device in the Xilinx tools!

The MMP board does look interesting, but it seems to only have 10A 1.0v core supply - can someone please tell me what the current KC705 design is using at 400MH/s?

Xilinx vivado estimates the power draw of the 7K325 Chip is ~11W. It's infact hashing at 500MH/s right now with minor modification to the code. The VCCInt power module is getting a bit hot for my liking at 500MH/s. IMO the voltage reg chips on that module need heatsinks.

Thanks for that - according to the manual the MMP power board only has 6A of VCCINT - which at 1.0v is just 6W - have you got a fan you can point at the regulator chips?

[goxed]

BTW, can the Minimodule plus work without the baseboard or is the baseboard required to make the MMP work?

It needs some sort of baseboard to supply it with the 8 different power supply voltages it wants - Avnet seem to want $500 for the baseboard and $300 for the PSU board, so it might be worth the effort of designing your own, especially as the MMP FPGA board seems to sell below the cost of a 7k325 FPGA, and seems to come with a license file to unlock the 7k325 device in the Xilinx tools!

The MMP board does look interesting, but it seems to only have 10A 1.0v core supply - can someone please tell me what the current KC705 design is using at 400MH/s?

Xilinx vivado estimates the power draw of the 7K325 Chip is ~11W. It's infact hashing at 500MH/s right now with minor modification to the code. The VCCInt power module is getting a bit hot for my liking at 500MH/s. IMO the voltage reg chips on that module need heatsinks.

Thanks for that - according to the manual the MMP power board only has 6A of VCCINT - which at 1.0v is just 6W - have you got a fan you can point at the regulator chips?

So I am using the KC705 board, it's got a 1.0V @ 20A Vccint regulator. The chips are so small (smaller than my smallest thumbnails ) , that it's very difficult to affix a heatsink w/o shorting something. Any ideas would be appreciated. Right now I have placed the board next to the airconditioner.

[hagenees]

Sorry, I repeat my question: can somebody help me to run minert on ztex fpga board 1.11?