Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)

[O_Shovah]

Hello everybody

As i am reentering this topic afther some years i would like to as some questions:

I would like to know if the Spartan 3 series with 1000 gates is capable of running this fpga Miner software?

As magik allready tested it seems to me that the xilinx chips need a very different code structure. In wich way there would be modification nescesary?

I would like to know in wich way the LE's of Altera are comparable to the gates of Xilinx?

Were may i get basic literature about the laguages you use in this development ? ( last time i programmed such devices we allways used assembler code)


I hope i may contribute something to this very interesting project even with my rusty an humble knowledge 

[1714055521]

1714055521

[1714055521]

1714055521

[teknohog]

I would like to know if the Spartan 3 series with 1000 gates is capable of running this fpga Miner software?

As magik allready tested it seems to me that the xilinx chips need a very different code structure. In wich way there would be modification nescesary?

I ported the original FPGA miner to a Spartan 3E with 500K gates, so if you mean 1000K gates, it is certainly possible. The original was tied to Altera chips, here is my version for Xilinx with serial port communications:

https://github.com/teknohog/Xilinx-Serial-Miner

I had to keep the parameter LOOP_LOG2 at 5 for minimum unrolling, and I get 3 Mhash/s at 100 MHz. With bigger chips you should be able to decrease this for more unrolling and better hashrates.

However, a general issue with Xilinx seems to be that these designs need a lot of routing, so you run out of wires when trying to use all of the gates. Altera seems better in this respect.

Some of the others seem to be working on these issues with different designs. I have not yet touched the actual hashing code, I merely did the minimum to get this running on a Spartan.

[OrphanedGland]

Hi all,

I finally joined today to participate in this development. I am an experienced ASIC designer turned game programmer. I just started looking at the source code, hopefully will be contributing to the improvement of the core soon.

Question to others, have you considered pooling together to tape out an ASIC? A TSMC shuttle wouldn't cost 1 million. I can do the ASIC, but I lack the PCB board design knowledge. I can do it, but it'll probably have a short somewhere.

___________________________________________________________
Donate to me at: 1PNkxttFgUzvaMjmnzEU5dbviSiv9qkHBp

I have done some VLSI development, but it was full custom (ie hand-drawn layout using magic, rather than place and route RTL / standard cells).  We used MOSIS (www.mosis.com) which does "multi-project wafer runs" to keep costs down.  Back in 2001 we got a chip made using a 0.18um TSMC CMOS process.  Ended up costing around $50k for 50 chips, although not all of them were packaged.  The RTL used on this FPGA project could be used by yourself as a starting point to produce an ASIC design.  I would then recommend looking into optimizing the adder structures making use of CSA and CLA techniques.  Then some decisions need to be made about the external I/O.

[kokjo]

maybe the guys talking about ASIC should start a new thread about ASIC mining.
no offence. but the thread is about FPGA mining. i really like guys who haves bit idea for bitcoin mining, but you are getting offtopic now.

[FallingEdge]

to TheSeven
Thank's for this implementation.
I get your project from https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/0a9077e5c070e0a601981c6ec42dfc946fe3ccd6/projects/VHDL_Xilinx_Port
VHDL synthesized well, but an error got when run miner.py:

Code:

root@debian:/home/user2/d# python miner.py
Traceback (most recent call last):
  File "miner.py", line 478, in <module>
    curses.wrapper(miner.run)
  File "/usr/local/lib/python2.7/curses/wrapper.py", line 43, in wrapper
    return func(stdscr, *args, **kwds)
  File "miner.py", line 380, in run
    self.showstats()
  File "miner.py", line 290, in showstats
    self.statuswin.vline(4, x, curses.ACS_VLINE, my - 5)
_curses.error: wmove() returned ERR

What it means?
I run it on Debian 6.0, Python 2.7.2

 

[kokjo]

to TheSeven
Thank's for this implementation.
I get your project from https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/0a9077e5c070e0a601981c6ec42dfc946fe3ccd6/projects/VHDL_Xilinx_Port
VHDL synthesized well, but an error got when run miner.py:

Code:

root@debian:/home/user2/d# python miner.py
Traceback (most recent call last):
  File "miner.py", line 478, in <module>
    curses.wrapper(miner.run)
  File "/usr/local/lib/python2.7/curses/wrapper.py", line 43, in wrapper
    return func(stdscr, *args, **kwds)
  File "miner.py", line 380, in run
    self.showstats()
  File "miner.py", line 290, in showstats
    self.statuswin.vline(4, x, curses.ACS_VLINE, my - 5)
_curses.error: wmove() returned ERR

What it means?
I run it on Debian 6.0, Python 2.7.2

 

it has some thing to do with curses.
try a different terminal maybe, i don't know.

[Freakin]

How would something like a Papilio stack up to the cards being used in this thread?
http://papilio.cc/

Is it laughably underpowered?

Looks like it's a Spartan 3E chip on board, but it appears to be a cheap stripped down FPGA

[O_Shovah]

So if i would compare a Altera Cyclon III with 55k macrocells

 http://de.farnell.com/altera/ep3c55u484c7n/fpga-cyclone-iii-55k-le-484ubga/dp/1742170

to a Xilinx Spartan 3 with roughly 53k macrocells

 http://de.farnell.com/xilinx/xc3sd3400a-4csg484i/fpga-spartan-3a-dsp-484csbga/dp/1876218

The Xilinx would be a lot slower than the altera due to the routing problem using the current code altough they both have almost the same number of Elements.

Or am i mistaken here ?

Has anyone tested one or both of this chips and may supply Mh/s or similiar data for performance comparison ?

Itmight be interesting if the lower performance of the xilinx chips is caught up by theri lower prices.


The other thing is : How do the chips of the different families differ if they have the same number of elements  eg between cyclone III  and IV ?

[TheSeven]

to TheSeven
Thank's for this implementation.
I get your project from https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner/tree/0a9077e5c070e0a601981c6ec42dfc946fe3ccd6/projects/VHDL_Xilinx_Port
VHDL synthesized well, but an error got when run miner.py:

Code:

root@debian:/home/user2/d# python miner.py
Traceback (most recent call last):
  File "miner.py", line 478, in <module>
    curses.wrapper(miner.run)
  File "/usr/local/lib/python2.7/curses/wrapper.py", line 43, in wrapper
    return func(stdscr, *args, **kwds)
  File "miner.py", line 380, in run
    self.showstats()
  File "miner.py", line 290, in showstats
    self.statuswin.vline(4, x, curses.ACS_VLINE, my - 5)
_curses.error: wmove() returned ERR

What it means?
I run it on Debian 6.0, Python 2.7.2

 

it has some thing to do with curses.
try a different terminal maybe, i don't know.

Yes, it's a curses error, most likely being caused by the terminal window being too small to draw the summary box at the top.
Depending on the length of your pool names the current version will need around 120 chars of width, the older one in the git repository maybe a bit less.

[FallingEdge]

Yes, it's a curses error, most likely being caused by the terminal window being too small to draw the summary box at the top.

You're right, I increase terminal window size and now it work.

Depending on the length of your pool names the current version will need around 120 chars of width, the older one in the git repository maybe a bit less.

What is a current version? This?   http://dl.dropbox.com/u/23683845/pyfpgaminer-0.0.1.zip

[TheSeven]

What is a current version? This?   http://dl.dropbox.com/u/23683845/pyfpgaminer-0.0.1.zip

http://dl.dropbox.com/u/23683845/pyfpgaminer-0.0.3.zip

[FallingEdge]

http://dl.dropbox.com/u/23683845/pyfpgaminer-0.0.3.zip

Thanks, it work fine,
but i get only  6.253394 MH/s 

My  FPGA is Virtex IIPro XC2VP50 and project settings are:
  miner clock frequency = 50 MHz
  DEPTH = 3

In your opinion, is  6 MH/s correct value for this project settings?
or did I do something wrong?

[lame.duck]

Yes, this values should be correct, i get with LOOP=3

8   MHash/s @ 65 MHz on a EP2C35C8    (Fmax=63 MHz)         
14 MHash/s @ 85 MHz on a EP3C25C6

both with the original code from fpgaminer

[TheSeven]

http://dl.dropbox.com/u/23683845/pyfpgaminer-0.0.3.zip

Thanks, it work fine,
but i get only  6.253394 MH/s 

My  FPGA is Virtex IIPro XC2VP50 and project settings are:
  miner clock frequency = 50 MHz
  DEPTH = 3

In your opinion, is  6 MH/s correct value for this project settings?
or did I do something wrong?

DEPTH = 3 means 2^3 = 8 pipeline stages for the 64 SHA256 rounds, so each nonce will take 64 / 8 = 8 clock cycles. At 50 MHz that's 50 / 8 = 6.25 MH/s.

[O_Shovah]

I ve been looking for another developement board and got interested in this one xilinx Spartan 6

http://shop.trenz-electronic.de/catalog/product_info.php?products_id=830

As i asume the LE's of altera and xilinx to be equivalent this should be abled to run the xilinx version of teknohog an full scale or are there any other limitations than routing ?

If nobody has objections ,i will order it and be ready to help improving the code after my exams in august.

[lame.duck]

Why not just download the ISE from webpack and doing some dry runs on the code? The software will tell you the device utilisation and the expectable performance numbers and the functionl correctness can be tested before.

For mining there could with the current code base some better suited boards, but this can change with better designs.

[makomk]

I ve been looking for another developement board and got interested in this one xilinx Spartan 6

http://shop.trenz-electronic.de/catalog/product_info.php?products_id=830

As i asume the LE's of altera and xilinx to be equivalent this should be abled to run the xilinx version of teknohog an full scale or are there any other limitations than routing ?

They're not even remotely equivalent for the Spartan 6 series. The good news is that Spartan-6's LUTs are 6-input rather than 4-input, and that registers aren't as closely tied to LUTs which means you don't waste as many LUTs. The bad news is that the number of actual 6-LUTs is only 2/3rds of the number of equivalent "logic cells" they advertise, and of those only half have the carry chains required to use them as adders, and I don't think they can calculate more than a single bit of an addition per LUT (unlike the ALEs on Altera's recent Stratix FPGAs), and they lack the small local-ish RAM blocks that are used as shift registers on the Cyclone IV.

Basically, you're going to have fun fitting the design into anything smaller than the XC6SLX100, and unfortunately FPGAs that big aren't supported by Xilinx's free WebPack tools. The number of LUTs and registers might look like it'll fit with some cramming on the LX75, but you'll be constrained by the number of adders required. As for the LX45 - no chance as far as I can see, not even close to enough LUTs.

[O_Shovah]

Thank you both for your advice.

I've downloaded the ISE and am going to try am few dry runs for this chip.

If this chip isn't worth the effort wich board would you recommend for less than 300 Euro including maybe a reduction for students ?
(Beside the DE-115 already shown)

I remember fpgaminer to have reported he started testing on an Spartan 6 board.His results would be interesting.

[sjohn]

thanks for all your hard work so far, is there anyway you could have a sof file preconfigured at 80Mh/s for my de2-115?

[fpgaminer]

thanks for all your hard work so far, is there anyway you could have a sof file preconfigured at 80Mh/s for my de2-115?

You are most welcome Do you have appropriate cooling on your DE2-115? 80MHz on the DE2-115 will damage your FPGA without proper cooling, and will also fail to generate correct shares.

I can make a SOF regardless and let you know the cooling requirements, but I want to make sure you are fully aware of the dangers (like the loss of $600 when your FPGA dies from heat).