Butterfly Labs - Bitforce Single and Mini Rig Box

[steamboat]

Has anyone else noticed how the heatpipe cooler on the rev3 doesn't really cover the second FPGA? It is short by about 5cm. The center of the chip is covered but one whole side is left open.

I noticed this also. If this heatpipe is really custom made the job wasn't done good.

I'm thinking about putting a metal plate between the FPGA's and the heatpipe. This metal plate should cover the full area of both FPGA's and transfer it to the heatpipe. Maybe this could improve the cooling which is obviously mainly limited by the only parted covered FPGA.

Has someone already done this?

Adding any additional substance will only increase thermal resistance and makes cooling less efficient.
The aluminium plate which the heatsink sits on, is a by itself a heat-spreader directly attached to the die inside.


Regards,
BF Labs Inc.

I would agree here, don't add anything extra or your temps will just go up.

The heatsink itself could be better for sure, the aluminum part could be solid copper for start; and I noticed it is slightly short as well, however the copper pipes seem to touch the surface of the chip where the aluminum part cuts off, so that's something I suppose.

Again...  to clarify...   (trying to save unnecessary efforts among users), the chip itself is smaller than the aluminum heat spreader you see.  There is no purpose in trying to extend the heatsink out to the edge of the heat spreader because there is no heat being generated under the edge...  There is only air there.  See picture above for visual reference.

From a technical perspective, I beg to disagree.

There's a thermal resistance RT1 from the die to the heat spreader, and a thermal resistance RT2 from the heat spreader to the cooler. While RT1 cannot be changed, it is a good thing to minimize RT2. One way of minimizing RT2 is by removing the heat from the whole area of the heat spreader.

If you could choose full or partial coverage of the overhang...  certainly full would be an easy choice.  I'm just pointing out that the practical value of doing so in this case is nil.   This is the result of our thermal simulations in designing the heatsink.  The reason the few mm on the edge of the spreader are left uncovered is for package fitting.  

I understand the reasoning behind fitting the heatsink inside the case, but I must disagree with it not having a significant value. Mining is all about min/maxing. the heatsink could have quite easily extended the .25 inch (i'm guessing based on this picture) to gain the extra dissipation. The design of the enclosure for the single is absolutely terrible for dissipating heat, causing the fan to work harder to get less airflow. As far as the hack job you have done sanding the chip, here's an article from 1999 explaining what should be common sense.

 I like the singles, and I like what i've seen of the rig box, you guys have done a decent job at creating a product that fills a need in the market cheaply. That being said, your thermal solutions have been quite terrible/sloppy , and all the designs for the rig box are showing signs of the same backwards logic. I understand every startup company has growing pains, and i don't expect you to get everything right the first time, but please stop making excuses for poor designs and start fixing them.

I think it's important to point out once again that there is *NO* chip under the edge of the heat spreader.  The heat transfer capability from actual chip to heat sink via that area of heat spreader overhang is fantastically insignificant.  IE - it makes no practical difference to the thermal efficiency of the heatsink.  Suggesting otherwise, or promoting the idea that this is a cause of throttling isn't helpful to any user of the product.  I'm not pointing this out to win an argument.  I'm trying to save customers from confusion, misunderstanding and waste of effort.  Each of the chips have their own throttling point.  If you are working to improve the efficiency of any given unit, focusing on this area is akin to a snipe hunt or worse...  it could create heat problems such as the suggested metal plate insertion to try and extend coverage to this area. 

With regards to the 'sanding', extreme care was taken on the run of chips which had that treatment.  It was done with plastic abrasion and full vacuum draw.  90% of the chips shipped have no 'sanding' at all and are free of any marking.

I am not suggesting people should add another heatsink layer to cover the exposed edge of the plate. I am suggesting it would have been easy in the design of the heatsink to extend it to cover the entire surface area, and disagreeing with the reasoning behind not doing it of "it doesn't matter, the loss is minimal". The entire thought process behind a heat SPREADER is to make it easier to dissipate the heat by SPREADING it over a larger area. not covering the added area of the heat SPREADER effectively negates the purpose of putting one on in the first place.

As far as sanding goes, you are mixing up two posts. in regards to how it was done, I was cautioning end users to avoid getting metal dust all over the PCB to avoid shorts. I did not suggest you had not taken the necessary precautions. what I DID say is your sand job is horrible.

DOES NOT EQUAL .

Had you taken the time to run through the grits after sanding the chip, it is quite possible, neigh probable, the singles would not be having such bad throttling issues.

Other fpga manufacturers are not having throttling issues. Whether that is because they aren't utilizing the chips as well as you are, or because your thermal designs are terrible, is debatable. What isn't debatable is years of research in which techniques provide the best cooling for a chip, regardless of whether it's a cpu, gpu, fpga, or asic.

As i stated before, I do like your company and i do appreciate what you're trying to do. What I don't like is the excuses you are giving regarding blatant design flaws. It will be interesting to see what the final mini-rig product looks like and whether or not you've learned from mistakes you've made with the singles.

[rjk]

Had you taken the time to run through the grits after sanding the chip, it is quite possible, neigh probable, the singles would not be having such bad throttling issues.

If you've done any recent research, most of the "mirror finish" stuff has been debunked, seriously.

Other fpga manufacturers are not having throttling issues. Whether that is because they aren't utilizing the chips as well as you are, or because your thermal designs are terrible, is debatable. What isn't debatable is years of research in which techniques provide the best cooling for a chip, regardless of whether it's a cpu, gpu, fpga, or asic.

Umm.. they get plenty of "throttling", if they turn the speed up to insane levels. Technically it is just increased error rates, which indicates a need to reduce the speed to compensate.

As i stated before, I do like your company and i do appreciate what you're trying to do. What I don't like is the excuses you are giving regarding blatant design flaws. It will be interesting to see what the final mini-rig product looks like and whether or not you've learned from mistakes you've made with the singles.

Perhaps you should have a go at the polishing experiment (or whatever else you can think up), and let us know how it works? I am always interested to know the results of real world tests. Before calling it a "mistake", prove that it is wrong.

[Inaba]

I'm not weighing in on the polished vs unpolished debate (or sanded properly or not) ... but I do want to point out this:

Other fpga manufacturers are not having throttling issues.

There are no other FPGA manufacturers that are utilizing these chips in this manner, so it's basically a first adopter problem for BFL in design and operation.  Virtually all other FPGA applications do not utilize the chip to the capacity bitcoin mining does, which is, as I understand it, the fundamental problem BFL had in the beginning with their designs and simulations and the start/root cause of all the mystery to begin with.

[rjk]

I'm not weighing in on the polished vs unpolished debate (or sanded properly or not) ... but I do want to point out this:

Other fpga manufacturers are not having throttling issues.

There are no other FPGA manufacturers that are utilizing these chips in this manner, so it's basically a first adopter problem for BFL in design and operation.  Virtually all other FPGA applications do not utilize the chip to the capacity bitcoin mining does, which is, as I understand it, the fundamental problem BFL had in the beginning with their designs and simulations and the start/root cause of all the mystery to begin with.

Not only that, but BFL is the only one using a chip that has metal packaging, all the rest are plastic, so comparisons between them don't make a whole lot of sense..

[steamboat]

Had you taken the time to run through the grits after sanding the chip, it is quite possible, neigh probable, the singles would not be having such bad throttling issues.

If you've done any recent research, most of the "mirror finish" stuff has been debunked, seriously.

link? every chip/heatsink i've ever owned has benefited from lapping. is a "mirror finish" necessary? no. Is it better to have an 800 grit finish than a 120? yes. (not saying it's a 120 grit finish before you micro-analyse. i don't have the chip on hand so i can't tell you what the finish is)

Other fpga manufacturers are not having throttling issues. Whether that is because they aren't utilizing the chips as well as you are, or because your thermal designs are terrible, is debatable. What isn't debatable is years of research in which techniques provide the best cooling for a chip, regardless of whether it's a cpu, gpu, fpga, or asic.

Umm.. they get plenty of "throttling", if they turn the speed up to insane levels. Technically it is just increased error rates, which indicates a need to reduce the speed to compensate.

what constitutes insane levels? I don't know of any other companies using that chip, so i can't say how aggressive their clocks are. I also mentioned its quite possible BFL has a highly optimized bitstream that's putting a lot of thermal pressure on the chip. What i'm saying is their thermal dissipation design is not adequate/optimized and it's causing issues.
thermal paste is designed to increase the surface area contact of chip/heatsink. you want to use the smallest amount possible because metal to metal is a better conductor than metal to tim to metal. logically, if nothing else, the smoother/flatter the surface, the less tim required, the better the cooling.

As i stated before, I do like your company and i do appreciate what you're trying to do. What I don't like is the excuses you are giving regarding blatant design flaws. It will be interesting to see what the final mini-rig product looks like and whether or not you've learned from mistakes you've made with the singles.

Perhaps you should have a go at the polishing experiment (or whatever else you can think up), and let us know how it works? I am always interested to know the results of real world tests. Before calling it a "mistake", prove that it is wrong.

a single-specific experiment? sure, send me one and i'll have a go at it   as far as experiments with lapping vs non lapped. google "does lapping increase performance" the general consensus is yes, if the chip isn't flat/has a rough surface, or the heatsink isn't flat/rough surface.

I'm not weighing in on the polished vs unpolished debate (or sanded properly or not) ... but I do want to point out this:

Other fpga manufacturers are not having throttling issues.

There are no other FPGA manufacturers that are utilizing these chips in this manner, so it's basically a first adopter problem for BFL in design and operation.  Virtually all other FPGA applications do not utilize the chip to the capacity bitcoin mining does, which is, as I understand it, the fundamental problem BFL had in the beginning with their designs and simulations and the start/root cause of all the mystery to begin with.

again, i'm not debating that. If BFL's designers are so good (which again, it seems that they are) that they're running into thermal issues, they should create a solution that actually solves the issue. The box design is not optimized for airflow, the heatsink is not optimized for dissipation, and the sanding was not optimized for heatsink contact, thus creating issues.



EDIT:

I'm not weighing in on the polished vs unpolished debate (or sanded properly or not) ... but I do want to point out this:

Other fpga manufacturers are not having throttling issues.

There are no other FPGA manufacturers that are utilizing these chips in this manner, so it's basically a first adopter problem for BFL in design and operation.  Virtually all other FPGA applications do not utilize the chip to the capacity bitcoin mining does, which is, as I understand it, the fundamental problem BFL had in the beginning with their designs and simulations and the start/root cause of all the mystery to begin with.

Not only that, but BFL is the only one using a chip that has metal packaging, all the rest are plastic, so comparisons between them don't make a whole lot of sense..

metal packaging is a better conductor than plastic. not following there.

[rjk]

If you've done any recent research, most of the "mirror finish" stuff has been debunked, seriously.

link? every chip/heatsink i've ever owned has benefited from lapping. is a "mirror finish" necessary? no. Is it better to have an 800 grit finish than a 120? yes. (not saying it's a 120 grit finish before you micro-analyse. i don't have the chip on hand so i can't tell you what the finish is)

Quite so. I was referring specifically only to the mirror finish, not lapping.

Umm.. they get plenty of "throttling", if they turn the speed up to insane levels. Technically it is just increased error rates, which indicates a need to reduce the speed to compensate.

what constitutes insane levels? I don't know of any other companies using that chip, so i can't say how aggressive their clocks are. I also mentioned its quite possible BFL has a highly optimized bitstream that's putting a lot of thermal pressure on the chip. What i'm saying is their thermal dissipation design is not adequate/optimized and it's causing issues.
thermal paste is designed to increase the surface area contact of chip/heatsink. you want to use the smallest amount possible because metal to metal is a better conductor than metal to tim to metal. logically, if nothing else, the smoother/flatter the surface, the less tim required, the better the cooling.

Flatter, yes, but smoother is debatable because if it is too smooth, the thermal paste might not be able to fill the remaining imperfections, since they are smaller than the paste particle size.

Perhaps you should have a go at the polishing experiment (or whatever else you can think up), and let us know how it works? I am always interested to know the results of real world tests. Before calling it a "mistake", prove that it is wrong.

a single-specific experiment? sure, send me one and i'll have a go at it   as far as experiments with lapping vs non lapped. google "does lapping increase performance" the general consensus is yes, if the chip isn't flat/has a rough surface, or the heatsink isn't flat/rough surface.

The consensus that I found was that polishing wasn't nearly as important as having a perfectly flat surface.

Not only that, but BFL is the only one using a chip that has metal packaging, all the rest are plastic, so comparisons between them don't make a whole lot of sense..

metal packaging is a better conductor than plastic. not following there.

All I'm saying is that you shouldn't compare them. All "the other FPGA manufacturers" are using plastic chips.

[BTCurious]

Not only that, but BFL is the only one using a chip that has metal packaging, all the rest are plastic, so comparisons between them don't make a whole lot of sense..

metal packaging is a better conductor than plastic. not following there.

All I'm saying is that you shouldn't compare them. All "the other FPGA manufacturers" are using plastic chips.

I was wondering about that. Isn't the BFL single a plastic chip with a metal plate on top? Because if so, then why use the metal plate at all? Wouldn't it be better to put the heatsink directly on the chips? (Just wondering here, not taking sides)

[Inaba]

again, i'm not debating that. If BFL's designers are so good (which again, it seems that they are) that they're running into thermal issues, they should create a solution that actually solves the issue. The box design is not optimized for airflow, the heatsink is not optimized for dissipation, and the sanding was not optimized for heatsink contact, thus creating issues.

I don't disagree that the box design is not optimal in any way and I agree with you other assessments.  I was merely pointing out the fact that there are literally no other FPGA vendors doing or have done what BFL has done with these chips.  Even disregarding the plastic vs metal issue for a comparison, no other vendor would have run into these problems because they are not pushing the chips to continuous duty as far as bitcoin mining pushes them.  

[rjk]

All I'm saying is that you shouldn't compare them. All "the other FPGA manufacturers" are using plastic chips.

I was wondering about that. Isn't the BFL single a plastic chip with a metal plate on top? Because if so, then why use the metal plate at all? Wouldn't it be better to put the heatsink directly on the chips? (Just wondering here, not taking sides)

No, the chip packaging is similar to a CPU, where it is very close to or in contact with the die. The die itself is smaller then the area covered by the heat spreader.

[Inaba]

I bet someone that has a high capacity CNC machine that releases a water block for these would make bank.  I wish I knew how to mill.

[Cablez]

Considering BFL has already created a waterblock they should start selling those on their site as well.  Then we can wait 4 weeks for 2 different items.........I kid I kid!

[SgtSpike]

I bet someone that has a high capacity CNC machine that releases a water block for these would make bank.  I wish I knew how to mill.

If someone designs one, I have access to machines...

[rjk]

Considering BFL has already created a waterblock they should start selling those on their site as well.  Then we can wait 4 weeks for 2 different items.........I kid I kid!

Their design uses screw mounts that are not available on current-gen boards. The newer-gen boards have a tweaked layout to accommodate the block, so I wonder if it would still be possible to make a block for the current-gen singles.

[despoiler]

I bet someone that has a high capacity CNC machine that releases a water block for these would make bank.  I wish I knew how to mill.

I thought BFL was already working on one.

[DeathAndTaxes]

I bet someone that has a high capacity CNC machine that releases a water block for these would make bank.  I wish I knew how to mill.

If someone designs one, I have access to machines...

BFL alreayd made one.  Maybe they will give you the specs.  Could be a win - win.  Better cooling product would mean the chips can be driven harder = more demand for their chips.

[Unacceptable]

These units were designed to run in a commercial temp controlled enviroment @ 72 degrees f.Since they are not being run in such an enviroment,i.e. homes & offices where temp is not a mandatory 72 degrees,we are seeing these "overheat" issues.IMO.Plus the varience on a chip by chip basis as well.

Its was a choice they made when designing these devices.Personally I think it wasn't a good decision.Knowing full well the general public was going eat these up like candy.

I'm an A/C install & service tech & know of very few people who keep thier homes @ 72 f.It's more like 76-82 f.

I am not attacking BTW.I'm just stating things as I see them It's a great product & I'm very happy with it

My unit runs @ 760 mh/s consistantly (on the 768 FW,even at 89 degrees room temp   ) & I will at later date try to improve that by changing the grease & maybe an improved HS/fan setup,I'm still thinking

I'm also watching these BFL threads & other FPGA threads for ideas  

[cuz0882]

I bet someone that has a high capacity CNC machine that releases a water block for these would make bank.  I wish I knew how to mill.

I thought BFL was already working on one.

I would like to see a decent heatsink on the singles. Water cooling is a little extreme for something like this.

[Cablez]

I'd do it just because its something I'm in to.  Can't remember my last aircooled rig.  It certainly has potential for performance gains.

[SgtSpike]

These units were designed to run in a commercial temp controlled enviroment @ 72 degrees f.Since they are not being run in such an enviroment,i.e. homes & offices where temp is not a mandatory 72 degrees,we are seeing these "overheat" issues.IMO.Plus the varience on a chip by chip basis as well.

Its was a choice they made when designing these devices.Personally I think it wasn't a good decision.Knowing full well the general public was going eat these up like candy.

I'm an A/C install & service tech & know of very few people who keep thier homes @ 72 f.It's more like 76-82 f.

I am not attacking BTW.I'm just stating things as I see them It's a great product & I'm very happy with it

My unit runs @ 760 mh/s consistantly (on the 768 FW,even at 89 degrees room temp   ) & I will at later date try to improve that by changing the grease & maybe an improved HS/fan setup,I'm still thinking

I'm also watching these BFL threads & other FPGA threads for ideas  

Exactly.  All 10 of mine were absolutely fine with no throttling whatsoever in my 72F office.  I have a dedicated window A/C in there to keep things cool, and have it set at 70 (by the time the air is around to the miners, it's probably 72).

I only have 4 left, but have upgraded them all to the 872 MH/s firmware, and still zero throttling.

I think people are trying to expect too much of them out of environments that are hotter than 72F.

[bitpop]