[Archive] BFL trolling museum

[freeAgent]

So, you all saw this right?

Some did, others just thought "lol another delay" without realising that the timeline is actually pretty consistent with their December update. The update also happens to be their most detailed ever (ie. it actually includes a timeline...).

Well I'm totally fine laughing at you guys when the actually consistent date is pushed down for another month.

Btw what does week of feb. 10th actually mean? That's kinda ambiguous since it is a sunday. Is it the week before the sunday or after it?

Usually Sunday is counted as the first day of the week, so "the week of the 10th" means the 10th through the 16th.  That is pretty standard time measurement.

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[ElectricMucus]

So, you all saw this right?

Some did, others just thought "lol another delay" without realising that the timeline is actually pretty consistent with their December update. The update also happens to be their most detailed ever (ie. it actually includes a timeline...).

Well I'm totally fine laughing at you guys when the actually consistent date is pushed down for another month.

Btw what does week of feb. 10th actually mean? That's kinda ambiguous since it is a sunday. Is it the week before the sunday or after it?

Usually Sunday is counted as the first day of the week, so "the week of the 10th" means the 10th through the 16th.  That is pretty standard time measurement.

I assumed, ok then if they haven't shipped ASICs on the 17th they failed, right?

[becoin]

So, you all saw this right?

I have seen it already a month ago, 2 months ago, 3 months ago, 4 months ago... How many times should I watch this movie again and again?

[SgtSpike]

So, you all saw this right?

I have seen it already a month ago, 2 months ago, 3 months ago, 4 months ago... How many times should I watch this movies again and again?

Tis certainly entirely up to you.  Get a refund if you're tired of it.

[foo]

Usually Sunday is counted as the first day of the week, so "the week of the 10th" means the 10th through the 16th.  That is pretty standard time measurement.

Monday is the first day of the week in Europe, and also in the ISO standard. You Americans and your weird measurements...

[becoin]

So, you all saw this right?

I have seen it already a month ago, 2 months ago, 3 months ago, 4 months ago... How many times should I watch this movies again and again?

Tis certainly entirely up to you.  Get a refund if you're tired of it.

I can not get a refund. BFL refuse full refunds in BTC! What they do is only partial BTC refunds.

[lucif]

They spent your money for blackjack and whores ASIC research and contracts.

How they will refund everybody? They dont have enough amount for all.

[Frizz23]

How they will refund everybody? They dont have enough amount for all.

They simply ship what they have:

More specifically this is what BFL brought to the CES convention. What was the point again? To show off all the extra space you have? BFL so fucking fail. LOL!

[aTg]

Will change the QFN package to BGA simply to transmit heat better?
The spartan6 have such plastic package and there is no problem, if they change to a BGA chip size should be larger and totally different PCB design starting from 0, I have not read anything about how long it will take to redesign the PCB or if that will fit inside its gleaming steel boxes sanding.
When you have so many delays and are desperate to introduce the team, not more logical to have some little problem of heat put to redesign everything from almost 0?
What I see is to announce that you can put a BGA, and finally solder a latest generation FPGA with sanded surface ...

[ElectricMucus]

Will change the QFN package to BGA simply to transmit heat better?
The spartan6 have such plastic package and there is no problem, if they change to a BGA chip size should be larger and totally different PCB design starting from 0, I have not read anything about how long it will take to redesign the PCB or if that will fit inside its gleaming steel boxes sanding.
When you have so many delays and are desperate to introduce the team, not more logical to have some little problem of heat put to redesign everything from almost 0?
What I see is to announce that you can put a BGA, and finally solder a latest generation FPGA with sanded surface ...

Yes, however that even a last gen FPGA meets the performance requirements even by a magnitude is unrealistic.

Or it could in fact turn out to be consistent with a commonly sold structured ASIC like Altera Hardcopy & Co, what I mentioned all along, for which Josh countered "you know what we are using another package format, ha!"
Oh the "sidenote" that the performance/jule figures could be "a little off" is totally consistent with that too, just that if it turns out to be a structured asic it wouldn't just be a "little off".

If it weren't for the possibility of a total fuckup... oh well.  

[DobZombie]

https://forums.butterflylabs.com/bfl-forum-miscellaneous/690-13-jan-2013-asic-update-discussion-thread.html

An update that is...empty....

Just like your head.

lol!

[aTg]

Will change the QFN package to BGA simply to transmit heat better?
The spartan6 have such plastic package and there is no problem, if they change to a BGA chip size should be larger and totally different PCB design starting from 0, I have not read anything about how long it will take to redesign the PCB or if that will fit inside its gleaming steel boxes sanding.
When you have so many delays and are desperate to introduce the team, not more logical to have some little problem of heat put to redesign everything from almost 0?
What I see is to announce that you can put a BGA, and finally solder a latest generation FPGA with sanded surface ...

Yes, however that even a last gen FPGA meets the performance requirements even by a magnitude is unrealistic.

Or it could in fact turn out to be consistent with a commonly sold structured ASIC like Altera Hardcopy & Co, what I mentioned all along, for which Josh countered "you know what we are using another package format, ha!"
Oh the "sidenote" that the performance/jule figures could be "a little off" is totally consistent with that too, just that if it turns out to be a structured asic it wouldn't just be a "little off".

If it weren't for the possibility of a total fuckup... oh well.  

Is that I assume from the beginning that it will be a structured asic ...
And they will not deliver 60 GH/s

[PuertoLibre]

https://forums.butterflylabs.com/bfl-forum-miscellaneous/690-13-jan-2013-asic-update-discussion-thread.html

An update that is...empty....

Just like your head.

lol!

You amuse easily, like a circus monkey.

Turns out I must apologize. The Box of Fans isn't a Box of Fans at all as this new picture shows














































































It's a box of fans and space(rs).

[Micon]

My BFL scam accusation thread:

https://bitcointalk.org/index.php?topic=136392.msg1453090#msg1453090

started for a full investigation of BFL.   Remember this is a representative of the company on the floor of CES 2013:

http://www.youtube.com/watch?v=UlWrmIqGs3Y&feature=youtu.be&t=2m36s

[bitmar]

This update still does not explain the mass production of chips without a prototype and testing. The chances that these chips will work are the same as 100,000 lines of code written on paper by the programmer.  They still do not know the exact parameters of chips.  0.8w per GH or 1.2w per GH - this is a great difference -> 50% !!!

Typical Phases of a Custom ASIC Design.
1. Feasibility Study
2. Design
3. Prototyping !!!!
4. Engineering Runs
5. Industrialization
6. Management of full IC Fabrication Process
7. Wide Selection of Processes and Technologies
8. Series Production
http://www.trias-mikro.de/html/prod_asic_overview_chipAlliance.html?1,1,0

BFL Phases:

1. Design
2. Series Production
3. Waiting for a miracle that the chips will work

[smoothie]

This update still does not explain the mass production of chips without a prototype and testing. The chances that these chips will work are the same as 100,000 lines of code written on paper by the programmer.  They still do not know the exact parameters of chips.  0.8w per GH or 1.2w per GH - this is a great difference -> 50% !!!

Typical Phases of a Custom ASIC Design.
1. Feasibility Study
2. Design
3. Prototyping !!!!
4. Engineering Runs
5. Industrialization
6. Management of full IC Fabrication Process
7. Wide Selection of Processes and Technologies
8. Series Production
http://www.trias-mikro.de/html/prod_asic_overview_chipAlliance.html?1,1,0

BFL Phases:

1. Design
2. Series Production
3. Waiting for a miracle that the chips will work

+1 without thorough testing and a prototype they are fucked if they think they can ship in Feb with no issues.

[Gyrsur]

This update still does not explain the mass production of chips without a prototype and testing. The chances that these chips will work are the same as 100,000 lines of code written on paper by the programmer.  They still do not know the exact parameters of chips.  0.8w per GH or 1.2w per GH - this is a great difference -> 50% !!!

Typical Phases of a Custom ASIC Design.
1. Feasibility Study
2. Design
3. Prototyping !!!!
4. Engineering Runs
5. Industrialization
6. Management of full IC Fabrication Process
7. Wide Selection of Processes and Technologies
8. Series Production
http://www.trias-mikro.de/html/prod_asic_overview_chipAlliance.html?1,1,0

BFL Phases:

1. Design
2. Series Production
3. Waiting for a miracle that the chips will work

I guess BFL did software simulations of the ASIC design and founded on these results the design was chosen for production without prototyping. Also the specs are founded on the software simulations I guess.

[nathanrees19]

I have not read anything about how long it will take to redesign the PCB

With good engineers? A day. Throw in another day to get other engineers to review it. Add a few weeks to get them manufactured in whatever quantity. Since they would have made this design change at least a month ago (most likely more), they would have the PCBs by now.

PCBs are easymode next to ASICs.

[nathanrees19]

I guess BFL did software simulations of the ASIC design and founded on these results the design was chosen for production without prototyping. Also the specs are founded on the software simulations I guess.

It's possible that they had prototype chips in a different package, identified all the issues in them and rolled in the fixes with the package change.

[nathanrees19]

started for a full investigation of BFL.   Remember this is a representative of the company on the floor of CES 2013:

http://www.youtube.com/watch?v=UlWrmIqGs3Y&feature=youtu.be&t=2m36s

I think you should post this video more; not enough people know that you're in the habit of harassing company representatives to try and make them look bad on video.