Klondike - 16 chip ASIC Open Source Board - Preliminary

[Silvas]

I don't know if avalon released their firmware or not but this isn't the avalon reference design, I do know that.  I'm sure it's based on it to some extent, but it definitely isn't a clone... so I doubt their firmware could just be dropped in without some changes, the extent of which is anyone's guess

[joeventura]

I wasn't implying just throwing in their firmware but using it as reference.

[daemondazz]

Their github readme still says:

current version of FPGA bitstream contains licensed parts we can not open source at the moment, a licensed free version is being worked on that will be released in the future.

It looks like the actual bitstream is there but not the source.

[BkkCoins]

Well, there goes my comfort level.

Did Avalong release their own firmware? Would it help or is this design completely different?

This is a completely different design. The only thing in common is they both have Avalon ASIC chips. The Avalon design does not have a micro-controller on board, my design does not have an FPGA. So their firmware is FPGA firmware and mine is PIC firmware. Due to this even the cgminer driver will be different. But this has all been known for 2 months now so it's not news to anyone who has been investing effort/time in Klondike products.


----

Just to update everyone in case it's not clear:

I've arrived back from Bkk and have sample chips from steamboat, final needed parts from Mouser, and K16 boards from China. I will be initially testing power supply on the boards and then PIC on the K1 and then mount an ASIC on a K1 for comm. tests. So barring unexpected set backs (like solder paste that turns out to be useless), I should be able to report something on ASIC communication within a day or two.

[Bakal]

Nice! Good luck!!! 

[fasmax]

TerraHash has had a K16 board populated for a few days now.
Have you received any feed back on how their bring process is going?
I know they promised to keep you included in board bring up.

[Beastlymac]

Well, there goes my comfort level.

Did Avalong release their own firmware? Would it help or is this design completely different?

This is a completely different design. The only thing in common is they both have Avalon ASIC chips. The Avalon design does not have a micro-controller on board, my design does not have an FPGA. So their firmware is FPGA firmware and mine is PIC firmware. Due to this even the cgminer driver will be different. But this has all been known for 2 months now so it's not news to anyone who has been investing effort/time in Klondike products.


----

Just to update everyone in case it's not clear:

I've arrived back from Bkk and have sample chips from steamboat, final needed parts from Mouser, and K16 boards from China. I will be initially testing power supply on the boards and then PIC on the K1 and then mount an ASIC on a K1 for comm. tests. So barring unexpected set backs (like solder paste that turns out to be useless), I should be able to report something on ASIC communication within a day or two.

Good news any idea on possible clock levels as it has been hinted that good levels of over clocking is a possibility? 

Thanks

[Bicknellski]

Just to update everyone in case it's not clear:

I've arrived back from Bkk and have sample chips from steamboat, final needed parts from Mouser, and K16 boards from China. I will be initially testing power supply on the boards and then PIC on the K1 and then mount an ASIC on a K1 for comm. tests. So barring unexpected set backs (like solder paste that turns out to be useless), I should be able to report something on ASIC communication within a day or two.

AWESOME NESS!

[Kake]

Just to update everyone in case it's not clear:

I've arrived back from Bkk and have sample chips from steamboat, final needed parts from Mouser, and K16 boards from China. I will be initially testing power supply on the boards and then PIC on the K1 and then mount an ASIC on a K1 for comm. tests. So barring unexpected set backs (like solder paste that turns out to be useless), I should be able to report something on ASIC communication within a day or two.

Best of luck! *Fingers crossed*

[eros]

EDIT: one is AP6502 and one is AP6502A
Your 5V*500mA calculation is based on the quiescent load I assume. So when there's no load the converter would use 2.5W.
Potentially the AP6502A would deliver 90%*2A*5V (assuming the Efficiency graph with Vout =3.3V is similar to the 1.2Vout) = 9W

USB (normal port) give 500mA 5V (miinus cable loss). No load current is minimal. I can't find 9W USB ports. Thank you clarifying AP6502 and AP6502A are diffrent chips. I missed it.
 But AP6502 and AP6502A have very similiar efficiency curves. In 3.3v range efficiency peaks 90% but not in 1.2V range. It is quite sure AP6502A 1.2V efficiency are 70-80% range in 2A current. Avalon best is 6.6W/Ghash 1.15v but normal operating 1.2v or little more if OC'd. 0.285Mhash * 6.6w=1.88w (at best) or 1.4A. From modules 164W per 80chips -> 2.05W per chip @1.2v -> 1.71A.
If AP6502A efficiency is 75% @1.2v 1.71A it takes 2.73W in. Over USB limit.
 Datasheet note add schotky diode to improve efficiency. But no data how much it helps or are efficiency graphs with or without diode.

--> nano may work in normal 500mW USB port, but it should undervolt/clocked. 1.2A charge USB works fine for nano2.

[Werner]

A great project you have here Good luck!

[docjunior]

Thanks for the updates, Bkk.  Excited to hear your first results!

[TomKeddie]

Well, there goes my comfort level.

Did Avalong release their own firmware? Would it help or is this design completely different?

This is a completely different design. The only thing in common is they both have Avalon ASIC chips. The Avalon design does not have a micro-controller on board, my design does not have an FPGA. So their firmware is FPGA firmware and mine is PIC firmware. Due to this even the cgminer driver will be different. But this has all been known for 2 months now so it's not news to anyone who has been investing effort/time .

Has anyone put a cro or logic analyzer on a real Avalon?  Without any of their hdl it is tough to know what the comms looks like.  Not releasing their code is annoying, they could release what they can and we could check out the comms protocol even if we can't build chips. In a few months their ip will be useless.

[intron]

Has anyone put a cro or logic analyzer on a real Avalon?  Without any of their hdl it is tough to know what the comms looks like.  Not releasing their code is annoying, they could release what they can and we could check out the comms protocol even if we can't build chips. In a few months their ip will be useless.

Asked the same, no response. The datasheet is rather vague
on crucial points, would love to see some real life scope traces.

intron

[marto74]

6 sample Avalon chips arrived today from zefir.
Test PCB boards are ready ,
most of the components are here too.

Sleepless nights are comming

[Foofighter]

6 sample Avalon chips arrived today from zefir.
Test PCB boards are ready ,
most of the components are here too.

Sleepless nights are comming

n1, gl

[intron]

6 sample Avalon chips arrived today from zefir.
Test PCB boards are ready ,
most of the components are here too.

Sleepless nights are comming

Nice:-)

intron

[marto74]

BKK
I have a question
On both K1 and K16 board BOM the PIK controler is the same
but the configurations on the PCB for the PIC on K1 and K16 are different.
Any special purpose on that?

[marto74]

K1 case and hea tsink design

[joeventura]

K1 case and hea tsink design

Real nice looking!

I would buy a room full of these if someone would sell them at a reasonable price (like double the cost to make them) Maybe $20-$30 each