Klondike - 16 chip ASIC Open Source Board - Preliminary

[joeventura]

Please let's get a standardized working design based on components that are readily available and screw with it after that is complete.

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[Bicknellski]

Unfortunately when I started the design I hadn't heard anything about over clocking Avalons and didn't design that in. I added some head room on the power supply just out of safety. I'm not aware of any higher current easy to swap regulator solution so the 3 options I see are:

1. Just place 14 chips / board. The wasted 2 chip board space isn't much of a loss.

2. Scrub the extra power connector behind the PCIe and add a IR3897 9A reg there to supply 4 of the end chips. This would cost a bit extra for parts - rough guess, about $5 maybe.

3. As #2 but extend the board by about 2cm and add 4 more chips, plus a full 16A IR3895 reg behind the PCIe conn. This would supply 6 chips, with 2 of those taken from current 16, making a 20 chip board. This would cost only a bit more than #2 due to higher board cost and the parts being a bit more costly, rough guess, about $8 maybe, but a more radical design change due to heat sink size also being different.

Another data point - the IR3895 over current protection kicks in at 18A minimum, so how well it behaves at max load probably depends a lot on how well it's cooled. Also, some of the reported power use in the other thread is for control board, 3.3V supply and fans so it could be somewhat less for actual ASIC power.

I'd vote for number #2 as that seems a simple solution. No radical change. Parts swap and a little more in price. Seems like the best route. Again if we can chip in for this redevelop or board order let us know. And in all seriousness heat sinks can be easily redesigned and as for anyone that did a mass production run already that is just foolish given that BKKCoins clearly warned everyone to WAIT till he had a working board.

I might add can the K64 have the additional IR3895 9A and the K16 retain the power connector? That way those who are wanting the same design because they have already heavily produced or lined up production for these prototype boards can jerry rig their units for 14 chips etc and those who are looking to maximize overclock etc and build farms can have this solution in the K64 boards? I do not think that 14 chips on a 16 chip board is a solution given the simple #2 solution.

282 >>> 350 is a significant jump especially when we are talking 1000s of chips. I really think that those of us who are in groups or have larger orders need to have this boost. The potential of 68 mhz per chip adds up and really shouldn't be ignored given the design and layout of the Cairnsmore 3 which is delayed but could be available in a few months. We really need this sort of change so that Klondikes are not a one off novelty and give us all an advantage. Waiting patiently for the decision. That extra $5 in board cost can mean faster ROI given the difficulty jumps.

[mike2kt]

2. Scrub the extra power connector behind the PCIe and add a IR3897 9A reg there to supply 4 of the end chips. This would cost a bit extra for parts - rough guess, about $5 maybe.

I'd vote for number #2 as that seems a simple solution. No radical change. Parts swap and a little more in price. Seems like the best route. Again if we can chip in for this redevelop or board order let us know. And in all seriousness heat sinks can be easily redesigned and as for anyone that did a mass production run already that is just foolish given that BKKCoins clearly warned everyone to WAIT till he had a working board.

I'm in agreement with BKKC about swapping in the IR3847 SupIRBuck regulator (16A vs 25A, see last page). The IR3847 isn't pin-for-pin compatible with the 16A regulators on rev V0.1. However it is still in the same chip package size. I haven’t gone that deep into the changes yet, but it looks like mainly moving traces around the regulators and substituting some components around the regulators with different values.

In other words the swap won't take any major board redesign. Implementing "patchwork" solutions like adding an unbalanced third rail (16Ax16Ax9A) would require significant board rework. Plus the additional cost is more than just the regulator, you have to factor in all the relevant component additions.

[ScaryHash]

Hi,

While that overclocking would be nice to have, I've found over many years of dealing with computers and overclocking that it's mostly a "feel good" measure. Why? Everybody wants something for nothing, and that's effectively what it is when you overclock a processor or a graphics card. Or, so people think.

There is an actual cost to making something overclockable, which we see here. Most people do not realize that there has always been a cost to overclocking, in the sense of the service life of a component, power cost, stability, heat, etc...

In any case, now we're talking about designing something to have overclocking "headroom". The cost that we're talking about now is some minimal $$, but also time to get stuff "right", which could be important down the road, especially with 30% difficulty increases that have been happening lately. If we see repeated 25-30% difficulty increases, that pretty much negates any overclocking headroom that could be built in, at least, in my opinion.

If you increase each chip by 50 Mh/s, 16 chips is only 0.8 Gh/s. That will mitigate part of ONE 25% increase in difficulty. It's not going to save anybody's ROI by more than a few days or a week at most.

I suspect that the real challenge will be getting the 16 chips working smoothly in CG miner.

Just my 2 bits. Working on a nice 4th of July present for ya...

[Vycid]

Hi,

While that overclocking would be nice to have, I've found over many years of dealing with computers and overclocking that it's mostly a "feel good" measure. Why? Everybody wants something for nothing, and that's effectively what it is when you overclock a processor or a graphics card. Or, so people think.

There is an actual cost to making something overclockable, which we see here. Most people do not realize that there has always been a cost to overclocking, in the sense of the service life of a component, power cost, stability, heat, etc...

In any case, now we're talking about designing something to have overclocking "headroom". The cost that we're talking about now is some minimal $$, but also time to get stuff "right", which could be important down the road, especially with 30% difficulty increases that have been happening lately. If we see repeated 25-30% difficulty increases, that pretty much negates any overclocking headroom that could be built in, at least, in my opinion.

If you increase each chip by 50 Mh/s, 16 chips is only 0.8 Gh/s. That will mitigate part of ONE 25% increase in difficulty. It's not going to save anybody's ROI by more than a few days or a week at most.

I suspect that the real challenge will be getting the 16 chips working smoothly in CG miner.

Just my 2 bits. Working on a nice 4th of July present for ya...

I agree entirely. We need to have a robust design complete at spec clocks before considering anything else - OC is extra. The game here is being first-to-market, not producing the best performance/price ratio. If you want that, KNCMiner is over there ---->

I would feel like an idiot if I ended up with dysfunctional miners because I wanted to save 2 chips per board.

[Bicknellski]

Given that this can be tested and determined to work the # 2 solution is really the best way to move forward given the overall concerns of those interested in this project. Time, difficulty and the costs involved can all be addressed simply with the #2 option. Keeping it as it is now will lead to an earlier "stale" date for the K16 or K64 board itself and that means a greater loss to BKKCoins overall if people simply stop ordering boards and paying him a royalty.

Clearly the best option is stability with the ability to overclock. Remember as an open source hardware project someone could easily do this with a slight revision and undercut BKKCoins and that is unfortunately a concern we need to be aware of given that many people have already JUMPED the gun and produced boards before a prototype. I won't be jumping ship to anyone else even if we are stuck with the current variant I am not sure about the rest of the people here though and I want to be sure that BKKCoins is rewarded for all this effort.  I worry with other projects being less than fair and jumping on the design yet again. We as group should not be held back by others like this but we also have to be proactive and protect BKKCoins investment.

[marto74]

True.
Do not worry.
Let's wait until these chips start to hash.
Then there are number of variants to achieve overclocking.
BKK is protected at least concerning my service

[dmcdad]

While that overclocking would be nice to have, I've found over many years of dealing with computers and overclocking that it's mostly a "feel good" measure. Why? Everybody wants something for nothing, and that's effectively what it is when you overclock a processor or a graphics card. Or, so people think.

Possibly, but keep in mind Avalon has said:

hint hint: the chip has a much higher clock cap

So using a higher clock rate might be much less of a hack than it seems.

[Ente]

I am an engineer with a background in aerodynamics/fluids and am capable of performing Heat/CFD simulations. Is there any way I can contribute to the heat sink/dissipation design. I can't promise anything but I can try if I had more understanding of what the goals/design are.

Awesome! :-)
Quick question about watercooling:
How about building a simple aluminum "box" from 5mm aluminum, no fins or similar, and screwing the K16s on that? We could use both sides of the cooler and it would be pretty easy to build.
I guess even with a low waterstream it should cool the board enough?
Cooling the water with a big radiator and a fan, outside, 35°C outside-temp worstcase.
With a few dozen watt per 100cm² this should be a piece of cake for the actual cooler?

Your gut-feeling is enough for me now :-)
(Else we might migrate to the K16 DIY thread)

Ente

[Defkin]

I am an engineer with a background in aerodynamics/fluids and am capable of performing Heat/CFD simulations. Is there any way I can contribute to the heat sink/dissipation design. I can't promise anything but I can try if I had more understanding of what the goals/design are.

Awesome! :-)
Quick question about watercooling:
How about building a simple aluminum "box" from 5mm aluminum, no fins or similar, and screwing the K16s on that? We could use both sides of the cooler and it would be pretty easy to build.
I guess even with a low waterstream it should cool the board enough?
Cooling the water with a big radiator and a fan, outside, 35°C outside-temp worstcase.
With a few dozen watt per 100cm² this should be a piece of cake for the actual cooler?

Your gut-feeling is enough for me now :-)
(Else we might migrate to the K16 DIY thread)

Ente

I am working on something here. I will update soon as I have been working on doing up 3d printed ends and clamps.
https://bitcointalk.org/index.php?topic=215893.0

[itod]

Any additional work on overclocking makes no sense in the circumstances where difficulty increases 20% every 2 weeks. All your overclocking gain will be immediately negated by difficulty rise.

Also, any component price increase, gaining their larger availability, is more than welcomed. Think about how much you will lose if you have to wait for any of the non-mass available component, or ship them from a far source. This is a real danger with a K16 PIC.

Just my 0.00000002

[Ente]

Any additional work on overclocking makes no sense in the circumstances where difficulty increases 20% every 2 weeks. All your overclocking gain will be immediately negated by difficulty rise.

Also, any component price increase, gaining their larger availability, is more than welcomed. Think about how much you will lose if you have to wait for any of the non-mass available component, or ship them from a far source. This is a real danger with a K16 PIC.

Just my 0.00000002

Huh?
Even when we have a 20% diff increase every 2 weeks, we still have those 20% gain on hashingrate *forever*!
As long as we start hashing at the same time, ideally shortly after receiving chips, we gain. If we were to wait 2 weeks longer because of implementing the overclocking, it equals out for the output . But still raises the resale-value of the miner.

As I said, I believe OC-capability will be a major deciding factor, quicker than we assume!

Ente

[sensei]

Kinda interested in the k-1

I don't see anyone willing to make them though

I can make them without any problem.

http://mittenmining.com

[sensei]

So the bake went ok. There are a few things I need to fix up. Here's a few photos snapped with the USB microscope and not enough light (it's late night here). Notice a solder bridge on PIC, IR3895 reg. twisted out of position a bit and I guess I'll have to use my rework station and adjust that. Maybe a bit too much paste? And a couple 0402 caps just plain sat up right. I thought they'd popped or exploded but I didn't hear anything, but then with the cam I saw they had just turned upwards and so only looked like they were gone.

One think I notice is no heat relief around the pads for the caps.  To get a better joint don't you usually use a pad attached to the plane rather than the plane itself?

Yes, that is the case. You need the thermal relief from the plane.

[itod]

If we were to wait 2 weeks longer because of implementing the overclocking, it equals out for the output .

My bad, you are right. It is a good strategy to wait.

[BkkCoins]

NEWS FLASH!!! NEWS FLASH!!!

My K16 is hashing with 1 chip.

It's not giving a correct result nonce yet but I'm almost 99% sure that's due to errors in precalc code or maybe I'm shifting in word order backwards.

I soldered an ASIC on the board this morning and spent all day twiddling this and that, mostly getting the clock config right. Then bamm I saw something that looked like nonce bits coming out but they were stunted little bits trying desperately to reach high. But the twinkle was enough and I went through the Avalon reference design again to check and realized I'd not used the correct pull-up value for the result lines. Somehow I f'd up and spec'd 100k resistors instead of 470R. So I quickly removed them and soldered in some 1K that I had here. And the bits sprung forth to their full heights. I was totally excited and hopping around my work bench. Even my wife was in to see what the big commotion was about.

So... next step, test the UART receiver, and muck with the send data until the right nonce comes back.

BTW I'm running at half clock b/c no heat sink attached yet. The chip gets slightly warmish to the finger. With only one chip and half clock you have to set the scope trigger and hold the probes for a while until a nonce is found. I counted about 4-8 seconds but of course it depends on what point it is in it's cycle. One chip at half clock (128MHz) would be about 33 seconds for a full sweep.

[loshia]

NEWS FLASH!!! NEWS FLASH!!!

My K16 is hashing with 1 chip.

It's not giving a correct result nonce yet but I'm almost 99% sure that's due to errors in precalc code or maybe I'm shifting in word order backwards.

I soldered an ASIC on the board this morning and spent all day twiddling this and that, mostly getting the clock config right. Then bamm I saw something that looked like nonce bits coming out but they were stunted little bits trying desperately to reach high. But the twinkle was enough and I went through the Avalon reference design again to check and realized I'd not used the correct pull-up value for the result lines. Somehow I f'd up and spec'd 100k resistors instead of 470R. So I quickly removed them and soldered in some 1K that I had here. And the bits sprung forth to their full heights. I was totally excited and hopping around my work bench. Even my wife was in to see what the big commotion was about.

So... next step, test the UART receiver, and muck with the send data until the right nonce comes back.

BTW I'm running at half clock b/c no heat sink attached yet. The chip gets slightly warmish to the finger. With only one chip and half clock you have to set the scope trigger and hold the probes for a while until a nonce is found. I counted about 4-8 seconds but of course it depends on what point it is in it's cycle. One chip at half clock (128MHz) would be about 33 seconds for a full sweep.

GEAT!
We are moving forward

[zurg]

NEWS FLASH!!! NEWS FLASH!!!

My K16 is hashing with 1 chip.

It's not giving a correct result nonce yet but I'm almost 99% sure that's due to errors in precalc code or maybe I'm shifting in word order backwards.

I soldered an ASIC on the board this morning and spent all day twiddling this and that, mostly getting the clock config right. Then bamm I saw something that looked like nonce bits coming out but they were stunted little bits trying desperately to reach high. But the twinkle was enough and I went through the Avalon reference design again to check and realized I'd not used the correct pull-up value for the result lines. Somehow I f'd up and spec'd 100k resistors instead of 470R. So I quickly removed them and soldered in some 1K that I had here. And the bits sprung forth to their full heights. I was totally excited and hopping around my work bench. Even my wife was in to see what the big commotion was about.

So... next step, test the UART receiver, and muck with the send data until the right nonce comes back.

BTW I'm running at half clock b/c no heat sink attached yet. The chip gets slightly warmish to the finger. With only one chip and half clock you have to set the scope trigger and hold the probes for a while until a nonce is found. I counted about 4-8 seconds but of course it depends on what point it is in it's cycle. One chip at half clock (128MHz) would be about 33 seconds for a full sweep.

Awesome, GJ! Cant wait lol

[BenTuras]

NEWS FLASH!!! NEWS FLASH!!!

My K16 is hashing with 1 chip.

CONGRATS!!

I was totally excited and hopping around my work bench. Even my wife was in to see what the big commotion was about.

LOL

[GandalfG]

NEWS FLASH!!! NEWS FLASH!!!

My K16 is hashing with 1 chip.

It's not giving a correct result nonce yet but I'm almost 99% sure that's due to errors in precalc code or maybe I'm shifting in word order backwards.

I soldered an ASIC on the board this morning and spent all day twiddling this and that, mostly getting the clock config right. Then bamm I saw something that looked like nonce bits coming out but they were stunted little bits trying desperately to reach high. But the twinkle was enough and I went through the Avalon reference design again to check and realized I'd not used the correct pull-up value for the result lines. Somehow I f'd up and spec'd 100k resistors instead of 470R. So I quickly removed them and soldered in some 1K that I had here. And the bits sprung forth to their full heights. I was totally excited and hopping around my work bench. Even my wife was in to see what the big commotion was about.

So... next step, test the UART receiver, and muck with the send data until the right nonce comes back.

BTW I'm running at half clock b/c no heat sink attached yet. The chip gets slightly warmish to the finger. With only one chip and half clock you have to set the scope trigger and hold the probes for a while until a nonce is found. I counted about 4-8 seconds but of course it depends on what point it is in it's cycle. One chip at half clock (128MHz) would be about 33 seconds for a full sweep.

Its work, its work  ...
gratz, GJ and keep it up.