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Author Topic: Klondike - 16 chip ASIC Open Source Board - Preliminary  (Read 434513 times)
c-tek
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July 08, 2013, 12:40:36 PM
 #2121


I love self proclaimed EE's.  Where's my facepalm picture...

Enigma...
Please keep it real, My certification in EE and IT that i have can back up most of what i say.
If you can keep this discussion on topic it it will be beneficial for all of us. Just because you love yourself we do not need to know....

Anyway as BKK say-ed the board will have the clock "covered" and will be in the admissible range for EMI (in my opinion). And if indeed we will see that it does interfere with other equipments (ie not FCC compliant) one can always create a casing from aluminum with proper ventilation holes and just use GND on the Board and the case.
The case can also be very good in such a way that we can make the airflow go trough the fins of the radiator as we want and not let it take the easy way out.


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cp1
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July 08, 2013, 12:46:34 PM
 #2122

I've made up plenty solderless breadboard prototypes using a 20MHz crystal for a PIC and have managed to not knock out my cell reception.  I'm sure it'll be fine.

Guide to armory offline install on USB key:  https://bitcointalk.org/index.php?topic=241730.0
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July 08, 2013, 02:03:13 PM
 #2123

1000 results:
374/364/175/64/19/1/2/1/0/0
(which is 1007 nonces = close to expected average of 1000)
I'm surprised so many have 0. If only we could test for a "dead" work unit and discard them. Tongue
Then you could increase all hashing performance by a massive 37% (based on that result) Cheesy

... and yet this is something I looked into a long time ago (almost 2 years) early on when I first found out about bitcoin, but never completed my work on it ...
By the looks of those results I should get back to it one day and finish it ... but I doubt I'll bother since it probably won't yield anything Tongue
It started as a program to optimise hashing (and found all the GPU optimisations independently)
Those results look very close the theoretical values for the relevant Poisson distribution (lambda = 1). The first 11 theoretical values are: {367.88, 367.88, 183.94, 61.313, 15.328, 3.0657, 0.51094, 0.072992, 0.009124, 0.001014, 0.000101}. This makes sense, since mining is a Poisson process.

Something I learned: multiple nonces within one work unit occurs about 2/3 as often as a single nonce. So you should be prepared to handle multiple nonces.
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July 08, 2013, 07:55:39 PM
 #2124

Kano, is there somewhere we can checkout the modified cgminer with the bflsc nonce stats?  I'd love to go further down the rabbit hole on these nonce statistics using a Jalapeno.

Thanks.

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July 08, 2013, 09:47:47 PM
 #2125

I know somewhere in this thread is the estimated wattage / amperage for each board. What was it @ 256MHz? what is it / to be expected at 350MHz? JUst trying to plan out the most cost effective PSU for amps on the 12v rail and wattage
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July 08, 2013, 09:49:56 PM
 #2126

I think each chip is 2W.  I'd imagine they'd be the bulk of the power use, maybe 80%?  (I just made that % up)

Guide to armory offline install on USB key:  https://bitcointalk.org/index.php?topic=241730.0
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July 08, 2013, 10:02:56 PM
 #2127

I know somewhere in this thread is the estimated wattage / amperage for each board. What was it @ 256MHz? what is it / to be expected at 350MHz? JUst trying to plan out the most cost effective PSU for amps on the 12v rail and wattage
Here's some info I posted a while back in a PM.

Quote
For typical use I've been going by the Avalon figures posted originally. They state 6.6W/GH, which is 1.86W/chip @ 282MH or 1.6A each. Each reg is rated for 16A and I think can handle that. So with given figures we'd be using 12.8A. I'd estimate about 13.6A @ 300MH, and judging from forum posts at 350MH (576W for 3 mods, 240 chips, but derate by 88% eff. for reg. out rating) it would be about 1.8A each or ~15A. So I'm projecting we can handle up to 350 without severe issues and likely just better cooling, more airflow.

Note that the reg has over current shutdown minimum 18A and the inductors are rated for 18A (which is when it's temp rises 40C above ambient).

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July 08, 2013, 10:27:02 PM
 #2128

I know somewhere in this thread is the estimated wattage / amperage for each board. What was it @ 256MHz? what is it / to be expected at 350MHz? JUst trying to plan out the most cost effective PSU for amps on the 12v rail and wattage
Here's some info I posted a while back in a PM.

Quote
For typical use I've been going by the Avalon figures posted originally. They state 6.6W/GH, which is 1.86W/chip @ 282MH or 1.6A each. Each reg is rated for 16A and I think can handle that. So with given figures we'd be using 12.8A. I'd estimate about 13.6A @ 300MH, and judging from forum posts at 350MH (576W for 3 mods, 240 chips, but derate by 88% eff. for reg. out rating) it would be about 1.8A each or ~15A. So I'm projecting we can handle up to 350 without severe issues and likely just better cooling, more airflow.

Note that the reg has over current shutdown minimum 18A and the inductors are rated for 18A (which is when it's temp rises 40C above ambient).
It looks like the Avalon design used a 20 amp regulator. This gives 2 amps per chip. The k16 also provides 2 amps per ASIC.
So if people are over clocking their Avalon design then I would think the K16 regulator would allow similar over clocking.
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July 08, 2013, 11:06:07 PM
 #2129

anyone have a idea/link of a good dc fan to mount on the heatsink for oc

what would be the max fan dimensions of the fan to fit , if I intend to stack K-16 on top of another ?
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July 08, 2013, 11:28:36 PM
 #2130

Kano, is there somewhere we can checkout the modified cgminer with the bflsc nonce stats?  I'd love to go further down the rabbit hole on these nonce statistics using a Jalapeno.

Thanks.

My git https://github.com/kanoi/cgminer
I'm not committing code in the master git at the moment while contact with ckolivas is sporadic - he's on holidays

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July 09, 2013, 05:45:40 AM
 #2131


My git https://github.com/kanoi/cgminer
I'm not committing code in the master git at the moment while contact with ckolivas is sporadic - he's on holidays


Thanks.  Building now.


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July 09, 2013, 06:37:20 AM
 #2132


My git https://github.com/kanoi/cgminer
I'm not committing code in the master git at the moment while contact with ckolivas is sporadic - he's on holidays


Thanks.  Building now.

And yes it's in the API 'stats' of course.

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July 09, 2013, 08:02:24 AM
 #2133

just a small question:

the not overclocked K16, will it need active cooling (fan) or is a heatsink enough?

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July 09, 2013, 08:19:01 AM
 #2134

just a small question:

the not overclocked K16, will it need active cooling (fan) or is a heatsink enough?
Probably active cooling but it seems like not that much airflow is needed so it could be very quiet. I'm just guessing right now based on how the first 3 chips are heating up. A big heat sink may be enough. I've run two chips fine with no cooling. Then I added a fan and the chips stay really cool. So then added a third and the heat sink doesn't even get warm with a fan. We'll see when the full 16 chips are putting energy into the heat sink, and for sure I'll report it here.

I also switched from 12V adapter to my ATX supply now. I hoped it would improve error rates due to better power but made no diff. Just prepping for adding up to the full 16 chips now. The wall wart couldn't handle more than 3-4.

BTW I've also been revising the PCB now as I want to get new ones made ASAP. I'ved changed the NOR gate to Dual NOR Gate, added a Schmitt buffer that could be easily left off by jumping it if not needed, and will add 16 ferrite beads to try improve the PLL stability.

I'm not committing code in the master git at the moment while contact with ckolivas is sporadic - he's on holidays
This code could actually be useful for detecting if chips are fully functional (each nonce range) if it could report a distribution of nonce values, 0 -> 2^32. Right now, I eye ball the nonce results and check if they seem to cover all values without duplicates (overlap). Maybe I should add an range accumulator into the nonce check to verify each chip is doing what it should be.

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July 09, 2013, 08:30:42 AM
 #2135

------
I'm not committing code in the master git at the moment while contact with ckolivas is sporadic - he's on holidays
This code could actually be useful for detecting if chips are fully functional (each nonce range) if it could report a distribution of nonce values, 0 -> 2^32. Right now, I eye ball the nonce results and check if they seem to cover all values without duplicates (overlap). Maybe I should add an range accumulator into the nonce check to verify each chip is doing what it should be.

+1 On that. A way to make sure all 16 chips hashing OK is a must. Otherwise it may turn that only I/O works and to loose hashing power


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July 09, 2013, 08:31:02 AM
 #2136

Just got this nonce: b000bbbf  Grin

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July 09, 2013, 08:35:53 AM
 #2137

Just got this nonce: b000bbbf  Grin

lol

b000b13s would be even better Tongue

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July 09, 2013, 08:36:27 AM
 #2138

Just got this nonce: b000bbbf  Grin
close enough.
id like b000b1e5

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July 09, 2013, 09:08:20 AM
 #2139

Maybe the ATX power is helping error rates. I'm getting 6 / 406 now, or about 1.5%. Much lower than last night on the wall wart, about 5%. Neither makes me happy but this is starting to get into a decent ball park.

Now tell me again how to calculate this properly using non 1-diff shares? I can't see a total count that includes difficulty accounted for. I know the git version now counts 1-diff shares, but is there a place to find that count on 3.3.1?

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July 09, 2013, 09:17:04 AM
Last edit: July 09, 2013, 09:32:29 AM by loshia
 #2140

Maybe the ATX power is helping error rates. I'm getting 6 / 406 now, or about 1.5%. Much lower than last night on the wall wart, about 5%. Neither makes me happy but this is starting to get into a decent ball park.

Now tell me again how to calculate this properly using non 1-diff shares? I can't see a total count that includes difficulty accounted for. I know the git version now counts 1-diff shares, but is there a place to find that count on 3.3.1?

yes you can With little hack of course

Here is the magic:
Driver avalon.c near line 736
if (avalon_decode_nonce(thr, avalon, info, ar, work)) {
   mutex_lock(&info->lock);
  if (!info->nonces++)
  gettemp = true;
  info->auto_nonces++;
  info->auto_totnonces++;
  mutex_unlock(&info->lock);
} else if (opt_avalon_auto) {
  mutex_lock(&info->lock);
  info->auto_hw++;
 info->totauto_hw++;
  mutex_unlock(&info->lock);
} else {
mutex_lock(&info->lock);
  info->totauto_hw++;
  mutex_unlock(&info->lock);
}

Define  info->auto_totnonces and   info->totauto_hw in driver avalon.h both int

Init/zero them somewhere in avalon_detect_one just to make it pretty Smiley
and finally around line 1285

root = api_add_int(root, "no_matching_work", &(info->no_matching_work), false);

Add
root = api_add_int(root, "totauto_hw", &(info->totauto_hw), false);
root = api_add_int(root, "auto_totnonces", &(info->auto_totnonces), false);

That is how i do that for the avalon and it works  Wink
And i can calculate good nonces per sec also ...and other fancy stuff
What i can tell that Con auto-freq code works rock solid and keeps hw% below 2% as advertised

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