FPGA development board "Lancelot" - accept bitsteam developer's orders.

[Icoin]

The DVB fundet Qcool Element (Water cooling adapter for Lancelot) goes prototype phase.
http://www.glari.ch:3000/projects/qcool
https://cryptostocks.com/securities/14

[loshia]

Guy's
While waiting for ngzang Lancelot bitstream i wana play with one of my boards  and try different bitstreams. I just wana be prepared for the moment when ngzang will release the official bitstream. However i have never done that before. I have a couple of questions and i would be thankful to anyone who can give me some info:

1. I have Lancelot dev kit available.
2. Are the instructions published for Icarus http://en.qi-hardware.com/wiki/Icarus#Flash_by_using_iMPACT,  http://dl.dropbox.com/u/28686048/Icarus/prgm-fpga.png, https://github.com/ngzhang/Icarus/blob/master/Downloads/bitsteam/guide%20for%20flash%20update.txt good to be used with Lancelot?
2. Have someone tried https://github.com/ngzhang/Icarus/tree/master/Downloads/bitsteam/200MHz_for_test or https://github.com/ngzhang/Icarus/tree/master/Downloads/bitsteam/V4 with lancelot?
3. What other "unofficial" bitsreams are available for Lancelot
4. How can i flash "temporally" bitstreams - i mean mcs files. As far i understood flashing mcs do not last power off/on? Probably this is the bet way for me to try.
5. I am using cgminer 2.7.5

Thank you very much in advance

[kano]

N.B. if you put a faster bitstream than 380MH/s in Icarus or Lancelot, you MUST at least use --icarus-timing short
Otherwise cgminer will slow down the device.

The default settings are to delay for 11.2 seconds before aborting work, and if the bitstream is only 1.5% faster than the 380Mh/s bitstream then the delay of 11.2 seconds will mean it will be idle for a short amount of time at the end of the nonce range each time it doesn't find a share in a full nonce range

The --icarus-timing options allow you to tell cgminer to work out the correct timing (using short or long) or specify the correct timing once you know it
See the API-README for details.

[loshia]

N.B. if you put a faster bitstream than 380MH/s in Icarus or Lancelot, you MUST at least use --icarus-timing short
Otherwise cgminer will slow down the device.

The default settings are to delay for 11.2 seconds before aborting work, and if the bitstream is only 1.5% faster than the 380Mh/s bitstream then the delay of 11.2 seconds will mean it will be idle for a short amount of time at the end of the nonce range each time it doesn't find a share in a full nonce range

The --icarus-timing options allow you to tell cgminer to work out the correct timing (using short or long) or specify the correct timing once you know it
See the API-README for details.

I know:)
I have read that already --icarus-timing. Th question was if someone have done it already. I just do not want to "kill" my board if i make something wrong while flashing it:)

[loshia]

Guys,
I am tiring to map my lancelets to particular names in order to be able to know which cgminer ICAxx corresponds to which board. I am using xubuntu 12.04.
I have tried following (udev rules):
ATTR{idVendor}=="0403",ATTR{idProduct}=="6001",ATTR{serial}=="A101LSVA",SYMLINK="ttyLancelot2"

When I tested it the serial A101LSVA corresponded to /dev/ttyUSB2 with board attached and working

However /dev/ttyLancelot2 always was symlinked  to /dev/bus/usb/003/026 or something and cgminer refused to work. When I manually symlinked /dev/ttyLancelot2 to /dev/ttyUSB2 all was fine. How to make udev to symlink to /dev/ttyUSBxx instead of /dev/bus/usb/xxx/xxx
10X

[spiccioli]

Guys,
I am tiring to map my lancelets to particular names in order to be able to know which cgminer ICAxx corresponds to which board. I am using xubuntu 12.04.
I have tried following (udev rules):
ATTR{idVendor}=="0403",ATTR{idProduct}=="6001",ATTR{serial}=="A101LSVA",SYMLINK="ttyLancelot2"

When I tested it the serial A101LSVA corresponded to /dev/ttyUSB2 with board attached and working

However /dev/ttyLancelot2 always was symlinked  to /dev/bus/usb/003/026 or something and cgminer refused to work. When I manually symlinked /dev/ttyLancelot2 to /dev/ttyUSB2 all was fine. How to make udev to symlink to /dev/ttyUSBxx instead of /dev/bus/usb/xxx/xxx
10X

loscia,

I did it like this for my CM1 boards:

https://bitcointalk.org/index.php?topic=78239.msg1091298;topicseen#msg1091298

spiccioli.

[loshia]

10X
That is what i was looking for:)
I will try it later and let you know the result!
Thank you
PS:

What do you think of HW err patch listed here?
https://bitcointalk.org/index.php?topic=78239.1760
Assuming i am having only ICA boards attached it can not brake anything right? And will count HW errors. Actually i applied it already and seems good.

[kano]

10X
That is what i was looking for:)
I will try it later and let you know the result!
Thank you
PS:

What do you think of HW err patch listed here?
https://bitcointalk.org/index.php?topic=78239.1760
Assuming i am having only ICA boards attached it can not brake anything right? And will count HW errors. Actually i applied it already and seems good.

... https://bitcointalk.org/index.php?topic=28402.msg1158924#msg1158924

[loshia]

spiccioli,
udev works charming:) you made my day thank you

kano,

I just cloned
https://github.com/kanoi/cgminer/

It turns out that if (hash2_32[7] != 0) means hw_error not like the patch i found:)
Share below target is not always hw_err right? Anyway thank you for your work. I am running your code right now and i will let you know how it goes. Bad thing is that i have HW errors counters>0 I am joking..I guess i have to live with them like everybody else here.
Everyone was talking abut HW error rate - % - Now i can calculate and graph it:)

Best

[spiccioli]

spiccioli,
udev works charming:) you made my day thank you

loshia,

you're welcome.

spiccioli

[kano]

spiccioli,
udev works charming:) you made my day thank you

kano,

I just cloned
https://github.com/kanoi/cgminer/

It turns out that if (hash2_32[7] != 0) means hw_error not like the patch i found:)
Share below target is not always hw_err right? Anyway thank you for your work. I am running your code right now and i will let you know how it goes. Bad thing is that i have HW errors counters>0 I am joking..I guess i have to live with them like everybody else here.
Everyone was talking abut HW error rate - % - Now i can calculate and graph it:)

Best

Yeah the catch now is that there are 2 tests required.

The first test is the simple one - all nonces returned by mining devices are 1 diff - so they MUST be "hash2_32[7] == 0"
If not - then yep that's a hardware error.
If it is '0' then it is not a hardware error.

The 2nd test is the difficulty level.
Now that pools are giving out >1 diff work, that 2nd test comes in to play - if that second test fails, it is simply just a normal share but not high enough difficulty - so no error.
e.g. with a 10 diff pool, 90% of the shares found by any mining device will be the wrong difficulty and thus ignored (but not an error)

Meanwhile My 2 Icarus after a bit over 2 days:

Code:

 cgminer version 2.7.5c - Started: [2012-09-05 13:15:08]
--------------------------------------------------------------------------------
 (5s):1395.4 (avg):1491.6 Mh/s | Q:3487  A:61173  R:406  HW:30  E:1754%  U:20.7/m
 TQ: 0  ST: 7  SS: 16  DW: 388  NB: 360  LW: 161062  GF: 18  RF: 9  WU: 20.9
 Connected to Nowhere with LP as user Miku
 Block: 0000015d263f4a611b3d1b72a98f5dfe...  Started: [14:22:16]
--------------------------------------------------------------------------------
 [P]ool management [G]PU management [S]ettings [D]isplay options [Q]uit
 GPU 0:  73.0C 3501RPM | 366.1/366.7Mh/s | A:14975 R: 97 HW: 0 U: 5.08/m I: 9
 GPU 1:  71.0C 2084RPM | 365.9/365.8Mh/s | A:14958 R: 92 HW: 0 U: 5.07/m I: 9
 ICA 0:                | 379.6/379.5Mh/s | A:15589 R:110 HW:18 U: 5.29/m
 ICA 1:                | 379.6/379.6Mh/s | A:15651 R:107 HW:12 U: 5.31/m

So I'm getting a bit under 0.1%

[loshia]

Kano,
I have noticed a couple things:
1. You are running both GPU and FPGA on your cgminer. Is it a good idea to have them both on single miner? Are there some potential problems because of that? Currently i am having two cgminers running - one with GPU disabled and icaurs enabled and second cgminer with GPU enabled and icaurs disabled
2. Your cgminer version is 2.7.5c is it just a string bumped up right? what i am asking is if https://github.com/kanoi/cgminer/ contains your latest code?
3. Your HW errors are a lot less than mines:) However i am not done with hardware setup yet - i have to polish it, Voltage drop of the second crappy PSU is big about 1.3 volts. I suspect some of the usb cables that came along with the usb hubs i bought. They just look like a pice of garbige compared to ngzang USB cables that came along with lancelots.  In general  my HW errors for all Lancelots are < 0.3%, but i have some boards with almost 3%. It is just one night run of course.

10X

[kano]

Cgminer is threaded - so it is actually better to run 1 cgminer than 2.

The threading basically means it's no real difference, however if your pool supports roll-n-time, it's better to have one cgminer talking to the pool than having 2 of them (see my E: 1754% value) - the rolling covers all 4 devices easily enough - whereas with 2 cgminers you will be getting twice as much work from the pool.

I do however, also run 2 cgminers - the 2nd one just has 1 BFL.
Since BFL's suck when it comes to dealing with LP's, I prefer to point that at a pool I know will get minimal Rejects

Yes 2.7.5c is my current git (I haven't added anything in the past 2 days) but I skipped 'b'
I always add letters on the end for my versions so I know where they came from (in this case it is 2.7.5 + my changes = my git master)
When I add more code before 2.7.6 comes out, it will become 2.7.5d or 2.7.5e or something like that
(I now only use 'a' for the Ubuntu 11.04 executable of each official release, that I make)

[loshia]

Thanks kano!
Just a side question. I am using bitminter for the moment. as far as i know roll-n-time will come shortly but there is no support for cgminer yet. Pool works great. Can you tell me which pool do you use with roll-n-time enabled for cgminer please? I hope it is not top secret of course:)

[kano]

Thanks kano!
Just a side question. I am using bitminter for the moment. as far as i know roll-n-time will come shortly but there is no support for cgminer yet. Pool works great. Can you tell me which pool do you use with roll-n-time enabled for cgminer please? I hope it is not top secret of course:)

At the moment, OzCoin and EMC

Oh  ... and in case you didn't realise ... the cgminer API command 'stats' will also tell you for each pool you have in your list that has done at least one getwork

[flynn]

Guy's
While waiting for ngzang Lancelot bitstream i wana play with one of my boards  and try different bitstreams. I just wana be prepared for the moment when ngzang will release the official bitstream. However i have never done that before. I have a couple of questions and i would be thankful to anyone who can give me some info:

1. I have Lancelot dev kit available.
2. Are the instructions published for Icarus http://en.qi-hardware.com/wiki/Icarus#Flash_by_using_iMPACT,  http://dl.dropbox.com/u/28686048/Icarus/prgm-fpga.png, https://github.com/ngzhang/Icarus/blob/master/Downloads/bitsteam/guide%20for%20flash%20update.txt good to be used with Lancelot?
2. Have someone tried https://github.com/ngzhang/Icarus/tree/master/Downloads/bitsteam/200MHz_for_test or https://github.com/ngzhang/Icarus/tree/master/Downloads/bitsteam/V4 with lancelot?
3. What other "unofficial" bitsreams are available for Lancelot
4. How can i flash "temporally" bitstreams - i mean mcs files. As far i understood flashing mcs do not last power off/on? Probably this is the bet way for me to try.
5. I am using cgminer 2.7.5

Thank you very much in advance

I am following the same path very slowly.

I have ngzhang's dev kit JTAG cable working - just follow the Xilinx instructions and under Linux you probably need this : http://rmdir.de/~michael/xilinx/

Connect the small board with a big white arrow on the xilinx JTAG cable, then connect the cable with the 7 colored wires to it.

Connect the loose wires to the Lancelot board in this order : from left: VCC/GND/TCK/TDO/TDI/TMS
that is, RED/BLACK/YELLOW/WHITE/PURPLE/GREEN   ignore the GREY wire (INIT)

Start IMPACT => you can see the two LX150;
I didn't dare downloading anything yet tho, I also wonder what is the exact bitstream currently running, my guess is https://github.com/ngzhang/Icarus/tree/master/Downloads/bitsteam/V3

[loshia]

flynn,
Thanks for the update. The wise thing we can do is to wait for ngzang instructions - personal opinion. I think if we do something wrong we can "kill" the boards . More over there are some switches on the pcb prog1 and prog2. I personally do not have enough knowledge to look at the pcb files and find out what they are used for.
If someone else has the guts to try it and share the info with us will be great;)

[ngzhang]

come to say i'm still alive.

and this is 40 64cycle cores @ ~4ns...



 

i must say the development process is a disaster, i never want to do it again.

[loshia]

I mast say that i am not an expert but it seems that there is a lot of room available to fill Apart of the joke i have red somewhere that some of the guys do use "self made" tools to be able to achieve big density. The info was here if i remember correctly but link is dead
http://www.bitfury.org/xc6slx150.html

[ngzhang]

I mast say that i am not an expert but it seems that there is a lot of room available to fill Apart of the joke i have red somewhere that some of the guys do use "self made" tools to be able to achieve big density. The info was here if i remember correctly but link is dead
http://www.bitfury.org/xc6slx150.html

yeah we also write a lot of private tools, in order to help us fight with stupid XILINX tool chain.