FPGA development board "Lancelot" - accept bitsteam developer's orders.

[luffy]

@ngzhang
have you checked this already?
https://bitcointalk.org/index.php?topic=88413.0

[ngzhang]

@ngzhang
have you checked this already?
https://bitcointalk.org/index.php?topic=88413.0

yep, but you know...
these fpgas are  tooooo small...

[seriouscoin]

@ngzhang
have you checked this already?
https://bitcointalk.org/index.php?topic=88413.0

yep, but you know...
these fpgas are  tooooo small...

You should apply to work for BFL.

They're looking for a Mandarin speaking engineer in Asia.

Please work for them.

[ngzhang]

@ngzhang
have you checked this already?
https://bitcointalk.org/index.php?topic=88413.0

yep, but you know...
these fpgas are  tooooo small...

You should apply to work for BFL.

They're looking for a Mandarin speaking engineer in Asia.

Please work for them.

NEVER EVER

[Dhomochevsky]

 

What if they say "Pretty please"?

[EnergyVampire]

sub

Added to Watchlist: https://bitcointalk.org/index.php?topic=90136.0

[exahash]

You should apply to work for BFL.

They're looking for a Mandarin speaking engineer in Asia.

Please work for them.

NEVER EVER

Thank goodness!

[disclaimer201]

You should apply to work for BFL.

They're looking for a Mandarin speaking engineer in Asia.

Please work for them.

NEVER EVER

Thank goodness!

Why should he work someone else? Butterfly Labs suck in comparison.

[CoinDiner]

First off    sorry for the thread hijack!

If anyone from Europe is thinking of getting some of these boards, and NOT using bitcoins to pay , can you let me know how you plan on paying.

Ta

[PawShaker]

You should apply to work for BFL.

They're looking for a Mandarin speaking engineer in Asia.

Please work for them.

NEVER EVER

Thank goodness!

Why should he work someone else? Butterfly Labs suck in comparison.

Please, stay freelance. I do belive in distribution and not concentration of power. Yes, when talented people get together they can create oustanding gifts to the humanity... or dominate the world. For instance I can live without "personal computer", "mouse", "iPhone". I apreciate significance of any of these breakthroughs but none of them is wotrth sacrificing beeing free. The leader is gone, but his company continoues the work of global domination.

[seriouscoin]

@ngzhang
have you checked this already?
https://bitcointalk.org/index.php?topic=88413.0

yep, but you know...
these fpgas are  tooooo small...

You should apply to work for BFL.

They're looking for a Mandarin speaking engineer in Asia.

Please work for them.

NEVER EVER

First, never say never ....oops

Second, we want you to work for BFL so we can have correct info and not BS crap. I'm sure they cant do jack to you because you're in China.

Work for them so you can build better products *HINT HINT*

[Turbor]

First off    sorry for the thread hijack!

If anyone from Europe is thinking of getting some of these boards, and NOT using bitcoins to pay , can you let me know how you plan on paying.

Ta

He has a bank account. Wire transfer works very well.

[ngzhang]

@ngzhang
have you checked this already?
https://bitcointalk.org/index.php?topic=88413.0

yep, but you know...
these fpgas are  tooooo small...

You should apply to work for BFL.

They're looking for a Mandarin speaking engineer in Asia.

Please work for them.

NEVER EVER

First, never say never ....oops

Second, we want you to work for BFL so we can have correct info and not BS crap. I'm sure they cant do jack to you because you're in China.

Work for them so you can build better products *HINT HINT*

bank transfer or paypal is acceptable.
or MTGOX$ redeem code

[rph]

ASICs will fuck all FGPAs to shit.

Only if it's full custom below ~90nm, which means several million dollars in mask costs, a 6-9 month
mfg period, and a pretty good chance that the first chip is useless, unless you know WTF you are
doing and poached a rockstar team of people making $200k+/yr away from companies like
Broadcom, Marvell, Intel, etc. And managed to convince your investors they wouldn't be better
off funding something else for a larger / lower risk market.

Given the odds of BFL pulling that off - I'm going to keep buying FPGAs.
I will fear a true full custom mining ASIC if/when it exists, but the FPGAs
will certainly have paid for themselves way before then.

-rph

[rjk]

Would you agree though, rph, that SHA256 is quite a bit simpler than most designs, and therefore is (even slightly) less likely to need several respins before a good wafer is produced?

[rph]

It helps but logic/RTL verification is one of the easiest steps in a modern ASIC design.
The lower level physical/analog design is what fucks over most amateur ASIC designs.

-rph

[rjk]

It helps but logic/RTL verification is one of the easiest steps in a modern ASIC design.
You derisk that by using - guess what - FPGAs. The lower level physical/analog design
is what fucks over most amateur ASIC designs.

-rph

I see, so the person or company that is designing an ASIC really is responsible for the entire thing, it isn't as simple as handing some completed HDL over to a company who will then interpret them into their process and print some chips.

[2112]

Only if it's full below ~90nm, which means several million dollars in mask costs, a 6-9 month
mfg period, and a pretty good chance that the first chip is useless, unless you know WTF you are
doing

This is a gross overestimate. The folded, not-unrolled design is basically a two 32-bit-wide shift registers with some multi-input adders in a feedback and an adder-comparator on the output. The remaining logic is all standard cells: PLL, ROM and I/O.

SHA-256 is pretty much self-testing: there are no unreachable states and all every state is observable. Any internal fault will eventually show up on the outputs.

The lower level physical/analog design is what fucks over most amateur ASIC designs.

And again dual SHA-256 is a dream assignment for the beginners. It is small and it takes only about 64 or 128 simulated clocks to verify the entire custom circuitry. From my past experience with SPICE and BSIM4 I would venture to guess that I could simulate one clock cycle of an entire SHA-256 round on my Core2Duo laptop in one day.

The additional benefit for the team is that they have design closure achieved from the moment they pass automated DRC verification. All timing and power targets are soft, they have absolutely no interoperability requirements and any hard targets for timing closure or power closure. All they have to do is pick an  internal clock generation cell with variable multiplier.

I would guess that the chances of a "zero yield" first spin are atypically low for this design.

[hardpick]

Only if it's full below ~90nm, which means several million dollars in mask costs, a 6-9 month
mfg period, and a pretty good chance that the first chip is useless, unless you know WTF you are
doing

This is a gross overestimate. The folded, not-unrolled design is basically a two 32-bit-wide shift registers with some multi-input adders in a feedback and an adder-comparator on the output. The remaining logic is all standard cells: PLL, ROM and I/O.

SHA-256 is pretty much self-testing: there are no unreachable states and all every state is observable. Any internal fault will eventually show up on the outputs.

The lower level physical/analog design is what fucks over most amateur ASIC designs.

And again dual SHA-256 is a dream assignment for the beginners. It is small and it takes only about 64 or 128 simulated clocks to verify the entire custom circuitry. From my past experience with SPICE and BSIM4 I would venture to guess that I could simulate one clock cycle of an entire SHA-256 round on my Core2Duo laptop in one day.

The additional benefit for the team is that they have design closure achieved from the moment they pass automated DRC verification. All timing and power targets are soft, they have absolutely no interoperability requirements and any hard targets for timing closure or power closure. All they have to do is pick an  internal clock generation cell with variable multiplier.

I would guess that the chances of a "zero yield" first spin are atypically low for this design.

I think what you are saying is a sha-256 asic is fairly simple and they should get it right the first time ?

[kano]

Only if it's full below ~90nm, which means several million dollars in mask costs, a 6-9 month
mfg period, and a pretty good chance that the first chip is useless, unless you know WTF you are
doing

This is a gross overestimate. The folded, not-unrolled design is basically a two 32-bit-wide shift registers with some multi-input adders in a feedback and an adder-comparator on the output. The remaining logic is all standard cells: PLL, ROM and I/O.

SHA-256 is pretty much self-testing: there are no unreachable states and all every state is observable. Any internal fault will eventually show up on the outputs.

The lower level physical/analog design is what fucks over most amateur ASIC designs.

And again dual SHA-256 is a dream assignment for the beginners. It is small and it takes only about 64 or 128 simulated clocks to verify the entire custom circuitry. From my past experience with SPICE and BSIM4 I would venture to guess that I could simulate one clock cycle of an entire SHA-256 round on my Core2Duo laptop in one day.

The additional benefit for the team is that they have design closure achieved from the moment they pass automated DRC verification. All timing and power targets are soft, they have absolutely no interoperability requirements and any hard targets for timing closure or power closure. All they have to do is pick an  internal clock generation cell with variable multiplier.

I would guess that the chances of a "zero yield" first spin are atypically low for this design.

So, in this arena - price wise what would be a very reasonable estimate of how much it would cost BFL?
(so I know if the major effort to very slightly possibly invalidate sha256 would be worth the while to kill their company)