Swedish ASIC miner company kncminer.com

[kano]

They are approx 0.086 BTC per Avalon chip and €80 to assemble ten to an open source board, and €100 to assemble 20.

Chips are rated at 282 Mh/s each. Not too sure where you've got 2.0-2.5 BTC for 10 from?!

So thats €280 for 5.64 Ghash

About 700,000 chips on order??  5.64 Ghash x 35,000 in a few months.  Is that right?

No, man your addition sucks, that's just the chips as it states clearly above. Then you have 100 Euros if they decide to do the double sided boards or 160 if just the 10 chips per board, plus housing and psu. On top of which you're sending anonymous currency to people you don't know on a bulletin board to buy the chips and then have them send that to another anonymous person in another country to assemble the unit.

But then by August/September who knows what offers will be available.

One things for sure, the BFL crowd won't be making anything like they envisaged.

However, they will be making something ... unlike here as far as they have given details so far.
My BFL Jalapeno is currently mining at 5.368Gh/s on a rpi (faster on my desktop) with cgminer
The one I ordered cost ... $187 ... with shipping.
They are now priced at $274 ...

Kano -
You make the BFL alternative sound so reasonable.  I would venture to say that your experience with BFL and the microsingle is atypical.  The experience of a new pre-order buyers at $274 would expect something very different (in terms of shipping time).

I've got no idea when BFL will ship if you order today.
The Jalapeno does, however, already exist and will be shipping in quantity soon.

Here we have a couple of guys who have never made bitcoin hardware before and have 2.25 months left to meet their 'few months' they said in the opening.
That few months isn't going to happen.
Then to top it off they say they are 'going' to sell a device for roughly 10x the price what BFL is shipping soon.

As has been stated before, if they were really trying to make these things and were going to meet a deadline in a little over 2 months from now, they would be providing details about what they are doing.
They don't have any 'great' secrets that will give any competitor an advantage.
Their great secret really simply means turning customers away. Pure and simple.

There's no reason for them to hide, unless they have something to hide ......

[zedicus]

DO NOT SEND $. THIS COMPANY HAS THE TRAITS OF A SCAM.
------------------------------------------------------------

May cause massive anxiety, weight loss, migraines, instant account draining, reverse thinking, tongue seizure, dry mouth, digital suicide, tooth grinding, kidney stone, indefinite toe cramp and blood loss from the nose. If you need immediate support do not call the manufacturer.  If you need support on their invisible product line. . be prepared to downgrade to a 3 year old model so you can get in que for support on one of the products that doesnt exists.








 

[Phinnaeus Gage]

Thanks to this now locked thread...

Re: Butterfly Labs
Today at 04:30:17 AM                                                                                               #93

Thanks, I wasn't aware that I could do that. I thought it was a mod only feature. Here is an article proving one of my points btw http://www.edn.com/design/integrated-circuit-design/4313790/Making-ASIC-power-estimates-before-the-design.

Follow the provided link above to read more of which I included the first three paragraphs to whet your whistle.

ASIC design teams face a growing problem. ASIC power-consumption estimates that take place before the design phase lack both scope and credibility. These shortcomings affect process, design, and IP (intellectual-property) selection. As the design complexity increases and power-consumption requirements tighten, this problem becomes more pervasive, often causing design rework, schedule slippage, higher NRE (nonrecurring-engineering) costs, and other challenges.

To address these issues, engineers should use a structured approach and a set of heuristic power-estimation rules for making effective predesign ASIC power estimates. Given that IC design flows and design requirements differ greatly, you may need engineering judgment and creativity to extend this approach across a range of design situations. In any event, these concepts should provide a good starting point. Companies that outsource portions of their ASIC design flows should engage early with their ASIC design partners to improve the quality of their predesign power estimates.

From an analytical viewpoint, generating power-consumption estimates should be straightforward. However, predesign power estimation is often given a low priority and may rely on the wrong mix of people to support the effort. In general, the team responsible for process, IP, and design selection should also own the predesign power estimates. This team will need augmentation if it is too distant from the design-implementation effort or if it has little hands-on power-estimation experience. For example, a software-centric architect plus a continually distracted manager will probably generate inadequate predesign ASIC power estimates, causing suboptimal process, design, and IP selection. That team needs designers with hands-on experience, and it may also need to include low-power-design experts from the ASIC design partner. The structured approach lends itself to distributing tasks and recombining results so that team members can share the workload.

[Bitcoinorama]

Wow, surely you should have sent that last post to BFL_Josh a while back!

Not having a dig by any means, but word for word, that appears to be their precise issue to date. (BFL)

Will have to see what KNCMiner come up with (as in design spec AND working prototype), all I will add is that I was in communication with Sam all day yesterday and he comes across as reasonable, proactive and open-minded to ideas. His responses were positive and timely. He even responded to a suggestion I sent at 3am GMT, which surprised me as I chatted to him yesterday afternoon (GMT), so they are certainly burning the midnight oil at the weekend.

For now, I won't say what I suggested as I want to see if it will actually happen, but he said it's an idea he will take seriously, so we'll see...

Certainly they have given us names to all involved and the faces behind the names are idenfiqble through LinkedIN and have relevant computer science and engineering expertise as well as a reputable chip manufacturer capable of production without third party logistical hiccups.

The price is only worthwhile if the product is in the hands of the customers before the competition (including DIY) catches up...

[dan99]

Wow, surely you should have sent that last post to BFL_Josh a while back!

Not having a dig by any means, but word for word, that appears to be their precise issue to date. (BFL)

Will have to see what KNCMiner come up with (as in design spec AND working prototype), all I will add is that I was in communication with Sam all day yesterday and he comes across as reasonable, proactive and open-minded to ideas. His responses were positive and timely. He even responded to a suggestion I sent at 3am GMT, which surprised me as I chatted to him yesterday afternoon (GMT), so they are certainly burning the midnight oil at the weekend.

For now, I won't say what I suggested as I want to see if it will actually happen, but he said it's an idea he will take seriously, so we'll see...

Certainly they have given us names to all involved and the faces behind the names are idenfiqble through LinkedIN and have relevant computer science and engineering expertise as well as a reputable chip manufacturer capable of production without third party logistical hiccups.

The price is only worthwhile if the product is in the hands of the customers before the competition (including DIY) catches up...

Well, I hope he really listen and make changes ... but time is catching up and time don't wait.. or can be reverse back

[FlappySocks]

Well I am willing to give these guys a chance if the ROI stacks up before the DIYers come online (and I have invested in DIY too).

I think some folk are underestimating what the wholesale Avalon chip sale is going to do to the difficulty level when it comes online.  BFL customers that don't get their kit in the next couple of months are going to loose their ROI.

The next race is to produce an ASIC that is an order of magnitude more efficient that the Avalon ASICs.

[Bitcoinorama]

Which is what I hope these guys understand. It's a tough one; they have to produce a product multiple times more powerful than the current offering for a better price and make it more efficient to run(be it clocked or less power hungry or both) to offer any longevity and ROI as well as potential profit.

BFL's downfall has been the absolutely bizarre intention to put aesthetic design before function. They are now left with a huge amount of redundant cases they paid for with investor money and now at last minute have had to perform a complete design overhaul at further expense and time. Irrespective of whether they return any profit to their customers BFL and those involved with the project have banked and have created a 'successful product and company' in terms of their careers, although investors may not share the same sentiment. Thanks to their aggressive marketing campaign coupled with mainstream media exposure they will be receiving customer orders for the foreseeable future even with their now inflated prices. Those new customers are unlikely to see a return if they order now and BFL deliver the new orders in their current expected timeframe. It's just beyond me why they thought aesthetics even remotely come into what is potentially a product with such a finite timeframe of purposeful use. It's not as if it does anything so worthy of putting on display and staring at it, but people actually chose to preorder it based on looks, so essentially there's my answer.

Avalon's entire purpose has been to disrupt any centralisation without the desire to profit. That latter part is BS; they are, and have been profiting comfortably from this venture, but their intention to ensure decentralisation is valid.

KNCMiner carry people with industry experience, but will also have investors knowledgeable of the BFL customer experience, savvy enough to create their own DIY products in due course unless KNCminer can create a compelling reason otherwise, cautious and unkeen to share the same BFL/bASIC experience which is why working prototypes mean everything. The fact that ORSoC are involved means a prototype should be justifiably feasible to produce prior to requesting funds. They have the kit, the set-up and the people in house. Whatever they do they have to be realistic with respect to expectations of what can be achieved and definitely by what timeframe they can be in the hands of their customers. Furthermore, they must acknowledge the number of DIY chips Avalon is flooding the market with in that timeframe and the subsequent effect they may have on difficulty. There is no excuse for this. KNCMiner raised their intentions to produce at the exact same time as Avalon's notice to sell bulk chips so this cannot be being ignored. Bottom line, people want to support Bitcoin and all it stands for, but they also want to profit from their time and expense.

European customers desperately need a solid offering though. Paying import fees from outside the EU (approx 30% for orders above $135 to the UK - 20% VAT and a bizarre new levy of 9% on top of the full VAT included value for orders over $135 dollars plus shipping) is not fun!

[Beepbop]

What's so special about this FPGA that it can mine anything other than a sha256(sha256()) coin?

A Field Programmable Gate Array (FPGA) can be reprogrammed into doing almost anything you want it to do. If the printed circuit board around it doesn't support your new application, you can still re-use the FPGA.

An Application Specific Integrated Circuit (ASIC) is locked into doing only one thing. It's not field programmable.

So yeah, an FPGA miner probably has higher reuse value than an ASIC.

[Bitcoinorama]

These days with electronics the purpose of engineering design is to design products with the intention to reuse, recondition, or recycle. I would like to assume the current producers of ASIC miners have designed products with the intention to harvest parts once they reach their end of functional life cycle, or at least point customers in the right direction as to where their redundant tech may be beneficial; i.e. assisting research into curing disease etc. There are certainly uses beyond Bitcoin that need to be considered for social entrepreneurs.  

[HjerterEss]

How come these guys never respond to any of my emails?

[Bitcoinorama]

Wrong email addy? I used one someone posted here as opposed to the site contact form. That's probably swamped with all manner or BS questions. Also keep your Q's on point, constructive and brief, that's just common sense.

Best, A.

 

[thomashrev89]

How come these guys never respond to any of my emails?

Sam answered me after 10 min.

[HjerterEss]

Maybe I sent my email to the wrong adress or something then. I used the adress found on their website.

[organofcorti]

What's so special about this FPGA that it can mine anything other than a sha256(sha256()) coin?

A Field Programmable Gate Array (FPGA) can be reprogrammed into doing almost anything you want it to do. If the printed circuit board around it doesn't support your new application, you can still re-use the FPGA.

An Application Specific Integrated Circuit (ASIC) is locked into doing only one thing. It's not field programmable.

So yeah, an FPGA miner probably has higher reuse value than an ASIC.

But that's not something the average customer can do is it? So retail value won't be that much better.

[dan99]

How come these guys never respond to any of my emails?

Sam answered me after 10 min.

He does answer but won't listen to your suggestions and comments that is kind of sad ya...

[kano]

...
The next race is to produce an ASIC that is an order of magnitude more efficient that the Avalon ASICs.

Lulz - you do realise the ASIC chip in the Avalon is only max setting 300Mh/s right? That's why they have 240 of them ...
The BFL chip in the first Jalapeno is > 2.5GH/s - 2 of them make more than 5GH/s (already)

[mwarrior]

Wowzers.  Trying to catch up and my brain hurts.  So is there no advantage to being one of the first 500 to sign up for this?  50+ GH/s sounded great... but this sure leaves a lot of questions.  After reading all the posts I guess the 60 GH/s device isn't happening? Bitcoin price is still way unstable and who knows where it will end up.  I managed to land #355 of the 1-500 which I guess is moot?  Probably need to stick with trading.  Damn coins.

[kano]

What's so special about this FPGA that it can mine anything other than a sha256(sha256()) coin?

A Field Programmable Gate Array (FPGA) can be reprogrammed into doing almost anything you want it to do. If the printed circuit board around it doesn't support your new application, you can still re-use the FPGA.

An Application Specific Integrated Circuit (ASIC) is locked into doing only one thing. It's not field programmable.

So yeah, an FPGA miner probably has higher reuse value than an ASIC.

But that's not something the average customer can do is it? So retail value won't be that much better.

... and, as an example, they'd need to add RAM to it to be able to design and run scrypt mining (litecoin)
... and it's not just go to your local shop and buy some RAM either ...

sha256 uses hardly any memory - it's very different to most other applications in more than one way

The biggest one, in BTC's use of it, is that it needs to do 4 billion iterations to find 0 or more (average 1) results on almost the same data set.
The input (and output) is very simple and very small compared to the work done.

[opentoe]

$ 2,795.00 for 6 GH FPGA? Hmmm 
$ 7,000.00 for 250 GH ASIC(?) seems much better deal...

That can't be correct. $3000 for 6GH? And it's not even an ASIC? I don't get it.

[opentoe]

Hashrate will hit 60 mil this summer, the fgpa miner might not get much btc

"might not" ? You mean NOT ANY.