ASICMINER: Entering the Future of ASIC Mining by Inventing It

[jjiimm_64]

Are the chips working??

[memvola]

Are the chips working??

It was explained in the latest update:

Update

The samples passed all functionality tests. The power consumption is also within the expected range. And as our overclocking tests had shown, they still have a lot of potentials compared to our original spec. This means that the biggest risk of our project is gone and our NRE is a fruitful spend.

[jjiimm_64]

Are the chips working??

It was explained in the latest update:

Update

The samples passed all functionality tests. The power consumption is also within the expected range. And as our overclocking tests had shown, they still have a lot of potentials compared to our original spec. This means that the biggest risk of our project is gone and our NRE is a fruitful spend.

No sir...  That says they passed some tests..  I am asking  Are the chips working?

[Transisto]

Can someone with a seat on the board say if they're getting more update than that ?

As someone with more than half the requirement I'd like some more updates, like ETA, in PM or otherwise.

[zefir]

Can someone with a seat on the board say if they're getting more update than that ?

Nope, so far board members do not have more info than what is provided in this thread. Hope friedcat and team are busy getting those chips operating (or acquiring BTCFPGA )...

[SebastianJu]

Are the chips working??

It was explained in the latest update:

Update

The samples passed all functionality tests. The power consumption is also within the expected range. And as our overclocking tests had shown, they still have a lot of potentials compared to our original spec. This means that the biggest risk of our project is gone and our NRE is a fruitful spend.

No sir...  That says they passed some tests..  I am asking  Are the chips working?

And what do you think are the function of the chips? Mining isnt it? So if they passed all functionality tests that means to me that they do what their function is. What do you think does this mean?

[DutchBrat]

I also dont think Friedcat would say the NRE is a fruitful spend if the chips are not capable of hashing....

That being said the first ASIC should be online by now (been 5days since his update) and the fact that he hasnt made a big announcement about the first ever ASIC hashing away looking for a bitcoin block, makes me afraid that they might have run into some other problems....

Hopefully Friedcat will update us again tonight as he usually does (on a thursday morning)

[MrTeal]

I also dont think Friedcat would say the NRE is a fruitful spend if the chips are not capable of hashing....

That being said the first ASIC should be online by now (been 5days since his update) and the fact that he hasnt made a big announcement about the first ever ASIC hashing away looking for a bitcoin block, makes me afraid that they might have run into some other problems....

Hopefully Friedcat will update us again tonight as he usually does (on a thursday morning)

Doing all the board assembly and testing, then building them into rigs and commissioning the system might be taking a little longer than expected (not sure on their original timeline), but this kind of operation isn't like getting a single in the mail and plugging it in.

[repentance]

That being said the first ASIC should be online by now (been 5days since his update) and the fact that he hasnt made a big announcement about the first ever ASIC hashing away looking for a bitcoin block, makes me afraid that they might have run into some other problems....

For goodness sake.  When he first posted pictures of the chips he was talking about the next steps taking 2-3 weeks. 

[DutchBrat]

I also dont think Friedcat would say the NRE is a fruitful spend if the chips are not capable of hashing....

That being said the first ASIC should be online by now (been 5days since his update) and the fact that he hasnt made a big announcement about the first ever ASIC hashing away looking for a bitcoin block, makes me afraid that they might have run into some other problems....

Hopefully Friedcat will update us again tonight as he usually does (on a thursday morning)

Doing all the board assembly and testing, then building them into rigs and commissioning the system might be taking a little longer than expected (not sure on their original timeline), but this kind of operation isn't like getting a single in the mail and plugging it in.

Wouldnt it be wise to build one rig, to see how it all works in real life, before assembling all of the available chips into rigs.

They had the 2 strips of chips, build 1 or more rigs out of those, let them run fir a while, see if it works as expected and then have the remainder built....

It is not like getting a single in the mail, more like building one....

But i am probably too impatient 

[DutchBrat]

That being said the first ASIC should be online by now (been 5days since his update) and the fact that he hasnt made a big announcement about the first ever ASIC hashing away looking for a bitcoin block, makes me afraid that they might have run into some other problems....

For goodness sake.  When he first posted pictures of the chips he was talking about the next steps taking 2-3 weeks. 

I am not expecting 6 TH to be online this instant, am talking about the first test rig to be online.... If 6 TH takes 3 weeks, one rig should be done in 1 week dont you think

[kano]

That being said the first ASIC should be online by now (been 5days since his update) and the fact that he hasnt made a big announcement about the first ever ASIC hashing away looking for a bitcoin block, makes me afraid that they might have run into some other problems....

For goodness sake.  When he first posted pictures of the chips he was talking about the next steps taking 2-3 weeks. 

I am not expecting 6 TH to be online this instant, am talking about the first test rig to be online.... If 6 TH takes 3 weeks, one rig should be done in 1 week dont you think

Producing the board will be the majority of the time, it's not got to do with the number of TH/s, it's to do with creating that piece of hardware.
So when you divide 6TH/s by 6 it doesn't make developing the board 6 times faster

[SebastianJu]

That being said the first ASIC should be online by now (been 5days since his update) and the fact that he hasnt made a big announcement about the first ever ASIC hashing away looking for a bitcoin block, makes me afraid that they might have run into some other problems....

For goodness sake.  When he first posted pictures of the chips he was talking about the next steps taking 2-3 weeks. 

I am not expecting 6 TH to be online this instant, am talking about the first test rig to be online.... If 6 TH takes 3 weeks, one rig should be done in 1 week dont you think

Producing the board will be the majority of the time, it's not got to do with the number of TH/s, it's to do with creating that piece of hardware.
So when you divide 6TH/s by 6 it doesn't make developing the board 6 times faster

What i dont understand is... friedcat spoke about to create the hardware as far as one can. Bitfountain had the plan for the chips, their size and all pins. That means its absolutely doable to create the PCB and create the plastic cover for the whole asic. When the chips come you only have to put them into the PCB and everything is running.
It obviously didnt happen this way. Why?

[Digigami]

That being said the first ASIC should be online by now (been 5days since his update) and the fact that he hasnt made a big announcement about the first ever ASIC hashing away looking for a bitcoin block, makes me afraid that they might have run into some other problems....

For goodness sake.  When he first posted pictures of the chips he was talking about the next steps taking 2-3 weeks. 

I am not expecting 6 TH to be online this instant, am talking about the first test rig to be online.... If 6 TH takes 3 weeks, one rig should be done in 1 week dont you think

Producing the board will be the majority of the time, it's not got to do with the number of TH/s, it's to do with creating that piece of hardware.
So when you divide 6TH/s by 6 it doesn't make developing the board 6 times faster

What i dont understand is... friedcat spoke about to create the hardware as far as one can. Bitfountain had the plan for the chips, their size and all pins. That means its absolutely doable to create the PCB and create the plastic cover for the whole asic. When the chips come you only have to put them into the PCB and everything is running.
It obviously didnt happen this way. Why?

Likely because if the chips had failed the preliminary test, a redesign may have required pinout changes or supporting circuit designs. In which case we would have spent money on a handful of useless boards.

[MrTeal]

It doesn't make sense to have the boards fully populated and then add the ASICs. You'd have to reflow the boards twice, and there's no reason for that. Maybe Friedcat will confirm, but I would guess that they had the PCBs and stencil ready to go, and will now fully populate the boards. This would be similar to Avalon, where they designed the PCB and tested it with simulated signals prior to the arrival of the ASICs.

[kjj]

It doesn't make sense to have the boards fully populated and then add the ASICs. You'd have to reflow the boards twice, and there's no reason for that. Maybe Friedcat will confirm, but I would guess that they had the PCBs and stencil ready to go, and will now fully populate the boards. This would be similar to Avalon, where they designed the PCB and tested it with simulated signals prior to the arrival of the ASICs.

This, reflow.  Boards with surface mount devices are rarely (never?) half-made.  And sadly, if the board has small packages, it can be extremely difficult to crank one out by hand.  The QFN 40 package they showed is nearly impossible to do by hand.  Watch this video.  Note that the board they are actually working on is totally bare, regardless of what they say about kapton tape.

One thing that they can do just to validate the chip is to build a second board design with sockets.  ZIF sockets for MLP packages like the QFN 40 are expensive, like hundreds of dollars each expensive.  Unless they spent thousands on sockets, the blip from them testing will be lost in the poisson noise that dominates all of our short range hash speed estimates.

Building a one or two chip socketed board seems prudent, and I suspect that they did.  But of course, I have no more information than anyone else here.

[HorseRider]

Another friend of mine is interested in betting a small amount money on ASICMINER shares after I talked to her about this project yesterday. If any one is interested in selling them, please PM me the number of shares and the price.

[friedcat]

Update

It doesn't make sense to have the boards fully populated and then add the ASICs. You'd have to reflow the boards twice, and there's no reason for that. Maybe Friedcat will confirm, but I would guess that they had the PCBs and stencil ready to go, and will now fully populate the boards. This would be similar to Avalon, where they designed the PCB and tested it with simulated signals prior to the arrival of the ASICs.

In fact we have two pcbs. One for testing and one for mining. The latter is also a demo-version with respect to the first batch, because besides mining it will be used for profiling (mainly heat dissipation) to make our mass production stage better. The pcbs for testing are single-chip ones that are not modular, but it's simple enough that we could make hand fixes when anything goes wrong. It helped us much in determining and fixing a lot of small problems.

While the pcb for mining inhabits many chips, and are modular in a sense that controllers and dc/dc adapters are pluggable and replaceable. They should be are a being assembled with chips and other components by our assembly service with outsourcing contracts.

What we have done in the past week:

1. Making order and sending the pcbs, chips and other components to the assembly service.
2. Negotiating for the final renting contracts with workshop-typed land providers.
3. Dealing with mechanical parts (mining device holders, heatsinks, fans and air-conditioning).
4. Placing the mass production order to the chip foundry and making the first part of payment.
5. Getting noticed that the rest 6 wafers of the first batch in the foundry have only 6 layers left.

Thanks for all shareholders' patience and we are also very eager to have our devices mining. The service for pcb mass production and assembly has a very effective production line and responds very quickly to us, thanks to the glow competition of small and medium electronic businesses in Shenzhen.

In addition, if we are lucky enough, other current and potential mining device producers, if they ever have any step of production outsourced to Chinese businesses, will be delayed by the Chinese New Year (Feb. 10). It will be a long vacation (typically 7 days, plus a prior week and a succeeding week of low working efficiency from holiday syndrome and some of the employees' annual vacation-New Year vacation requirements).

[🏰 TradeFortress 🏰]

Update

It doesn't make sense to have the boards fully populated and then add the ASICs. You'd have to reflow the boards twice, and there's no reason for that. Maybe Friedcat will confirm, but I would guess that they had the PCBs and stencil ready to go, and will now fully populate the boards. This would be similar to Avalon, where they designed the PCB and tested it with simulated signals prior to the arrival of the ASICs.

In fact we have two pcbs. One for testing and one for mining. The latter is also a demo-version with respect to the first batch, because besides mining it will be used for profiling (mainly heat dissipation) to make our mass production stage better. The pcbs for testing are single-chip ones that are not modular, but it's simple enough that we could make hand fixes when anything goes wrong. It helped us much in determining and fixing a lot of small problems.

While the pcb for mining inhabits many chips, and are modular in a sense that controllers and dc/dc adapters are pluggable and replaceable. They should be are a being assembled with chips and other components by our assembly service with outsourcing contracts.

What we have done in the past week:

1. Making order and sending the pcbs, chips and other components to the assembly service.
2. Negotiating for the final renting contracts with workshop-typed land providers.
3. Dealing with mechanical parts (mining device holders, heatsinks, fans and air-conditioning).
4. Placing the mass production order to the chip foundry and making the first part of payment.
5. Getting noticed that the rest 6 wafers of the first batch in the foundry have only 6 layers left.

Thanks for all shareholders' patience and we are also very eager to have our devices mining. The service for pcb mass production and assembly has a very effective production line and responds very quickly to us, thanks to the glow competition of small and medium electronic businesses in Shenzhen.

In addition, if we are lucky enough, other current and potential mining device producers, if they ever have any step of production outsourced to Chinese businesses, will be delayed by the Chinese New Year (Feb. 10). It will be a long vacation (typically 7 days, plus a prior week and a succeeding week of low working efficiency from holiday syndrome and some of the employees' annual vacation-New Year vacation requirements).

Thanks for the update! Just want to make sure, you honor transfers of ASICMINER shares right?

[MPOE-PR]

That being said the first ASIC should be online by now (been 5days since his update) and the fact that he hasnt made a big announcement about the first ever ASIC hashing away looking for a bitcoin block, makes me afraid that they might have run into some other problems....

For goodness sake.  When he first posted pictures of the chips he was talking about the next steps taking 2-3 weeks. 

The PCB's out and tested using artificial signals (using a software-controlled source of signal to simulate the chips). The place for our first batch's deploying is also located. The first chip starting mining will be very early if the chips are correct (no more than a week after we get the chips), but the whole 12TH/s of our first batch would be online incrementally.

The chips were gotten on the 28th, one week from then was one week ago.

The next item on the checklist is

samples sent to community