I have never taped out a thing in my life either, and my experience with the industry is image sensors, not asics, and not even from design POV. Most of the steps will be similar, but lets not waste time going over that. I am not a rocket scientist either, and cant tell you all the steps involved in launching a rocket and docking it with the space station. I can tell you you almost certainly cant do it 6 weeks if you start from scratch. Simply deducting from common sense how long it took others.
First of all, common sense is actually a pretty terrible way to figure things out. You either do research and find out, or admit you don't know and don't care enough to bother finding out.
Only NASA, The Russians, and Space X have ever built rockets that carried capsules that have docked with the space station. I wouldn't even try to guess how many people have designed integrated circuits.
Either way, you didn't claim it would take a long time to design a chip. You said it would take nine months between
when the process node size was fixed and couldn't be changed, and when the chips were ready for use.
Now, apparently you're telling me you have no idea
why that would be the case, other then "Common sense".
Switching the process node would be more like adjusting the payload capacity of a rocket. While it's still in the blueprint phase before construction begins. Could you decide you need 5 engines instead of 4 six weeks before construction starts? Or even after construction has begun?
The design for the Saturn V rocket was changed from four engines to five - It didn't take six weeks, but this was all done with pencil, paper and slide rules, no CAD, no computers at all.
TheSeven said he was using a hardware description language to generate the chips. I don't exactly know what it is that would make it
take longer to generate, for example, a 40nm chip design compared to 65nm chip. Or why it would take 6 months to do a die shrink. As far as I know the only difference is how much the intermediary companies and fab charge you to actually do the tapeout.
How long did it take between the time bitfury settled on a 55nm design for them to have working silicon?
I dont know, but I do know bitfury raised the idea of developing his own asic back in may of 2012, I know they taped out in March this year, had prototypes hashing in July and have only recently been shipping in volume.
I might also add, if Bitfury was involved in this project, Id probably have bought in.
But the question is, what was the latest they could have switched to a different feature size.
Anyway, your argument seems to be they may be further ahead in the design and closer to tapeout that Im willing to believe, and that may be so. But you should be asking Theswede for evidence of that rather than asking me to prove the negative. Everything I have seen so far points towards little more than vague ideas and not being anywhere near tape out. In fact, Ive not seen anything that leads me to believe there will ever be one "rev2". TheSeven has recently been contracted to do "some work". Fine, but my guess is that he has been asked to come up with some numbers, rough projections. If that had already been done, wouldnt we have heard them? So he is probably not doing more a preliminary feasibility study, One that should lead to canceling this whole project, if there ever was one. And if it doesnt, you can go by any of the other bitcoin asics to get an idea of when it could realistically be deployed. Not this year, that much Im very confident off. Next summer seems a lot more plausible and financially unfeasible.
I don't know where they are in their design. I don't know what steps they need to go through between having having a verilog codebase they can simulate and having a GDSII file or mask set that they can use to produce chips, how long those steps take, how much they cost, etc for various process nodes.
But there doesn't seem to be much basis for saying that the process node needs to be fixed 9 months before chips finish.
