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Author Topic: 1GH/s, 20w, $500 — Butterflylabs, is it a scam?  (Read 116544 times)
DeathAndTaxes
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Gerald Davis


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November 26, 2011, 04:41:00 PM
 #841

For future reference, what is the best method to use for removing heatsinks that have been attached with thermal glue (instead of using thermal grease and holding them on with screws)?

Remove the screws (obviously).  Then twist 90 degrees.  That should break enough of the adhesion to allow you to remove the heatsink. If the heatsink isn't significantly loser you likely will need to try again.  I have done it plenty of times on things like northbridge heatsinks but kinda scary doing it on a $500 board.

NEVER pull hard straight upward.  Until you break the adhesion you have a good chance of ripping the solder joints right from the board.
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November 26, 2011, 04:45:09 PM
 #842

...but kinda scary doing it on a $500 board...

My point exactly  Grin

The freezer trick sounds like it ought to work too.

Mining Rig Extraordinaire - the Trenton BPX6806 18-slot PCIe backplane [PICS] Dead project is dead, all hail the coming of the mighty ASIC!
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November 26, 2011, 05:04:11 PM
 #843

Dying here for some proof. There is a slight chance this might be real after all. Thank you D&T for explaining how this could work.
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Your Minion


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November 26, 2011, 05:19:26 PM
 #844

Where's the pudd/ I mean proof.

"A banker is a fellow who lends you his umbrella when the sun is shining, but wants it back the minute it begins to rain." - Mark Twain
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November 26, 2011, 06:45:31 PM
 #845

sASIC is not attractive for mining as it does not have the dedicated adder resources
required to compete with modern FPGAs. I think even ArtForz (who actually built an sASIC)
would agree on this point today, with the recent FPGA design optimizations.

BFL needs to show that:

a) The device can generate real, accepted shares for deepbit or another large,
respected pool at the stated power and performance level, reliably, on a long term basis

b) The device can be built in moderate volume for significantly less than $500
(or $700 or whatever they're charging now)

c) The device will ship in production in <4 weeks, regardless of how many orders they get.

-rph

Ultra-Low-Cost DIY FPGA Miner: https://bitcointalk.org/index.php?topic=44891
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November 26, 2011, 07:12:29 PM
 #846

sASIC is not attractive for mining as it does not have the dedicated adder resources
required to compete with modern FPGAs. I think even ArtForz (who actually built an sASIC)
would agree on this point today, with the recent FPGA design optimizations.

BFL needs to show that:

a) The device can generate real, accepted shares for deepbit or another large,
respected pool at the stated power and performance level, reliably, on a long term basis

b) The device can be built in moderate volume for significantly less than $500
(or $700 or whatever they're charging now)

c) The device will ship in production in <4 weeks, regardless of how many orders they get.

-rph


I think all the FPGA producers like you are getting a bit scared. If this was real you would all be out of business as quick as a fiddle.

Are you saying that sASIC like Altera Hardcopy is not used in this device ? What is used if not this chip ? Maybe you know something we don't.
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November 26, 2011, 07:21:01 PM
 #847

Are you saying that sASIC like Altera Hardcopy is not used in this device ? What is used if not this chip ? Maybe you know something we don't.

Altera Hardcopy is not a structured ASIC technology, at least not in the same sense as eASIC/etc. It's an FPGA cost-down technology.
You can't repurpose the chip for MD5, DES, WEP, NTLM, etc and IMO the loss of flexibility is too large for the per-chip cost savings.

-rph

Ultra-Low-Cost DIY FPGA Miner: https://bitcointalk.org/index.php?topic=44891
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November 26, 2011, 07:32:31 PM
 #848

Nope, hardcopy is a "real" sASIC, I think you're thinking of xilinx easypath (which is pretty much maskROM programmed FPGA).
And I never quite said that sASIC isn't competitive, I said the specific device I used was barely competitive with 45nm FPGAs. Mainly thanks to having no dedicated adder resources and being older (but also low up-front cost) technology.
If this is based on something like a 40nm hardcopy III, performance and power figures look like they're in the right ballpark.

bitcoin: 1Fb77Xq5ePFER8GtKRn2KDbDTVpJKfKmpz
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November 26, 2011, 07:37:01 PM
 #849

If this is based on something like a 40nm hardcopy III, performance and power figures look like they're in the right ballpark.

I'd agree and if this exists at all - hardcopy is the most likely explanation. But 28nm FPGAs arriving in
Q1 will beat 40nm Hardcopy w/o the massive upfront investment and loss of flexibility, so I am continuing to
invest in FPGA-based HW.

-rph


Ultra-Low-Cost DIY FPGA Miner: https://bitcointalk.org/index.php?topic=44891
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November 26, 2011, 08:26:46 PM
 #850

When's the next meet ?

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November 26, 2011, 08:29:01 PM
 #851

But 28nm FPGAs arriving in Q1 will beat 40nm Hardcopy

Thats highly unlikely. Altera's documentation for Hardcopy suggests powersavings, die space (cost) savings and speed increases that are (very) far beyond a die shrink.  My guess is BFL's product isnt even on a leading edge process, but something cheaper like 90nm. An FPGA just cant be competitive with a s-asic.

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November 26, 2011, 08:48:05 PM
 #852

So 25 passed. So does 26 in a couple of hours. No magical uncorn. Just as I predicted. BFL = great ride on the failrumorcopter. Better file those chargebacks before the time runs out. Shipping in 4-8 weeks for a while now Tongue

No test. No live demo. No announcement. No data on chips. Yeah, sounds like a typical scam to me. Has the big announcement on the 25 passed and I did not see it ? Am I just dumb ? Or, are they strong with the scam, these ones ?
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November 26, 2011, 08:53:23 PM
 #853

Sigh.. dude, we know you dont believe it. Please spare us your tiresome, repetitive, content-less "cheer-leading" and use your time more productive by looking up some recipes.



I have a strong hunch you may need it.

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November 26, 2011, 09:06:55 PM
 #854

Can you try and make some pictures in macro mode that makes the print on the asics readable? Im curious to find out what they are, even though its probably mundane like IO and USB. Id just like to confirm there are no custom asics on there other than what is perhaps under those heatsinks (still standing by my structured asic guess).
The ones that are readable are an AVR32 32UC3A1128 microcontroller ("128KB flash, 32KB SRAM, 10/100 ethernet MAC, full-speed (12 Mbps) USB 2.0 with embedded host capability, I2S, and a built-in audio D/A converter") and an FTDI FT2232H high-speed (480 Mbps) dual USB-to-serial converter. This thing looks to be seriously overdesigned! If they'd just added a cheap Ethernet PHY and port, it would have more than enough processing grunt to connect directly to a pool by itself and mine standalone with no computer.

Quad XC6SLX150 Board: 860 MHash/s or so.
SIGS ABOUT BUTTERFLY LABS ARE PAID ADS
DeathAndTaxes
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Gerald Davis


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November 26, 2011, 09:23:41 PM
 #855

Thats highly unlikely. Altera's documentation for Hardcopy suggests powersavings, die space (cost) savings and speed increases that are (very) far beyond a die shrink.  My guess is BFL's product isnt even on a leading edge process, but something cheaper like 90nm. An FPGA just cant be competitive with a s-asic.

Die size matters a lot.  Nobody even sells 90nm sASICs because they are so woefully inadequate compared to FPGA.  Not sure where you get this idea that they are magnitudes cheaper or higher performance.
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November 26, 2011, 09:24:23 PM
 #856

Altera's documentation for Hardcopy suggests powersavings, die space (cost) savings and speed increases that are (very) far beyond a die shrink.

There is marketing, and then there's reality. It's simply not true that 40nm HC is "very far beyond" a
28nm FPGA on a miner (or most other adder-bound) designs. Download the tools and run a design through both.

Given the upfront cost and loss-of-flexibility HC only makes sense if you need (or can resell) a very large #
of fixed-function chips before 28nm FPGAs arrive.

-rph

Ultra-Low-Cost DIY FPGA Miner: https://bitcointalk.org/index.php?topic=44891
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November 26, 2011, 09:39:25 PM
 #857

There is marketing, and then there's reality. It's simply not true that 40nm HC is "very far beyond" a
28nm FPGA on a miner (or any other adder-bound) design. Download the tools and run a design through both.

I wouldnt know how, but I would love to see the results if someone could.

Quote
Given the upfront cost and loss-of-flexibility HC only makes sense if you need (or can resell) a very large #
of chips before 28nm FPGAs arrive.

Well, lets look at the numbers we have. Right now the best FGPA board seems to be the Ztek board, right? It achieves 22 MH/W and when applying the largest volume discount for 100+ boards, 0.6 MH/$. Its based on an FGPA built on leading edge 45 process.

Lets look at BFL's numbers; 53 MH/W and 1.5 MH/$. I suspect its not even built on a leading edge process, but even if it is, thats almost 2.5x better power efficiency and 3x better cost efficiency.

A process shrink will rarely give you 50% on both metrics (I think we can agree the FPGA is by far the largest cost). So I just dont see how a 28nm FPGA could possibly close the gap with BFLs product, let alone a future s-asic built on a smaller node.


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November 26, 2011, 09:57:22 PM
 #858

Well, lets look at the numbers we have. Right now the best FGPA board seems to be the Ztek board, right? It achieves 22 MH/W and when applying the largest volume discount for 100+ boards, 0.6 MH/$. Its based on an FGPA built on leading edge 45 process.

Lets look at BFL's numbers; 53 MH/W and 1.5 MH/$. I suspect its not even built on a leading edge process, but even if it is, thats almost 2.5x better power efficiency and 3x better cost efficiency.

A Spartan6 miner can get within 20% of the BFL MH/$ in qty 100,
and as FPGA competition heats up and margins shrink I think that 3X gap will close quite a lot.
Suffice to say the build I am doing for myself is much, much better than 0.6MH/$.

ztex was first to market and is/was able to extract high margins for having a very
high quality working product that you can buy today. BFL seems OK with razor-thin
margins from the start. My point is just that their end-product pricing is not
accurately reflecting the true cost structure of 45nm FPGAs vs 40nm HC.

There is also the small matter of BFL not actually demoing a working miner yet.

-rph

Ultra-Low-Cost DIY FPGA Miner: https://bitcointalk.org/index.php?topic=44891
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November 26, 2011, 10:15:10 PM
 #859

There is also the small matter of BFL not actually demoing a working miner yet.

-rph


  This..

   Inaba, when are they going to get you a unit to actually test?

If you're not excited by the idea of being an early adopter 'now', then you should come back in three or four years and either tell us "Told you it'd never work!" or join what should, by then, be a much more stable and easier-to-use system. - GA
It is being worked on by smart people. -DamienBlack
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Gerald Davis


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November 26, 2011, 10:28:36 PM
 #860

Well, lets look at the numbers we have. Right now the best FGPA board seems to be the Ztek board, right? It achieves 22 MH/W and when applying the largest volume discount for 100+ boards, 0.6 MH/$. Its based on an FGPA built on leading edge 45 process.

Lets look at BFL's numbers; 53 MH/W and 1.5 MH/$. I suspect its not even built on a leading edge process, but even if it is, thats almost 2.5x better power efficiency and 3x better cost efficiency.

A process shrink will rarely give you 50% on both metrics (I think we can agree the FPGA is by far the largest cost). So I just dont see how a 28nm FPGA could possibly close the gap with BFLs product, let alone a future s-asic built on a smaller node.

Die shrink will ultimately delivery 2x the performance both per $ and per Watt.  That is the whole reason for die shrinks.   Grin  People like to say Moore's law makes computers faster but that is only half the benefit.  If computers had same efficiency as 8086 while you would have a 4GH 6 core chip it would require a 20KW connection to the power grid and costs tens of thousands of dollars a year to operate.

ztek board is available in bulk if someone wanted to finance it (250 unit licensed production run).  So comparing a $200K+ sASIC investment to a board priced for small production is hardly equivalent.  In units of 250 it is closer to 1MH/$ which makes the cost advantage less than <2:1.  While implementations will vary 28nm FPGA will deliver roughly twice the performance per watt and per $ than 45nm process.

Still lets see BFL actually delivery something first.
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