1GH/s, 20w, $500 — Butterflylabs, is it a scam?

[xzion]

incredibly interesting thread, subbing for future.

looking forward to seeing test results.

[1714498444]

1714498444

[runeks]

Inaba, regarding the driver used to control this box, is it a simple user-space USB driver packaged into the program we can see running on your laptop in the last two picture you posted?

I'd very much like to take a look at the source code. I don't expect to see anything revolutionary, as anything they don't want out can be hidden in the firmware on the device. I'm just really curious to see how its built, and especially so if it requires a kernel driver, which would be more of a pain to get working on ARM.

[Inaba]

The demo plan is that I will:
A) connect it to a non-routable development side of the pool, so that the box is unable to communicate with the internet.  I will then let it submit shares to the pool and I will have one of the getwork servers in debug mode and I will see what is sent out and what's sent back.  As I found no evidence of any wireless communications on the board, and since the computer it's connected to will not be on the internet, it won't have any way of falsifying the shares submitted.
B) I will take a unit home that evening, disassemble and take more robust pictures.  I will NOT be removing any heat sinks, however.  
C) I will do further testing that evening on my own with a packet analyzer to see  what packets are being transmitted, when and where they are going and coming from.
That's the plan as of right now, at any rate.

Please make sure at some point during the actual mining you run it on a power meter so you can get a measurement under actual mining load.

There are various ways to fake this sort of thing and match one of {rate,power} but not both. (e.g. you could use a big-fast-expensive FPGA to get 1GH/s, but if they did that they couldn't deliver on their advertised price)

Yeah, I forgot to mention that specifically... but in the initial pictures, I had some pics of the Kill-A-Watt meter, but the flash blanked out the LCD screen on it.  I will have the Kill-A-Watt and take a better picture while it's in operation.

Inaba, regarding the driver used to control this box, is it a simple user-space USB driver packaged into the program we can see running on your laptop in the last two picture you posted?

I'd very much like to take a look at the source code. I don't expect to see anything revolutionary, as anything they don't want out can be hidden in the firmware on the device. I'm just really curious to see how its built, and especially so if it requires a kernel driver, which would be more of a pain to get working on ARM.

I actually mis-spoke a bit, I think, when I called it a driver.  It's actually the mining software used to run it... it uses the standard USB driver already present for basic IO.  To my knowledge, they will be releasing the source to the whole thing (it's GPL'd I believe, so they'd have to release it if anyone asked anyway).

[runeks]

^ Cool, sounds like it's easily portable then. There would be no reason to develop a kernel driver anyway, as far as I know.
I guess I might as well send them and e-mail and ask them for the source code.

[ngzhang]

on the basis of the pics, this is a very high quality product, with professional design.

it looks like 2 FPGAs with a MCU on a 4 layers PCB.  and  i see that 3 voltage test points, 1.1V/2.5V/3.3V.

which high-end FPGA uses 1.1V for the core?

not altera S4 (0.9V),
possible  xilinx V6 is 1.05V (1.1V is OK),
possible  xilinx V5 is 1.05V (1.1V is OK)

[gmaxwell]

on the basis of the pics, this is a very high quality product, with professional design.
it looks like 2 FPGAs with a MCU on a 4 layers PCB.  and  i see that 3 voltage test points, 1.1V/2.5V/3.3V.
which high-end FPGA uses 1.1V for the core?
not altera S4 (0.9V),
possible  xilinx V6 is 1.05V (1.1V is OK),
possible  xilinx V5 is 1.05V (1.1V is OK)

V6 isn't going to do 1GH with 20w.

[ngzhang]

on the basis of the pics, this is a very high quality product, with professional design.
it looks like 2 FPGAs with a MCU on a 4 layers PCB.  and  i see that 3 voltage test points, 1.1V/2.5V/3.3V.
which high-end FPGA uses 1.1V for the core?
not altera S4 (0.9V),
possible  xilinx V6 is 1.05V (1.1V is OK),
possible  xilinx V5 is 1.05V (1.1V is OK)

V6 isn't going to do 1GH with 20w.

yeah, and i also consider the power on this board is VERY over engineered, 2top and 2botton high-end mosfets for just approx. 9A I-core?  (19.8W, 9.9W/each,1.1V, so : 9Amax)

but 2 V5 or V6 can easily get 1.05G/s, that means 500M/each, just implemented 3 cores run @ 170M or 2 cors run @ 250M is ok. very, very, easy on V6.

and, Inaba, no need to remove the heatsinks, just let us know all the other chips on this board is enough for evaluation this board on a technology side.

[ArtForz]

ngzhang: Altera SIII is 1.1V core.

[sadpandatech]

ngzhang: Altera SIII is 1.1V core.

  Aye, looked it up since I am not familiar.  To ask, do you think that's what they are using? Seems the ones on their boards have a silver housing and the Alter SIII are black. No clue if that's static or if a custom chip from them could be different though.  Also, what would be the smallest cell count that could be capable of the ~500MH they are claiming? I notice those chips are not cheap.. Sorry to ask such useless questions but you're just about the most qualified brain about to answer them. ;p


   Cheers

[ngzhang]

ngzhang: Altera SIII is 1.1V core.

oh, i forgot to check altera S3.
so, is it every thing goes clear?

[ArtForz]

Those packages look like 1mm grid thermally enhanced flipchip BGA ... guesstimating by the 0.1" headers ... 29x29mm FF780
so if these are SIII, pretty much "could be anything from a L50 to a E260"
One thing kinda throwing me off... if those are HCs, 1.1V core doesn't make sense. HCII is 1.2V and HCIII and IV are 0.9V.
As for "what SIII would you need for that"... depends on how much time you spend optimizing, first guess would be 2 unrolled engines with 1 pipeline stage per round, each running @ 250MHz... gut feeling says a L150.
So, random guesses:
a) these are HCIIIs, they prototyped with SIII and forgot to update the label for vcore.
or
b) only SIII based prototypes exist, once they get enough pre-orders HCIIIs get ordered (about 8wk if you rush assembly... possible.)
or
c) they somehow got a whole bunch of large SIIIs really cheap.
or
d) something entirely different.

[ngzhang]

Those packages look like 1mm grid thermally enhanced flipchip BGA ... guesstimating by the 0.1" headers ... 29x29mm FF780
so if these are SIII, pretty much "could be anything from a L50 to a E260"
One thing kinda throwing me off... if those are HCs, 1.1V core doesn't make sense. HCII is 1.2V and HCIII and IV are 0.9V.
As for "what SIII would you need for that"... depends on how much time you spend optimizing, first guess would be 2 unrolled engines with 1 pipeline stage per round, each running @ 250MHz... gut feeling says a L150.
So, random guesses:
a) these are HCIIIs, they prototyped with SIII and forgot to update the label for vcore.
or
b) only SIII based prototypes exist, once they get enough pre-orders HCIIIs get ordered (about 8wk if you rush assembly... possible.)
or
c) they somehow got a whole bunch of large SIIIs really cheap.
or
d) something entirely different.

i highly agree with you with a combination of C and B.

they got some S3 for cheap.

than sell the product in cost price or a few percents of loss.

when pre-order number goes enough, start the hard-copy progress.

if not, kill this project.

[gmaxwell]

b) only SIII based prototypes exist, once they get enough pre-orders HCIIIs get ordered (about 8wk if you rush assembly... possible.)
or
c) they somehow got a whole bunch of large SIIIs really cheap.
or
d) something entirely different.

You'd agree what we could probably identify (b),(c) from the power usage though, no?

[ArtForz]

Not sure on power, someone bored enough to synthesize a design and run power estimations?
Don't get fooled by xilinx S6 perf/power, those are the worst of all 45/40nm FPGAs by a long shot; we pretty much only use them because they're cheap-ish and readily available in small qty.

[eldentyrell]

You'd agree what we could probably identify (b),(c) from the power usage though, no?

Early board photos showed an exposed JTAG header.  Just hook it up and query for IDCODEs.

If they did a custom chip it can obviously ignore the IDCODE request or lie, but if they're using a commercial FPGA they can't change this behavior.  The chip will tell us what it is.

[sadpandatech]

  I'm going out to buy a shirt tommorow that reads,

      I'm
     With
    Smartie
  <--v^-->

  Thanks for your information, Art, Ng, Gmax, and Big-Chip

[makomk]

As far as I can tell that would require a lot more software work. Like building a program for the Atmel chip that fetches work. I think this would, somewhat, be a waste of time, as this is what ckolivas has spent so much time perfecting with cgminer. Also, is there a TCP/IP implementation for this Atmel chip even? Or how'd they actually send packets with the PHY, let alone run a mining application on the board?

There are platform-independent open source embedded TCP/IP stacks out there, the most widely used of which is uIP. I've been meaning to write some kind of embedded miner for them for a while. Obviously USB or something similar would still be needed as an option for people that want to run large numbers of miners, though.

Not sure on power, someone bored enough to synthesize a design and run power estimations?
Don't get fooled by xilinx S6 perf/power, those are the worst of all 45/40nm FPGAs by a long shot; we pretty much only use them because they're cheap-ish and readily available in small qty.

Yeah, that's pretty much what I figured; just the messy routing on those alone has got to cost a fair amount in power consumption.

[ngzhang]

Yeah, that's pretty much what I figured; just the messy routing on those alone has got to cost a fair amount in power consumption.

but i noticed on virtex-6 there are still very high I-cores.


ADD:

U5 on that board is atmel AT45DB642D, a 2.5V dataflash.
for the FPGA config steam storage? (so not hard-copy?)

[bulanula]

I say we probe the chip by JTAG and see what it is so we know if they can really pull this off.

Time for demo is still Sunday at midnight GMT right ? Thanks.

[rph]

Don't get fooled by xilinx S6 perf/power, those are the worst of all 45/40nm FPGAs by a long shot; we pretty much only use them because they're cheap-ish and readily available in small qty.

S6 is worse than V6 on perf/W, but it's still optimal on perf/$ even in qty 100+.

A7 should be a very good fit when it arrives

-rph