Swedish ASIC miner company kncminer.com

[Ytterbium]

They will need to have atleast few chips to test the chip itself. They must get a lot data from the actual chip - how can they ship a product to end-user that includes a chip that has only been simulated?
If they don't have chips to test yet, they will be late. Just like Bitfurys chip differed from the simulations kinda lot. Same with BFL. How would it be different with KNC? Really?

They can test the chips at this point if they want too. They would know if there was a problem by now.

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[vesperwillow]

As stated a few times, the logic of the chip was already proven before the silicon was poured. All which remains is making sure they function electrically-speaking, which doesn't take long. Mating the chips to the boards takes longer, which isn't saying much.

As to the preorder process mentioned earlier being half up front/half later, that's similar to how some preorder systems work. You pay an interest/reservation amount up front to get early buy-in, then the remainder after a certain milestone to lock your placae in. It would be nice to see more of this happening in the coin world.

[HyperMega]

They would be testing them individually as they were packaged.  While you can't be certain of the extent of the testing unless you're involved, at the very least they're testing to sort out parts from bad dies from near the edge of the wafer (perhaps only 1 or 2 of the engines functional) and for major faults like Vcc shorted to GND.

How extensive the testing is per chip will depend on the testbeds and simulations that OrSoc provided the packager.  They're doing at least gross electrical testing at a minimum.  They probably are not going so far as binning parts with 4 engines showing up as functional...

There was a concrete question at the KnC open day, if they will do any wafer level or chip level final tests. They clearly answered with no.

If this is still true, they are currently doing a blind packaging of all dies (including the completely bad dies from near the edge of wafers and dies with electrical shorts) and they will assemble all these chips to PCBs. The first time they will notice that there is something wrong with a single chip is when they try to hash with it assembled to a PCB.

This is probably the fastest way to get a chip hashing (because they save the time required for bringing up and debugging a production test environment). But it could be that they have to throw away a lot of fully assembled PCBs. Not optimal in terms of costs, but finally KnC’s problem.

[Puppet]

There was a concrete question at the KnC open day, if they will do any wafer level or chip level final tests. They clearly answered with no.

If this is still true, they are currently doing a blind packaging of all dies (including the completely bad dies from near the edge of wafers and dies with electrical shorts) and they will assemble all these chips to PCBs. The first time they will notice that there is something wrong with a single chip is when they try to hash with it assembled to a PCB.

This is probably the fastest way to get a chip hashing (because they save the time required for bringing up and debugging a production test environment). But it could be that they have to throw away a lot of fully assembled PCBs. Not optimal in terms of costs, but finally KnC’s problem.

You can test the chips after packaging, but before soldering it to a PCB. Soldering untested dies/chips on a PCB makes no sense to me, I cant believe thats what they will be doing.

[HyperMega]

There was a concrete question at the KnC open day, if they will do any wafer level or chip level final tests. They clearly answered with no.

If this is still true, they are currently doing a blind packaging of all dies (including the completely bad dies from near the edge of wafers and dies with electrical shorts) and they will assemble all these chips to PCBs. The first time they will notice that there is something wrong with a single chip is when they try to hash with it assembled to a PCB.

This is probably the fastest way to get a chip hashing (because they save the time required for bringing up and debugging a production test environment). But it could be that they have to throw away a lot of fully assembled PCBs. Not optimal in terms of costs, but finally KnC’s problem.

You can test the chips after packaging, but before soldering it to a PCB. Soldering untested dies/chips on a PCB makes no sense to me, I cant believe thats what they will be doing.

This is called "chip level final test". They said, they won't do it. At least this is what is written in the open day Q&As report.

[Puppet]

This is called "chip level final test". They said, they won't do it. At least this is what is written in the open day Q&As report.

I know, I just assume they misunderstood the question as chip testing is like a few dollar cents per chip and pretty much always cheaper than paying for mounting and PCB.

Anyway, as you said, its their problem.

[Xialla]

*patiently waiting for video and refreshing KNC website every hour*

[Ytterbium]

There was a concrete question at the KnC open day, if they will do any wafer level or chip level final tests. They clearly answered with no.

If this is still true, they are currently doing a blind packaging of all dies (including the completely bad dies from near the edge of wafers and dies with electrical shorts) and they will assemble all these chips to PCBs. The first time they will notice that there is something wrong with a single chip is when they try to hash with it assembled to a PCB.

This is probably the fastest way to get a chip hashing (because they save the time required for bringing up and debugging a production test environment). But it could be that they have to throw away a lot of fully assembled PCBs. Not optimal in terms of costs, but finally KnC’s problem.

You can test the chips after packaging, but before soldering it to a PCB. Soldering untested dies/chips on a PCB makes no sense to me, I cant believe thats what they will be doing.

Why not? There's only one chip per board, if it doesn't work they can just throw it out.

[-Redacted-]

Better look at the board pricture again - because the other components on the board cost far more than the hashing chip...

[vesperwillow]

Being engineers, they more than likely they ordered 30% more of everything than they needed, and they already planned for the 2nd batch orders. I would guesstimate, they have plenty of on hand and are willing to toss some components if necessary. Figure a 5% failure rate at worst for these scenarios, so it's within acceptable boundaries.

[-Redacted-]

No intelligent company tosses $250 worth of components and PCB because a $25 chip is bad...

[vesperwillow]

No intelligent company tosses $250 worth of components and PCB because a $25 chip is bad...

You do if you're in a rush to make a headline-breaking deadline, and if it's a significant number of rejects you hire someone to extract what they can off the board to put in the scrap bin.

Hypothetically if it cost them $2kUSD overhead per unit, and they sold 100,000 units expecting a 5% reject rate then they'd have 110,000 units of inventory (more in reality). Considering they're making 50% (roughly) per unit, a 1% loss per unit isn't a big deal.

[markm]

Maybe someone has never raced in a formula-1 race, too...

-MarkM-

[vesperwillow]

I suspect that you've never actually owned an electronics business of your own...

No,  never owned one. I've owned 3 other successful businesses though. I have worked at at electronics companies, and worked for companies which assembled/delivered things on time under duress of deadlines. There's always an acceptable amount of loss regarding service or product deliverables. If you plan for it, you minimize impact and lower stress.

This is why I'm presuming they ordered 30% more of everything critical and planned for at least a 5% loss.

Unless you have a much  better plan--not saying you don't, just curious.

[Beta-coiner1]

Ok,not speculation or guesses but just got a response from KNC concerning the speed increase for Saturns."The guaranteed minimum speed for Saturn is 200 Gh/s and we are expecting to be over that mark by a considerable margin"

[vesperwillow]

Ok,not speculation or guesses but just got a response from KNC concerning the speed increase for Saturns."The guaranteed minimum speed for Saturn is 200 Gh/s and we are expecting to be over that mark by a considerable margin"

They said this about the other units as well, a couple weeks back.

[capa]

Is it at all possible that the chips with be mounted like motherboard CPU's? So if a chip is bad it can easily be replaced/upgraded without damaging the PCB?

[-Redacted-]

Is it at all possible that the chips with be mounted like motherboard CPU's? So if a chip is bad it can easily be replaced/upgraded without damaging the PCB?

It's a very large pin-grid array.  They might be using sockets, but because of all the "bumps" it has, they're probably soldering it directly onto the board.

[vesperwillow]

Well, to start with, you don't scrap bad boards that cost 10x what the main chip on them costs - especially when you are paying software licenseing fees for each copy of the embedded firmware on them.  

Once things have died down, and depending on what the trouble is with the board,  you would either rework it to replace the hashing chip and sell it as an add-on module later, you might possibly use it in a lower end machine (probably not worthwhile), or, at the very least sell them "as is" for the cost of the parts.  I do not doubt they ordered extra to get through this first batch, but I seriously I doubt they are planning to just throw money in the trash afterwards...

I agree, which is why I mentioned hiring someone to handle them. By scrap bin, I meant the rework/look-into-it bin, not literally trash.

[crumbs]

Is it at all possible that the chips with be mounted like motherboard CPU's? So if a chip is bad it can easily be replaced/upgraded without damaging the PCB?

It's a very large pin-grid array.  They might be using sockets, but because of all the "bumps" it has, they're probably soldering it directly onto the board.

I think it's a ball-grid array (BGA), sort-a the same thing minus the pins.  It's an awesome package if you never have to rework it, but removing/replacing chips is pretty difficult -- you need a nice reflow station.  Hot air pencils won't do it.