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Author Topic: New Official AMT Thread  (Read 149468 times)
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opieum2
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May 22, 2014, 11:29:05 PM
 #1561

Thanks, I am not spi usb programmer, Just want to help out, and keep you barking up the right tree Smiley
Seems most industry devs already know most of this, It just hit the hobby level and I found it relevant to some of you guys diagnostic posts. AMT must also know this.

Seems all three have similar issues HF BA AMT. Would that boil down to Bitmine original design ?

1 SPI for each master slave.... Is correct way.

Yes its a good point and most of have gone through that one, but in this we don't think it's the SPI. Zefir outlined this in his thread:

https://bitcointalk.org/index.php?topic=294235.0

The chip resets itself when:

A. when supply voltage is unstable,
B. chip gets too hot,
C. there is noise on SPI bus and communication gets messed up.

Once that happens, we have not found a way to get the chain back to life other then possibly issuing a HW reset which is covered in zefir's thread.


For C. this is an easy fix...isolate the traffic into 5 lanes. This can be adjusted based on the type of miner. Create dedicated channels for it. This is where I was going with the USB/SPI suggestion. There are a few solutions for this on the market already to easily implement this. It would not require any major re-engineering and the backplane can go away allowing for more flexible airflow designs.

Gonna read zefir's post to get some more info, maybe something in there will pop at me and I might be able to mod up a solution to some of these things.

For the other two that is a design problem.

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May 22, 2014, 11:53:12 PM
Last edit: May 23, 2014, 12:43:24 AM by NotFuzzyWarm
 #1562

At the end of Zefir's someone has made a data in shifter as well. https://bitcointalk.org/index.php?topic=294235.msg6176799#msg6176799
Again the questions:
Are level shifter chips used to translate to/from RasPi's 3.3v I/O to/from the A1's required 1.8v for both data in & out on the production boards or using resistor divider network for the input data?
Does each A1 have it's own buffered clock signal?

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May 23, 2014, 12:02:34 AM
Last edit: May 23, 2014, 12:59:36 AM by NotFuzzyWarm
 #1563

Zefir also briefly touched on USB coms... https://bitcointalk.org/index.php?topic=294235.msg6506328#msg6506328

edit: Hmm... and the Technobit boards use usb. https://bitcointalk.org/index.php?topic=376351.msg4032228#msg4032228
Is just a render but click on the pics.

Are the new Bitmine/AMT/Technobit collaboration boards similar???
Does/can BFgminer work with them? It runs my 2 lil' ASIC Jalapeno's from BFL great.

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May 23, 2014, 01:10:38 AM
 #1564

well, at least some of you guys got broken hardware you get to fix yourselves Sad 

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May 23, 2014, 01:11:39 AM
 #1565

Zefir also briefly touched on USB coms... https://bitcointalk.org/index.php?topic=294235.msg6506328#msg6506328

edit: Hmm... and the Technobit boards use usb. https://bitcointalk.org/index.php?topic=376351.msg4032228#msg4032228
Is just a render but click on the pics.

Are the new Bitmine/AMT/Technobit collaboration boards similar???
Does/can BFgminer work with them? It runs my 2 lil' ASIC Jalapeno's from BFL great.

This is critically necessary with the AMT variant.

https://bitcointalk.org/index.php?topic=294235.msg6506328#msg6506328

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May 23, 2014, 01:43:42 AM
Last edit: May 23, 2014, 02:44:49 AM by NotFuzzyWarm
 #1566

Which? The HW_reset function, SPI info, or chip voltages?
Or all the above? Wink
Elsewhere in the thread they mention liking 0.84v (??) for starting the chip.

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May 23, 2014, 02:27:53 AM
 #1567

Quote zefir:
Step-by-Step Bring-up Process
1) Physical
Most is depicted in the above figure, this is the prose version:

    chip is 1.8V only => use level shifter for all signals from/to host SPI interface
    VDD needs to be ~820-850mV with a max. ripple of 70mV (pilot run chips do not support undervolting)
    AVDD needs to be 1.8V with a max. ripple of 200mV
    power-up PLL settings are based on 12MHz reference clock; if you use a higher value do not start hashing without reducing system clock via PLL or you risk bricking the chip by overclocking it.
    if you have a multi-chip board, use a clock distribution device to drive them with a single oscillator
    heat-sinks on both sides of the chip needed, monitor and ensure surface temperature does not exceed 50°C
    HW reset is mandatory; RSTN needs to be pulled low for at least one second; ensure it was released for at least one second before the first command is issued

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May 23, 2014, 02:30:50 AM
 #1568

1. Receive your miner immediately - with a 1.2hash rate or maybe a bit more. Immediately being end of this week.

I take it option #1 is no longer possible seeing how another 2 weeks have passed since that "end of this week" deadline.

Buy & Hold
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May 23, 2014, 02:41:38 AM
 #1569

Quote zefir:
Step-by-Step Bring-up Process
1) Physical
Most is depicted in the above figure, this is the prose version:

    chip is 1.8V only => use level shifter for all signals from/to host SPI interface
    VDD needs to be ~820-850mV with a max. ripple of 70mV (pilot run chips do not support undervolting)
    AVDD needs to be 1.8V with a max. ripple of 200mV
    power-up PLL settings are based on 12MHz reference clock; if you use a higher value do not start hashing without reducing system clock via PLL or you risk bricking the chip by overclocking it.
    if you have a multi-chip board, use a clock distribution device to drive them with a single oscillator
    heat-sinks on both sides of the chip needed, monitor and ensure surface temperature does not exceed 50°C
    HW reset is mandatory; RSTN needs to be pulled low for at least one second; ensure it was released for at least one second before the first command is issued
Thanks. All are  8-chip boards. Will be checking all levels I can including downstream SPI signals. Hopefully the A1 buffers things between the 2 side of it.

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May 23, 2014, 03:17:20 AM
 #1570

I will stay busy reading all those new links just posted, lots of good stuff therein,,,,
Did find the reason all are struggling, noone wanted to share info, till lately.
with a 6month lifespan on high end equiptment, they have no time to act like that.
Community shared it would have gone much faster.

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May 23, 2014, 04:24:06 AM
Last edit: May 23, 2014, 05:42:15 AM by NotFuzzyWarm
 #1571

I will stay busy reading all those new links just posted, lots of good stuff therein,,,,
Did find the reason all are struggling, noone wanted to share info, till lately.
with a 6month lifespan on high end equiptment, they have no time to act like that.
Community shared it would have gone much faster.
Can't disagree there. But... Community & business rarely make good bedfellows.

<stands up> I design very very expensive industrial systems for a living.
 A good part of their market is for <drum roll please> chip making. Because the product is in front of the bleeding edge I am often brought in nearly from day-one of our customers customer asking, "Can we do this...?". (Usually after informing them of what it will entail - yes. I love challenges).

The folks who commissioned the ASIC's be they Bitmine/InnoSilicon, Cointerra, BFL or whoever aside from Bitmaintech seem to have gone to the Underpants Gnomes school of business. Look it up. It's actually an oft used term Cheesy

In this case it goes:
step-1: Make chips for miners
step-2: ? ? ?
step-3: Profit!

The step-2 that is missing is design what *uses* the chip.

Point is I am damn certain of what will need to be addressed for my equipment & process to work 24x7x365 for years and often decades. Why am I certain? Because I and my company have been constantly researching future needs and at our expense already done all the groundwork. My customers are telling me they want to spend several million dollars a year bringing in our systems and I need to be certain the design will work. Period.

Yes chips delay hurt massively but more to the point those selling chips did nothing to actually *use* the chips in-house. After that release true engineering samples along with test boards. IF I have the timeline for the A1 right it went from a 1 to 2 chip reference pretty much conceived of/gotten to work in the dev & DIY threads in about a month (Jan-Feb) and then straight to 'production' with 8 chips. Of course the 1st versions have problems. eg. the multiple SPI slave chain matter. The entire design was never characterized to begin with. Just get it running... I understand the pressures that the pre-order syndrome brought on but hell, they threw a baby into battle!

At least it seems InnoSilicon/Dragon & Technobit saw what they actually had to deal with and addressed it better then those who relied on the BitMine design team.
<sits down again>

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May 23, 2014, 09:07:46 AM
 #1572

I will stay busy reading all those new links just posted, lots of good stuff therein,,,,
Did find the reason all are struggling, noone wanted to share info, till lately.
with a 6month lifespan on high end equiptment, they have no time to act like that.
Community shared it would have gone much faster.

Please read my related post: https://bitcointalk.org/index.php?topic=294235.msg6536840#msg6536840


Aside from that, if you are struggling with technical problems or want to discuss them, you should visit the above A1 DIY thread with better chances to meet other developers and get your issues resolved.


Cheers,
zefir

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May 23, 2014, 12:17:10 PM
 #1573

1. Receive your miner immediately - with a 1.2hash rate or maybe a bit more. Immediately being end of this week.

I take it option #1 is no longer possible seeing how another 2 weeks have passed since that "end of this week" deadline.

Was this offer ever legit?

Likely stepped on the lawyers toes. At this point I just hope it all gets worked out for everyone. I am trying for my part to hopefully salvage things in favor of the people who got something broken. And maybe in the process try to make sure this does not happen again to others. I do think they tried to make this work, but just failed on alot of levels. I get a bit pissed sometimes thinking about it, because its my 11k that got pissed away. So I like others have that axe to grind. I am sure AMT is keenly aware of that. Hopefully soon we hear about what will be done to make this all right for us.

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May 23, 2014, 12:52:52 PM
 #1574

actually that was a double side 20 pin, I posted the one for double side 10 pin. While some of the parts were in the box, some were not. Even though its in the box, its unusable. I bought some of these 10 pin, let me know if anyone needs them. They come from China, so might be a few... Now to find that female PCI-E board connector. Any ideas?

I need to find this one now... I guess it is called a "6-Pin Graphics Card PCIe Male Header Connector"


If youre looking for a 6 to 8 pin connector, I have some laying around from GPUs I bought (for mining of course). I could either send you one if thats what you're looking for, or id imagine they're easy to find at a local electronics DIY place.
Let me know!

Thanks mdiggy, that is very nice of you... I actually ordered some from where notfuzzywarm suggested. I have ordered the double sided 10 pin connector if anyone needs those.

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May 23, 2014, 01:44:05 PM
Last edit: May 23, 2014, 02:08:07 PM by NotFuzzyWarm
 #1575

I will stay busy reading all those new links just posted, lots of good stuff therein,,,,
Did find the reason all are struggling, noone wanted to share info, till lately.
with a 6month lifespan on high end equiptment, they have no time to act like that.
Community shared it would have gone much faster.

Nobody wanted to share?   Folks are just discovering the problems.... AMT is the one not sharing.

Heck... they are even asking these folks who are sharing to sign an NDA!  For the uninformed.... NDA is NON DISCLOSURE AGREEMENT
Swing and a miss.
The NDA will be because specific product IP is needed for me and ISA to do the voodoo we do so well. One can only go so far with visuals and conjecture based on the 1 & 2 chip reference boards and schematics. Obviously many things by necessity have to be different with the 8-chip setups. I've read the dev and DIY threads from start to finish before. Those are what pointed me at the various things I've been bringing up here as problems being seen sound a lot like what those threads covered. Somewhere between a reasonably good start and scaling to production systems seems that a lot of A1 company designers fell victim to the NIH attitude and tried to re-write the rules. Even the Technobit designs are still being tinkered with and discovered (and nice job on the power/speed work in their part of the Forum Losh...) but then that seems like what they were made for: stand-alone miners and tinkering toys, not piled in a common box as systems.

As with Hashfast, Black Arrow and others in the A1 game things for them have moved past the community-only aspect. Business is business and you can't sell systems unless you can differentiate your product from the others and that takes IP. Or at least systems that work...

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May 23, 2014, 02:33:46 PM
Last edit: May 23, 2014, 05:12:08 PM by NotFuzzyWarm
 #1576

Won't disagree at all on the commodity aspect and I am at a loss to explain the poor designs. What, did they (Bitmine.ch) hire some interns with not even 1st year design experience to make these rigs? Roll Eyes

"If AMT had instead focused on prompt delivery and solid support,  then maybe they would not be in this mess"
Delivery of what? The earlier non-working Bitmine-based designs? Again, read the A1 dev thread. Look at when ANYBODY 1st had chips to experiment with. Look at when the 1st test boards were made. Now consider that BMch et-al had promised full blown systems - not test kits - to be in customer hands months before. There simply was literally zero time left for the commercial entities to make/properly test a salable system.

IP does matter. It matters very very much. IP is what will make one design work when others trying to use the same core parts don't work. Right now AMT is competing with HF, Dragon and to some extent Bitmine.ch to get a decent A1 design out the door. Competing against other chip systems is not exactly an issue yet compared with getting things to work and be suitable for large production runs.

Bitmaintech will provide design guidelines if you want to use their chips but they will NOT give you their sales product designs. Same with Cointerra. Even Technobit licensed their board design to Bitmine/AMT. They did not just give it away and it is a damn safe bet that if Technobit sold systems vs modules/kits they would not have helped at all.

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May 23, 2014, 03:05:45 PM
 #1577

Won't disagree at all on the commodity aspect and I am at a loss to explain the poor designs. What, did they (Bitmine.ch) hire some interns with not even 1st year design experience to make these rigs? Roll Eyes

IP does matter. It matters very very much. IP is what will make one design work when others trying to use the same core parts don't work.

Bitmaintech will provide design guidelines if you want to use their chips but they will NOT give you their sales product designs. Same with Cointerra. Even Technobit licensed their board design to Bitmine/AMT. They did not just give it away and it is a damn safe bet that if Technobit sold systems vs modules/kits they would not have helped at all.


Well Cointerra sells their chips and will give you the reference design.  

It is actually a compelling deal... for $105,840  you get 525 chips.  Each chip is at 500GH/s nominal.

So if you were to build a farm.... $105K gets you  262 THs!   (Not including board manufacturing and power supplies)

Holy sh*t!   What they are saying is that you can build a 1THS for under $1,000.  

At $200 a chip in bulk.... they've considerably undercut Innosilicon at $45 per chip.   




 
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May 23, 2014, 03:15:27 PM
Last edit: May 23, 2014, 03:58:15 PM by NotFuzzyWarm
 #1578

Again, a reference design is just that: a basic how-to example to make something work and test it. It is a only a starting point. It is NOT an optimized final design much less something ready to be stuffed into a complete miner eco-system . They will give you a list of things to look out for but not their precise solutions to it.

It is not just a matter of taking a bunch of boards and stuffing them in a case, sprinkling pixie dust on it and Volia' - it works. BMch/AMT, & HashFast tried that approach and we see where that led.

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May 23, 2014, 03:18:21 PM
 #1579

Again, a reference design is just that: a basic how-to example to make something work and test it. It is NOT an optimized final design much less something ready to be stuffed into a complete miner eco-system . They will give you a list of things to look out for but not their precise solutions to it

Give the Cointerra reference design... you think you can come up with a reliable layout?

I am sure someone would be extremely interested considering price point... I mean... $100K can get you to almost 200 THs.   That can't be beat!

 
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May 23, 2014, 03:53:20 PM
 #1580

Again, a reference design is just that: a basic how-to example to make something work and test it. It is NOT an optimized final design much less something ready to be stuffed into a complete miner eco-system . They will give you a list of things to look out for but not their precise solutions to it

Give the Cointerra reference design... you think you can come up with a reliable layout?

I am sure someone would be extremely interested considering price point... I mean... $100K can get you to almost 200 THs.   That can't be beat!
You are obviously not including paying anyone a salary or any other overhead. For a commercial (paid) endeavor sure I could if I had any interest in it. However, I *have* a career and it is not in making miners.

Years ago I would have said that any decent electronics design engineer could do it. Sadly, that no longer seems to be the case as more and more are not being taught *why* things work the way they do, just what to do with them. Understanding the 'why' gives insight into what to do when over-simplified models do not produce working physical designs.

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