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Author Topic: Cairnsmore1 - Quad XC6SLX150 Board  (Read 286362 times)
makomk
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July 24, 2012, 06:33:06 PM
 #1481

I will test it, but the link is not working :-/
Whoops, sorry. Fixed.

Quad XC6SLX150 Board: 860 MHash/s or so.
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MrTeal
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July 24, 2012, 06:35:36 PM
 #1482

Are the RX and TX lines on the top or bottom layer or otherwise reasonably accessible where a skilled person could swap them to get the normal Icarus bitstream running?
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July 24, 2012, 06:53:11 PM
 #1483

Are the RX and TX lines on the top or bottom layer or otherwise reasonably accessible where a skilled person could swap them to get the normal Icarus bitstream running?

Makomk have swaped them in the bitstream we are testing at the moment. And to your idea, it's not possible, i think it's a 6 or 8 layer PCB.
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July 24, 2012, 07:38:58 PM
 #1484

http://s14.directupload.net/file/d/2961/xvi9i6lb_png.htm

like you see I have no stability issues, but only 1 fpga is running (second board the first I had sn 002 was broken)

cgminer 2.5.0, Win7 x64

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July 24, 2012, 07:40:28 PM
Last edit: July 24, 2012, 08:08:59 PM by ebereon
 #1485

short reply:
fpga0: fpgaminer_cm1_160_test_ds.bit <- working
fpga1: fpgaminer_cm1_160_test_nods_pullup.bit <- working
fpga2: fpgaminer_cm1_160_test_nods_pullup.bit <- not working
fpga3: fpgaminer_cm1_160_test_ds.bit <- not working


fpga0: fpgaminer_cm1_160_test_ds.bit <- working
fpga1: fpgaminer_cm1_160_test_nods_pullup.bit <- working
fpga2: none
fpga3: fpgaminer_cm1_160_test_ds.bit <- not working


fpga0: fpgaminer_cm1_160_test_ds.bit <- working
fpga1: fpgaminer_cm1_160_test_nods_pullup.bit <- working
fpga2: fpgaminer_cm1_160_test_nods_pullup.bit <- not working (get no work -> nods have other pinout?)
fpga3: fpgaminer_cm1_160_test_nods_pullup.bit <- worked one time U ~1.6 LED's ok, next 5 attempts not working...


fpga0: fpgaminer_cm1_160_test_ds.bit <- working
fpga1: fpgaminer_cm1_160_test_nods_pullup.bit <- working
fpga2: none
fpga3: fpgaminer_cm1_160_test_nods_pullup.bit <- not working

eb

EDIT:
See bold
rampone
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July 24, 2012, 10:23:28 PM
 #1486

 Cry only 2*50Mh/s bitstream working on my board so far. nuttin' else.
(first cry from me for over a month in this thread Wink

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July 24, 2012, 10:58:45 PM
 #1487

@rampone

Hope in the #bitminter on irc and i'll try to see if i can help you get your board working. No idea what issue you got but i'll try to help you if i can Smiley
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July 24, 2012, 11:43:40 PM
 #1488

I wrote another email to bitcoin.support@enter....uk . I guess we'll see further with an answer.

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spiccioli
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July 25, 2012, 06:28:33 AM
 #1489

Today I was able to get the Enterpoint cairnsmore to work with the tricone mining software without needing an isolated stand-alone cable, just the FTDI link.  The code is still early in function, and still suffers from some JTAG errors likely due to noise / reflections on the lines which will need better error handling.  I only performed several tests, but was easily able to get stable function with three rings at 100Mhz. (150 Mh/s).

I will keep you guys updated, I should have more time to work on it on Tuesday.

Here's some brief logs from submitted shares, it's fairly garbled from the ascii formatting for the colors.


Hi chrisp,

so you wrote the java interface for the cairnsmore board?

spiccioli
Cranky4u
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July 25, 2012, 08:11:26 AM
 #1490

FYI...day 2 now and stable

Set up

Win 7 64bit, cgminer 2.4.3 for FPGAs, phoenix miner for GPUs  (cgminer for GPUs not stable), 2 * CM1 om MB USB lines, 2 * 6770

CM1 are stable at total of 750.5MHs
GPUs are stable at total of 380MHs

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July 25, 2012, 12:05:46 PM
 #1491

Good to hear another with promising stability.
Have you tried Cgminer 2.5 I found it more stable all round over 2.4.3?

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July 25, 2012, 12:31:22 PM
 #1492

Today I was able to get the Enterpoint cairnsmore to work with the tricone mining software without needing an isolated stand-alone cable, just the FTDI link.  The code is still early in function, and still suffers from some JTAG errors likely due to noise / reflections on the lines which will need better error handling.  I only performed several tests, but was easily able to get stable function with three rings at 100Mhz. (150 Mh/s).

I will keep you guys updated, I should have more time to work on it on Tuesday.

Here's some brief logs from submitted shares, it's fairly garbled from the ascii formatting for the colors.


Hi chrisp,

so you wrote the java interface for the cairnsmore board?

spiccioli

Yep.

Unfortunately some JTAG timing or noise issues persist, but they are improved, I'll post an update when things are more stable.  I was able to run the the miner for 20-30 minutes without any issues, which is reassuring.
yohan (OP)
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July 25, 2012, 02:28:29 PM
 #1493

Ok a short update on progress with glasswalker's build that we are playing with. We have this now running on 3 FPGAs with a good stability and good mining results currently at a 175MHz clock rate. The 4th FPGA position still has some problems and we have a few more things that may make it viable in it's current form yet to try. Either running as 3 or 4 FPGAs we will aim to make a controller release available for it later today as it will give you all better hashing rates and U values. We will discuss with glasswalker how current bitstream is released and there may be more than one variant of the bitstream to suit each FPGA's particular needs.

The current issues are related to noise on the com lines which coupled with a weak UART design which either allow a false edge trigger and/or incorrect data to be received. At the penalty of a rebuild this can be fixed with a more robust UART design should the other methods that we are currently playing with fail.

The 175MHz build also looks like it might run at 200MHz on many boards as well but we have more work to do on that. We will concentrate on the 4th FPGA issue first before looking more at this possibility.
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July 25, 2012, 02:34:04 PM
 #1494

nice one! can't wait for the new bitstream and things.  Smiley
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July 25, 2012, 02:42:25 PM
 #1495

Thanks for the update!  I can't wait to test it out!  Grin
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July 25, 2012, 03:01:56 PM
 #1496

I've been following this thread very closely as i'm interested in making a bulk order.

So far, it doesnt make any business sense now. If you think this as an investment, then its terrible. How many ppl have got these board worked at intended speed? and if you did, for how long? I'm not a technical person but spending a month of tinkering is not acceptable. Maybe we should now know why BFL had a long waiting for their production.

As a potential customer, may i know exactly why you sell the boards without a working bitstream?

/troll

I don't think this post is a troll, his other posts seem to indicate he was looking to purchase from BFL but is having exactly the same problems everyone always seems to have with them on this forum. That said, these boards are being sold as pure hardware, because the guy making them knows hardware. He doesn't know or care what we do on the software end. I would highly encourage anyone to continue to watch this thread and see how open source community solutions work.

Keep in mind, once they do get a sufficient software solution for this board, everyone that owns one is going to be mining at significantly better price/hash rates than anyone who owns a BFL Single or anyone that's pre-ordered a SC product.

I know many people think the SC is going to beat everything else hands down, but guess what? You don't own one and you don't know when you will have one, people that order any other FPGA solution at least have an idea of when they will receive the product.
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July 25, 2012, 03:04:21 PM
 #1497

any speculation on the maximum power draw for the CM1 once everythings optimized? trying to plan out my psu purchase. I'm guessing ~60 watts per board if they're running @ 1000+mh/s

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ebereon
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July 25, 2012, 03:11:59 PM
 #1498

any speculation on the maximum power draw for the CM1 once everythings optimized? trying to plan out my psu purchase. I'm guessing ~60 watts per board if they're running @ 1000+mh/s

60 Watt is maximum, so this is what your PSU have to handle.
wildemagic
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July 25, 2012, 03:16:57 PM
 #1499

Keep in mind, once they do get a sufficient software solution for this board, everyone that owns one is going to be mining at significantly better price/hash rates than anyone who owns a BFL Single

BFL singles sell for $599 and hash at 830-880mh/s

CM1 sells for $960 and is speculated to hash at 800mh/s as (Xilinx XC6SLX150 x 4 / typical speed 200mh/s each)

any speculation on the maximum power draw for the CM1 once everythings optimized? trying to plan out my psu purchase.

Typical Xilinx XC6SLX150 based FPGAs use about 10w, so a quad board should be around 40w @ 200mhz/mhs.

I'm guessing ~60 watts per board if they're running @ 1000+mh/s

Not going to happen any time soon, especially if the chips are only at 1.2v, check out kakobrekla's thread here : https://bitcointalk.org/index.php?topic=90370.0

This will be my last update or at least for a while, I have achieved maximum clock 248mhz at 1.41V, which is the ztex bitstream limit.
Still waiting for new releases of ET's TML release - maybe we will see some interesting numbers there.

But given that Enterpoint might have software control over the voltage, its entirely possible that with a better bitstream or the tricone stream that overvoltage and 200mhz/mhs+ speeds will be possible.

kind regards

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July 25, 2012, 03:19:10 PM
 #1500

Keep in mind, once they do get a sufficient software solution for this board, everyone that owns one is going to be mining at significantly better price/hash rates than anyone who owns a BFL Single

BFL singles sell for $599 and hash at 830-880mh/s

CM1 sells for $960 and is speculated to hash at 800mh/s as (Xilinx XC6SLX150 x 4 / typical speed 200mh/s each)

any speculation on the maximum power draw for the CM1 once everythings optimized? trying to plan out my psu purchase. I'm guessing ~60 watts per board if they're running @ 1000+mh/s

Typical Xilinx XC6SLX150 based FPGAs use about 10w, so a quad board should be around 40w @ 200mhz/mhs.

kind regards
Everyone that ordered here got their devices for $640, and they may reach up to 1Ghs with an optimized bitstream. That is better than BFL.
An optimized bitstream is likely to pull more than 10 watts per FPGA, preliminary estimates are between 12 and 15 watts each.

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