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Author Topic: Cairnsmore1 - Quad XC6SLX150 Board  (Read 251473 times)
yohan
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July 03, 2012, 09:43:54 PM
 #1121

I know there are not too much free space on the PDB but what about adding in future versions 3 or 6 independant power switch ( one per pci-e o per 2 pci-e)  so you dont need to turn off the full array, if you have any problem.

We can put individual boards into standby and turn off various power supplies all potentially on the up/down structure so there isn't much mileage adding a lot of parts and complexity to the PDB. If anything I'd like to have current measurement so we could detect problems.
Any chance of making some power boards with screw connectors instead of the phoenix ones? You'd have a much wider audience and sell many more.
[/b]

Pheonix mating halves come with screw terminals. In fact there are a choice of the these and that was one of the reasons for us using this series. It's easy to make wiring looms without special tools. This also allows custom harnesses to suit individual rigs.

@Enterpoint Team & yohan:

Today i almost made world first in accidently destroying a cairnsmore1 board by putting in a wrong atx power supply cable (yeah call me stupid - i deserve it).

Seconds after i realized that some black smoke raised into the air over the board, i shut down the power supply.

When i took a closer look at the accident i realized that i just bought the worlds best fpga board for bitcoin mining available because all i had to do is put in a non-broken fuse from another cairnsmore1 board. It works perfectly again. WOW - just awesome! Thanks for bringing in the fuse into the design - that really safed me a board Smiley

I'll contact your sales - maybe you can supply me with a new fuse.

We can probably sort you out a fuse but if you want to look locally you can either buy it as a holder/fuse combo (sometimes easier to find) or the fuse itself. These parts are made by Littlefuse and the combo is part number R154010 (R154007 probably ok as well) and the individual fuse is 0453 010 (0453 008 or 0453 007 as well).

yohan,

any news on updated FPGA firmware able to use all four FPGAs per board?

My boards are hashing nicely but those red/yellow leds always on (and which remind me the Spanish flag Cheesy) make me feel a little sad Smiley

spiccioli

It's still moving forward. It's a piece of string task to a certain extent and until it is finished it's not. There isn't anything in the middle.

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Doff
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July 04, 2012, 01:19:20 AM
 #1122

Hashing away at full twin_test speeds with the replacement board Enterpoint sent. Thank you very much that was truly an amazing turnaround and terrific customer service.

I'm very happy with the board and patiently waiting for any new bitstream updates.

Thanks again,

Doff
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July 04, 2012, 05:38:54 AM
 #1123

first let me say I take anything that comes out of the *** camp w/ this much salt.

that being said, assuming they can deliver on even 20% of what they've promised, have you come up with/are thinking about anything similar to help the Enterpoint camp stay competitive?

Oh boy, here we go AGAIN...

I'm sure enterpoint will stay competitive with whatever other products are released.

This has been mentioned atleast three times already throughout the thread. Can we PLEASE not start this again? -.-

I think this is where I finish up this train of thought by saying 28nm running a Fury-like or TML-like firmware would be about half as dollar efficient as what BFL claims, and probably just as dollar efficient as what BFL will actually deliver. And, although yohan probably doesn't want to talk about upcoming products, I believe Enterpoint is already working on a 28nm board.

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July 04, 2012, 07:23:50 AM
 #1124

What do you think my issue here is:

3 Cairnsmores plugged in at an unpowered usb hub, all running the twintest bitstream and enterpoints cgminer for it. Windows seven, quad core, plenty of ram (it's a gaming pc).
5 first cores are pushing shares as is to be expected (0-4) But CM5 is doing less than a third of the shares of the other cores, with 0 rejects showing up at cgminer, whereas the other cores have a normal invalid rate (6-16 invalids at aroud 3300 shares hashed per core).

Im starting cgminer with the command: cgminer_twintest -o mint.bitminter.com:8332 -u ME -p MAHPASS --disable-gpu -S noauto -S\\.\COM22 -S \\.\COM23 -S \\.\COM26 -S \\.\COM27 -S \\.\COM30 -S \\.\COM31

If some relevant info is missing please just ask me.

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testconpastas2
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July 04, 2012, 09:04:15 AM
 #1125

surely this core has frozen.  if you quit cgminer and  try to re-execute the same comand. You'll get a COM error in that port..

If any core gets frozen, accepts stop raising too (in that core) and average hasing speed decrease

please answer with your feedback

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gpg key id:C6EF5CE3
Isokivi
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July 04, 2012, 10:44:57 AM
 #1126

surely this core has frozen.  if you quit cgminer and  try to re-execute the same comand. You'll get a COM error in that port..

If any core gets frozen, accepts stop raising too (in that core) and average hasing speed decrease

please answer with your feedback
No, it's not frozen, it keeps on hashing, just at the very low rate. It's been like this since the beginning.

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yohan
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July 04, 2012, 10:46:17 AM
 #1127

What do you think my issue here is:

3 Cairnsmores plugged in at an unpowered usb hub, all running the twintest bitstream and enterpoints cgminer for it. Windows seven, quad core, plenty of ram (it's a gaming pc).
5 first cores are pushing shares as is to be expected (0-4) But CM5 is doing less than a third of the shares of the other cores, with 0 rejects showing up at cgminer, whereas the other cores have a normal invalid rate (6-16 invalids at aroud 3300 shares hashed per core).

Im starting cgminer with the command: cgminer_twintest -o mint.bitminter.com:8332 -u ME -p MAHPASS --disable-gpu -S noauto -S\\.\COM22 -S \\.\COM23 -S \\.\COM26 -S \\.\COM27 -S \\.\COM30 -S \\.\COM31

If some relevant info is missing please just ask me.

As an experiment try taking out one or two of the board returning good results and see if that changes anything. Unpowered hubs do have some problems as any current taken will multiply up with the number of boards. It doesn't take much to overload an unpowered hub. Powered hubs are definately better and I would suggest this as a good thing to use for the short term

One other general issue with USB is that the way it timeslots data can mean that the USB can run out bandwidth on relatively low bandwidth applications e.g. serial coms with a relatively small number of boards. I would be surprised if 5 boards caused this issue but I am not an expert in USB protocol so I can't be more specific. It can be worth spreading your boards aroung your PCs ports. This isn't always a solution as an occasional PC has an internal hub for multiple ports which only actually has one USB controller but for most PCs this is a good way forward. Once we get the up/down function sorted out these potential USB problems should more or less dissappear.
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July 04, 2012, 11:12:06 AM
 #1128


As an experiment try taking out one or two of the board returning good results and see if that changes anything. Unpowered hubs do have some problems as any current taken will multiply up with the number of boards. It doesn't take much to overload an unpowered hub. Powered hubs are definately better and I would suggest this as a good thing to use for the short term

One other general issue with USB is that the way it timeslots data can mean that the USB can run out bandwidth on relatively low bandwidth applications e.g. serial coms with a relatively small number of boards. I would be surprised if 5 boards caused this issue but I am not an expert in USB protocol so I can't be more specific. It can be worth spreading your boards aroung your PCs ports. This isn't always a solution as an occasional PC has an internal hub for multiple ports which only actually has one USB controller but for most PCs this is a good way forward. Once we get the up/down function sorted out these potential USB problems should more or less dissappear.

Ok, I will try this a bit later, once I figure out which board it is, Would you care to comment on why the boards only work in usb3 ports for me ?

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testconpastas2
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July 04, 2012, 11:54:31 AM
 #1129

surely this core has frozen.  if you quit cgminer and  try to re-execute the same comand. You'll get a COM error in that port..

If any core gets frozen, accepts stop raising too (in that core) and average hasing speed decrease

please answer with your feedback
No, it's not frozen, it keeps on hashing, just at the very low rate. It's been like this since the beginning.

Isokivi please confirm me that accepts are growing . I sometimes have some boards hashing ( acording to cgminer) but  not accepting shares at all

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yohan
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July 04, 2012, 01:02:03 PM
 #1130



Ok, I will try this a bit later, once I figure out which board it is, Would you care to comment on why the boards only work in usb3 ports for me ?
[/quote]

We have seen it the other way with USB3 being a problem in Linux systems and we think that is a driver issue. However I do need to check this but I think USB3 ports can have a much higher current specification. That might be the difference especially as you have an unpowered hub.
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July 04, 2012, 01:52:41 PM
 #1131

What do you think my issue here is:

3 Cairnsmores plugged in at an unpowered usb hub, all running the twintest bitstream and enterpoints cgminer for it. Windows seven, quad core, plenty of ram (it's a gaming pc).
5 first cores are pushing shares as is to be expected (0-4) But CM5 is doing less than a third of the shares of the other cores, with 0 rejects showing up at cgminer, whereas the other cores have a normal invalid rate (6-16 invalids at aroud 3300 shares hashed per core).

Im starting cgminer with the command: cgminer_twintest -o mint.bitminter.com:8332 -u ME -p MAHPASS --disable-gpu -S noauto -S\\.\COM22 -S \\.\COM23 -S \\.\COM26 -S \\.\COM27 -S \\.\COM30 -S \\.\COM31

If some relevant info is missing please just ask me.

Just a guess, may you forgot to flash one FPGA with the twin_test bitstream and it is still the old shipping_test ? If im right perhaps you can detect the board when you check the LED activity when a share was found. Should be flash green when twin_test and red for shipping_test

xc3sprog –c cm1 –p 0 –Ixc6lx150.bit twin_test.bit <return>
xc3sprog –c cm1 –p 1 –Ixc6lx150.bit twin_test.bit <return>
xc3sprog –c cm1 –p 2 –Ixc6lx150.bit twin_test.bit <return>
xc3sprog –c cm1 –p 3 –Ixc6lx150.bit twin_test.bit <return>

My assumption is that every FPGA has its own flash and that needs to program. Unless there are any useful documentation about architecture etc. its all only a guess.

zefir
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July 04, 2012, 04:31:24 PM
 #1132

Just a guess, may you forgot to flash one FPGA with the twin_test bitstream and it is still the old shipping_test ? If im right perhaps you can detect the board when you check the LED activity when a share was found. Should be flash green when twin_test and red for shipping_test

xc3sprog –c cm1 –p 0 –Ixc6lx150.bit twin_test.bit <return>
xc3sprog –c cm1 –p 1 –Ixc6lx150.bit twin_test.bit <return>
xc3sprog –c cm1 –p 2 –Ixc6lx150.bit twin_test.bit <return>
xc3sprog –c cm1 –p 3 –Ixc6lx150.bit twin_test.bit <return>

My assumption is that every FPGA has its own flash and that needs to program. Unless there are any useful documentation about architecture etc. its all only a guess.



I assumed that for the twin-test it is enough to flash FPGAs 0 and 3, since the other two are not operational in that mode. Any indication that this might cause problems?

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July 04, 2012, 04:51:58 PM
 #1133

with twintest only -p0 and -p3 are needed.


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yohan
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July 04, 2012, 07:27:07 PM
 #1134

Just a guess, may you forgot to flash one FPGA with the twin_test bitstream and it is still the old shipping_test ? If im right perhaps you can detect the board when you check the LED activity when a share was found. Should be flash green when twin_test and red for shipping_test

xc3sprog –c cm1 –p 0 –Ixc6lx150.bit twin_test.bit <return>
xc3sprog –c cm1 –p 1 –Ixc6lx150.bit twin_test.bit <return>
xc3sprog –c cm1 –p 2 –Ixc6lx150.bit twin_test.bit <return>
xc3sprog –c cm1 –p 3 –Ixc6lx150.bit twin_test.bit <return>

My assumption is that every FPGA has its own flash and that needs to program. Unless there are any useful documentation about architecture etc. its all only a guess.



I assumed that for the twin-test it is enough to flash FPGAs 0 and 3, since the other two are not operational in that mode. Any indication that this might cause problems?

No problems just doing the 2.
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July 05, 2012, 07:29:36 AM
 #1135

Advance Warning

There are 1 or 2 people on our June delivery promise who have not responded to the notification that their unit is ready. We can only speculate why that might be but we do need to release reserved stock from our pending shelves in order to satisfy our general customer demand for more units and as fast as we can deliver. So some time later next week we be doing an order purge for anyone on a June delivery promise who has not responded, and that means orders will be cancelled from our side and you will lose your right to the offer price and your place in the queue.

We will do something similar in a few weeks time for July promise orders and so on until we eventually reach the point where Cairnsmore1 is a stock board with no pre-order structure.

Yohan
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July 05, 2012, 08:00:58 AM
 #1136

would someone with a jtag cable mind giving the new TML bitstream a whirl? it has unconfirmed support for cairnsmore1. http://www.tricone-mining.com/tml.html
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July 05, 2012, 09:19:08 AM
 #1137

Which FPGA pair is the right for the Icarus bitstream?   P 0 and P 1?
What happens when I flash the wrong pair? Is there a risk for the FPGA IO Cells due the crossed TX/RX? Does the right DIP switch setting disconnect the net between the FPGA pairs?

Is there a block diagram which shows the position of FPGA correlating to p X

There is a new bitstream from ET, seems no connection between devices are required, every FPGA is handled as own hashing device.
When I flash the “"david”" bitstream (included in the jar file) via xc3sprog tool, am I able to use his java tool to mine? What would be the correct setting for the DIP switches?

Thx Hpman
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July 05, 2012, 10:02:35 AM
 #1138

Which FPGA pair is the right for the Icarus bitstream?   P 0 and P 1?
What happens when I flash the wrong pair? Is there a risk for the FPGA IO Cells due the crossed TX/RX? Does the right DIP switch setting disconnect the net between the FPGA pairs?

Is there a block diagram which shows the position of FPGA correlating to p X

There is a new bitstream from ET, seems no connection between devices are required, every FPGA is handled as own hashing device.
When I flash the “"david”" bitstream (included in the jar file) via xc3sprog tool, am I able to use his java tool to mine? What would be the correct setting for the DIP switches?

Thx Hpman

P0 and P3 are the ones for the twin. If dip switches are set as recommended then P1, P2 are held in reset. That avoids any problems if you make sure on those dip switches. The positions go clockwise from the top left (cables to left side). No problems if flash the wrong parts you just won't get the expected peformance.

The ET bitstream we have not worked with as yet so no advice we can give there as yet. We can support individual FPGAs but that might need a Controller update.
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July 05, 2012, 10:32:24 AM
 #1139

I would start trying with the eldentyrell bitstream, but after 30 minutes of reading I still dont have a clue how to even start he's miner on a windows machine.
[edit]
After some more research it has become clear that the jtag cable is required.
And after messaging Yohan I now know that enterpoint wont bother looking at this bitstream for a couple of days. Also both Enterpoint and elldentyrell are saying they need information on oneandother and either is imo bothering to communicate with oneandother.


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July 05, 2012, 12:07:19 PM
 #1140

Advance Warning

There are 1 or 2 people on our June delivery promise who have not responded to the notification that their unit is ready. We can only speculate why that might be but we do need to release reserved stock from our pending shelves in order to satisfy our general customer demand for more units and as fast as we can deliver. So some time later next week we be doing an order purge for anyone on a June delivery promise who has not responded, and that means orders will be cancelled from our side and you will lose your right to the offer price and your place in the queue.

We will do something similar in a few weeks time for July promise orders and so on until we eventually reach the point where Cairnsmore1 is a stock board with no pre-order structure.

Yohan

I've requested payment info several times, never got any. I got e-mail from you on 16th of june that my VAT had been verified.

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www.bitfury.com
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