ASICMINER: Entering the Future of ASIC Mining by Inventing It

[necro_nemesis]

FYI: There are more docs and a video in the Google drive 'Specs' folder:

https://drive.google.com/?authuser=0#folders/0ByWHHc0u_thNMWtQeDNiT2duU0E

Looking over the data sheet again I am trying to appreciate the requirement for the secondary clock range:

bs decides the operating mode. When bs=0, the range of core clock frequency is 200MHz-400MHz. When bs=1, the range of core clock frequency is 375MHz-750MHz.

RM's test results were at 360MHz which falls in the range of the first setting. What would the purpose of the other clock frequency settings be if they start considerably higher than where it hashes near design? Given test results I assume 375 to be in the area of overclocking but the document also refers to an input oscillator of 20Mhz running the core at 400Mhz as typical. Then there's this range beyond that.

Can someone more knowledgeable in this area comment?

Edit: I have a theory. If one could cool the ASIC sufficiently it may serve a specific purpose at the expense of power efficiency.

[antirack]

FYI: There are more docs and a video in the Google drive 'Specs' folder:

https://drive.google.com/?authuser=0#folders/0ByWHHc0u_thNMWtQeDNiT2duU0E

Looking over the data sheet again I am trying to appreciate the requirement for the secondary clock range:

bs decides the operating mode. When bs=0, the range of core clock frequency is 200MHz-400MHz. When bs=1, the range of core clock frequency is 375MHz-750MHz.

RM's test results were at 360MHz which falls in the range of the first setting. What would the purpose of the other clock frequency settings be if they start considerably higher than where it hashes near design? Given test results I assume 375 to be in the area of overclocking but the document also refers to an input oscillator of 20Mhz running the core at 400Mhz as typical. Then there's this range beyond that.

Can someone more knowledgeable in this area comment?

Edit: I have a theory. If one could cool the ASIC sufficiently it may serve a specific purpose at the expense of power efficiency.

If you cool your ASICs (or CPUs) sufficiently, your reduce leak currents and you reduce the power consumption of the chip. For Intel Xeon Phi Coprocessors that would be 10% of reduction if you keep the junction temperature (Tj) below 95C, in addition to the energy savings due to the efficient cooling. Chips can also be pushed harder if they are cooled better. And so can power circuits. It has a multidimensional impact.

[necro_nemesis]

FYI: There are more docs and a video in the Google drive 'Specs' folder:

https://drive.google.com/?authuser=0#folders/0ByWHHc0u_thNMWtQeDNiT2duU0E

Looking over the data sheet again I am trying to appreciate the requirement for the secondary clock range:

bs decides the operating mode. When bs=0, the range of core clock frequency is 200MHz-400MHz. When bs=1, the range of core clock frequency is 375MHz-750MHz.

RM's test results were at 360MHz which falls in the range of the first setting. What would the purpose of the other clock frequency settings be if they start considerably higher than where it hashes near design? Given test results I assume 375 to be in the area of overclocking but the document also refers to an input oscillator of 20Mhz running the core at 400Mhz as typical. Then there's this range beyond that.

Can someone more knowledgeable in this area comment?

Edit: I have a theory. If one could cool the ASIC sufficiently it may serve a specific purpose at the expense of power efficiency.

If you cool your ASICs (or CPUs) sufficiently, your reduce leak currents and you reduce the power consumption of the chip. For Intel Xeon Phi Coprocessors that would be 10% of reduction if you keep the junction temperature (Tj) below 95C, in addition to the energy savings due to the efficient cooling. Chips can also be pushed harder if they are cooled better. And so can power circuits. It has a multidimensional impact.

Not only from a cost savings perspective but also wrt leakage as mentioned 40nm appears to be more advantageous if you intend to push the ASICs harder. The efficiency of an ASIC in the bitcoin universe is a tradeoff between power costs and mining revenue once infrastructure is covered. This leads me to question whether this range of core speeds has specific application for immersion cooled mining with the intent to overclock the ASICs when it's economically advantageous. If the math and physics work IMHO it's brilliant as it caters to both air and liquid cooled systems.

[minerpumpkin]

Is this immersion cooling proposal directed at hammer ASICs or are we talking about AM as well? This is confusing?

https://bitcointalk.org/index.php?topic=422243.msg6290126#msg6290126

[jimmothy]

Is this immersion cooling proposal directed at hammer ASICs or are we talking about AM as well? This is confusing?

https://bitcointalk.org/index.php?topic=422243.msg6290126#msg6290126

Should be able to work for any asic/chip.

[minerpumpkin]

Is this immersion cooling proposal directed at hammer ASICs or are we talking about AM as well? This is confusing?

https://bitcointalk.org/index.php?topic=422243.msg6290126#msg6290126

Should be able to work for any asic/chip.

But where's this coming from? What about those chip specifications? We always stressed how AM was involved with Allied Control immersion cooling

[antirack]

It's coming from the link I posted a page or two earlier.

Wasp uses AM BE200 chips in their hammer boards. So do all the other Asicminer chip buyers.

[tinyfox266]

no dividends for a couple of weeks. Is there anything wrong?

[freedomno1]

no dividends for a couple of weeks. Is there anything wrong?

Nothing wrong just kind of quiet waiting for gen 3 and the current miners not finding that many blocks

[tinyfox266]

no dividends for a couple of weeks. Is there anything wrong?

Nothing wrong just kind of quiet waiting for gen 3 and the current miners not finding that many blocks

have fried cat ever revealed some info about  the current status of the company or gen 3?  When it can distribute the dividends again?

[empoweoqwj]

no dividends for a couple of weeks. Is there anything wrong?

Nothing wrong just kind of quiet waiting for gen 3 and the current miners not finding that many blocks

have fried cat ever revealed some info about  the current status of the company or gen 3?  When it can distribute the dividends again?

all the info is in this thread. just read the last 5-10 pages and you will know what is going on, its not that hard.

[freedomno1]

no dividends for a couple of weeks. Is there anything wrong?

Nothing wrong just kind of quiet waiting for gen 3 and the current miners not finding that many blocks

have fried cat ever revealed some info about  the current status of the company or gen 3?  When it can distribute the dividends again?

all the info is in this thread. just read the last 5-10 pages and you will know what is going on, its not that hard.

That too guess you can stalk Friedcat says if you want as well although it doesn't mention any Rockxie related stuff
https://twitter.com/FriedcatSays

[antirack]

Friedcat has spoken:

Update

The documents as well as the (verified & produced) sample design are out:

Schematics - https://mega.co.nz/#!uNMkFZoI!lnlRehlynQQzNRfQ87_UYek1RtrOUvLZ6a074XeRqlo

Reference PCB File - https://mega.co.nz/#!DZVHgS6D!6pmTsmrito8rfVJJ-etvznOtUcalbAT6vU-C8EqY0_I

datasheet - https://docs.google.com/document/d/1_dmXzyMqtr7tVZukk2DAJih2sRq5jDy5DQPkwCce570/edit?usp=sharing

bonding list - https://docs.google.com/spreadsheet/ccc?key=0Al1fvFT7Sd5bdFFZSUllNW5seVRfM01kcDVqZkJfdFE&usp=sharing

9x9 package pictures -
https://drive.google.com/file/d/0B11fvFT7Sd5bUV90cFN4cEhTNEk/edit?usp=sharing
https://drive.google.com/file/d/0B11fvFT7Sd5banZkMDZqSTBGTEE/edit?usp=sharing
https://drive.google.com/file/d/0B11fvFT7Sd5bWjh6MmJsMFpCYkU/edit?usp=sharing

8x8 package picture -
https://mega.co.nz/#!DA1mBJzB!7hFnoT8ZYQd1d30m2oHbuscD36cCQ4ou7stsr5Lo03Y

The package we are using is 9mmx9mm, but it might be partly switched to 8mmx8mm.
Also, we plan to increase the center pad size to at least 7mmx7mm, so please leave enough margin on the PCB to avoid unnecessary re-designs.

[minerpumpkin]

We need to dissect any possible differences to prior information. Friedcat, what's the consumption, price and availability date?

[antirack]

Friedcat, what's the consumption, price and availability date?

I believe the power consumption will somewhat depend on the PCB implementation and the DC to DC power circuit on the board. I expect there will be boards with slightly varying power consumption.

The only thing we know today is preliminary numbers from Rockxie who did some test boards, but he had some (unrelated to BE200) component troubles. He did not post his final results yet as far as I know.

[romerun]

MOOOON

[freedomno1]

Not sure if I recall someone discussing this already or not, but what is your opinion on the Samsung GlobalFoundaries partnership and will it have any impact on future chip releases from Asicminer? Not a wafer person so hopefully not just asking a weird question.

http://www.theregister.co.uk/2014/04/17/samsung_globalfoundries_ink_exclusive_multiyear_14nm_finfet_deal/
http://online.wsj.com/news/articles/SB10001424052702304626304579508052587689582?mg=reno64-wsj&url=http%3A%2F%2Fonline.wsj.com%2Farticle%2FSB10001424052702304626304579508052587689582.html

Samsung and GlobalFoundries have announced a collaborative agreement that will enable 14-nanometer FinFET chippery to be manufactured at Samsung's fabs in Hwaseong, South Korea and Austin, Texas, as well as at GlobalFoundries' fab in Saratoga, New York.

"This is a paradigm change to the foundry landscape," GlobalFoundries VP of product management Ana Hunter said in an announcement video.

http://vimeo.com/92152458

[antirack]

Not sure if I recall someone discussing this already or not, but what is your opinion on the Samsung GlobalFoundaries partnership and will it have any impact on future chip releases from Asicminer? Not a wafer person so hopefully not just asking a weird question.

http://www.theregister.co.uk/2014/04/17/samsung_globalfoundries_ink_exclusive_multiyear_14nm_finfet_deal/
http://online.wsj.com/news/articles/SB10001424052702304626304579508052587689582?mg=reno64-wsj&url=http%3A%2F%2Fonline.wsj.com%2Farticle%2FSB10001424052702304626304579508052587689582.html

Samsung and GlobalFoundries have announced a collaborative agreement that will enable 14-nanometer FinFET chippery to be manufactured at Samsung's fabs in Hwaseong, South Korea and Austin, Texas, as well as at GlobalFoundries' fab in Saratoga, New York.

"This is a paradigm change to the foundry landscape," GlobalFoundries VP of product management Ana Hunter said in an announcement video.

http://vimeo.com/92152458

It doesn't matter, sooner or later ASICMiner will take over both of them.
(and then move on to make 3D mutli-stack 14nm Bitcoin ASICs)

[rudi]

Also, we plan to increase the center pad size to at least 7mmx7mm,

Any ideas what this means? What does the center pad do, why and how will it be increased in size?

[antirack]

Also, we plan to increase the center pad size to at least 7mmx7mm,

Any ideas what this means? What does the center pad do, why and how will it be increased in size?

Improved heat transfer from chip to PCB.

Some info on the QFN package and board mounting of a QFN packaged chip.
http://www.atmel.com/images/doc8583.pdf