Swedish ASIC miner company kncminer.com

[erk]

Link for proof please.  You don't make a package size of 3000mm2 if you have tiny chips . . .

More nonsense, Pentium III was 49.5 x 49.5mm, Pentium 4 53.3mm x 53.3mm  so 55 x 55mm is hardly unusual considering you are trying to dissipate twice the heat of those old processors.

Having math difficulty?

The Pentium III had a die size of 80mm2 (Coppermine version):
http://ark.intel.com/products/27531/Intel-Pentium-III-Processor-1_13-GHz-256K-Cache-133-MHz-FSB
That's 8mm x 10mm.  A fraction of the size you thought it was.

The Pentium 4 die size was 131mm2
http://ark.intel.com/products/27438/Intel-Pentium-4-Processor-2_40-GHz-512K-Cache-533-MHz-FSB
That's about 11mm x 11.9mm  Also a fraction of the size you thought it was.

55 x 55mm is 3025mm2
- 37.8 times the die size of the Pentium 3
- 23.1 times the die size of the Pentium 4

Now, I can do this all day long, so please continue.  

WTF are you on about? The only chip spec KNCminer have published is the package size 55mm x 55mm I don't you where you are coming up with this die size nonsense. Please point me to a release from KNCminer that talks about their die size.

Chip Progress report

 

The more technical audience amongst our customers have been asking for a lot details on the chips we will use. The information we have available to you today is that Jupiter will be a 4 chip design and Saturn a 2 chip design.

This means that we can achieve a minimum of 100GH/s per chip. Which we think most people will agree, puts us far ahead of our current competitors.

Our ASIC package selection has been optimized, allowing the use of a smaller package. The selected package is a 55mm x 55mm HFCBGA package (2046 ball count), optimized for maximum thermal characteristics.

https://www.kncminer.com/news/news-22

You obviously need new glasses, or simply don't understand the terms "die" and "package" properly.

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[bkpduke]

I've been in, and written for, the chip industry a very long time.  I know exactly what I am talking about and the difference between "package" and "die".

You don't make a 3000mm2 package size for a TINY chip.  Even if the actual chip die size is 1/4 the package size, that is a gigantic CPU.  TSMC, GlobalFoundries, and UMC don't even let you make die sizes over 600mm2 without very good reasons and special provisions in your contracts.  Why?  because they cannot meet the yield goals they advertise at those sizes.


And you couldn't even google the correct die sizes for a P3 and P4, yet you stated them as "fact".   

[Milan77]

I dont care about size, even like bigger hips, can cool them more easily, I care about functionality and price per ghash.

[bkpduke]

I dont care about size, even like bigger hips, can cool them more easily, I care about functionality and price per ghash.

Die size is directly proportional to price.  Larger dies cost much more to produce because of the lower yields.

So yes, you should care about die size because it means it will make it harder to KNC to meet their target production yields.  The foundry charges the same (by the wafer), so if you have more broken chips per wafer because the die size is high, then you have to raise the price on your "good" chips just to break even.

[Spelon]

I'd be very surprised if their chip is anywhere near for example an intel xeon in complexity. While I have no facts to act on, I'd find it very unlikely that their die should have the same wafer yield failure since I'm pretty sure they ain't packing 6.8b transistors per chip.

[bkpduke]

I'd be very surprised if their chip is anywhere near for example an intel xeon in complexity. While I have no facts to act on, I'd find it very unlikely that their die should have the same wafer yield failure since I'm pretty sure they ain't packing 6.8b transistors per chip.

Transistor complexity is only one factor that affects yields, and it is one of the smaller ones.

The MOST important factor is defect density of the wafer itself.  No matter how good you are at manufacturing, your wafers will have microscopic defects in them, and when the chips are etched over these defects they usually result in non-functional chips.  At best, if you get lucky and the defect occurs in a non-critical area of the CPU, then you can shut that off in post-processing and have a "partially functioning" CPU.

This is where smaller die sizes are key, because they result in higher yields.  Defect density in the wafers is approximately constant, and therefore if you have smaller dies, then you can toss away the defect chips and still have a very high yield.  When each CPU starts to occupy larger and larger surface areas, the chances of their being a critical defect goes up, and therefore yield goes down.

It just boils down to simple math, and this is why companies like Intel and AMD always strive to be as efficient as possible in transistors per mm2 of die area.  They know that as the die gets bigger, the yield drops like a stone, and profits go along with it (even when you own your own fab, like Intel).

[Cablez]

I'd be very surprised if their chip is anywhere near for example an intel xeon in complexity. While I have no facts to act on, I'd find it very unlikely that their die should have the same wafer yield failure since I'm pretty sure they ain't packing 6.8b transistors per chip.

Transistor complexity is only one factor that affects yields, and it is one of the smaller ones.

The MOST important factor is defect density of the wafer itself.  No matter how good you are at manufacturing, your wafers will have microscopic defects in them, and when the chips are etched over these defects they usually result in non-functional chips.  At best, if you get lucky and the defect occurs in a non-critical area of the CPU, then you can shut that off in post-processing and have a "partially functioning" CPU.

This is where smaller die sizes are key, because they result in higher yields.  Defect density in the wafers is approximately constant, and therefore if you have smaller dies, then you can toss away the defect chips and still have a very high yield.  When each CPU starts to occupy larger and larger surface areas, the chances of their being a critical defect goes up, and therefore yield goes down.

It just boils down to simple math, and this is why companies like Intel and AMD always strive to be as efficient as possible in transistors per mm2 of die area.  They know that as the die gets bigger, the yield drops like a stone, and profits go along with it (even when you own your own fab, like Intel).

Yes, but would this really apply to a large chip that has mostly replicated sections (hashing engines). I would think that Orsoc would have designed it in such a way as they could shut down sections of the chip that have defects. That would make the most sense economically.

[bkpduke]

I'd be very surprised if their chip is anywhere near for example an intel xeon in complexity. While I have no facts to act on, I'd find it very unlikely that their die should have the same wafer yield failure since I'm pretty sure they ain't packing 6.8b transistors per chip.

Transistor complexity is only one factor that affects yields, and it is one of the smaller ones.

The MOST important factor is defect density of the wafer itself.  No matter how good you are at manufacturing, your wafers will have microscopic defects in them, and when the chips are etched over these defects they usually result in non-functional chips.  At best, if you get lucky and the defect occurs in a non-critical area of the CPU, then you can shut that off in post-processing and have a "partially functioning" CPU.

This is where smaller die sizes are key, because they result in higher yields.  Defect density in the wafers is approximately constant, and therefore if you have smaller dies, then you can toss away the defect chips and still have a very high yield.  When each CPU starts to occupy larger and larger surface areas, the chances of their being a critical defect goes up, and therefore yield goes down.

It just boils down to simple math, and this is why companies like Intel and AMD always strive to be as efficient as possible in transistors per mm2 of die area.  They know that as the die gets bigger, the yield drops like a stone, and profits go along with it (even when you own your own fab, like Intel).

Yes, but would this really apply to a large chip that has mostly replicated sections (hashing engines). I would think that Orsoc would have designed it in such a way as they could shut down sections of the chip that have defects. That would make the most sense economically.

As I have mentioned earlier, it depends on where in the chip the defect is.  Certain parts, if the defect lies in them, you can forget salvaging the chip.

Also, building in "redundancy" like what you have mentioned is doubled-edged sword.  The bigger you make the chip, the more likely you are to have a defect result in a non-functional chip.


GPU (not CPU) builders have used this for 15 years now.  This is why you see AMD/Nvidia release multiple parts with various numbers of active "shader" units in the product (i.e. 7830 vs. 7850 vs 7870).  They are all made from the same design, but this is a way for companies to recoup some of the loss in post-processing.  By pulling partially functional chips and sell them at lower price points.


I suspect we will see something similar out of KNC.


Oh, and for those following BFL (who isn't, right?), they are already running into this.  It is why you see so much variability is the GH/s of the products they release.  Some of the chips are only partially functional.

And the BFL chip is a lot smaller than this one, so just scale that variability up even more for the KNC design (granted, they are 65nm vs. 28nm - but it all comes down to die SIZE for defects, not so much lithography node).

[bkpduke]

One more thing - this is why moving from say a 55nm node to a 28nm node for building your chips is SO important.  It allows you to pack the same number of chips in a much smaller area, thereby reducing the odds that you have defects in critical areas, and thereby pushing up your yield.  It why companies like Intel spend BILLIONS per year developing new, smaller, process nodes.

It also has the added benefit of:
1) allowing you to push up clock speed (MHz/GHz) and staying within your thermal confines
2) making more chips per wafer (wafer cost is reasonably fixed, so the more you can pack on, the better)


Now, one thing I have not seen mentioned, but is a very real possibility, is that KNC may be able to push up the clock speed on their chips to get a lot more GH/s out of them than the competition.  That's a very real benefit of being built on 28nm.


Gentlemen, we are at the VERY beginning of a very interesting war that will be waged between the different manufacturers.  Things which will overall affect who wins out are (in no particular order):
1) Chip design (both in terms of SHA256 processors per die, and clock speed)
2) Lithography Node - smaller is better (28nm vs. 55nm), but smaller is orders of magnitude more expensive (this is why Avalon started at 110nm, to get something CHEAP out the door)
3) Board design - if you have more power per chip, your board design can be cheaper
4) Thermal limitations - if you do not require exotic cooling mechanisms, your time to market is much faster.


Going to be an interesting 12-24 months for sure.


I am amazed that if a company like Intel wanted to quickly design, build, and host in-house their own setup, the could literally capture > 75% of bitcoin production in a very short time.  It all comes down to CPU design AND manufacturing process.  Both of which Intel is king of the entire world in.

[Milan77]

I dont care about size, even like bigger hips, can cool them more easily, I care about functionality and price per ghash.

Die size is directly proportional to price.  Larger dies cost much more to produce because of the lower yields.

So yes, you should care about die size because it means it will make it harder to KNC to meet their target production yields.  The foundry charges the same (by the wafer), so if you have more broken chips per wafer because the die size is high, then you have to raise the price on your "good" chips just to break even.

Technically speaking you are 100 % right, but still I must say again, as customer, I don't care for size if specification and price are acceptable. (mind paradox, I know, don't mind on that).

[bkpduke]

Good information, still sad that you compare BFL (A company that has NEVER created an ASIC before) with OrSoC (A company that has been doing it for 10 years) and suggest they will have similar issues.

LOL, I know, not a popular comparison.

But, keep this in mind - neither of them OWN a fabrication facility.  Both have to outsource production of their design elsewhere.  This means that they are both at the mercy of someone else's defect density and chip yield from a wafer.

[Loredo]

While there's a lull in the debate, and since it's almost the weekend, how about a little ASIC porn?

While there is no indication that OrSoC is involved with this organization, the pictures and discussions are pretty cool.

http://www.europractice-ic.com/docs/Annual_report_2012.pdf

[ultrix]

Good information, still sad that you compare BFL (A company that has NEVER created an ASIC before) with OrSoC (A company that has been doing it for 10 years) and suggest they will have similar issues.

LOL, I know, not a popular comparison.

But, keep this in mind - neither of them OWN a fabrication facility.  Both have to outsource production of their design elsewhere.  This means that they are both at the mercy of someone else's defect density and chip yield from a wafer.

So by your logic Intel, IBM, and Fujitsu are the only CPU manufacturers and Intel the only GPU manufacturer?   Outsourcing isn't a black and white issue.  If you go the BFL route, you hand the project entirely to someone else.  If you go the KNC route you use the foundry's standard cell library, but its up to you to do design validation.   Or you can go the bitfury route and largely ignore the standard cell library and go full custom.   In each of these scenerios there are risks and benefits that are mitigated by experience with the process.  BFL didn't know the first thing about IC manufacture or the process involved.  OrSOC has experience doing standard cell ASICs.  Don't know about on their selected foundry's 28nm process, but most of the differences are extrapolated into DRCs by Cadence/Synopsis after loading the foundry's standard cell library.  Bitfury is just a smart guy from what I can tell and spent his own time and money to develop his ASIC with what from my understanding was little prior experience.   But he did it.

[Kuroth]

I think one thing that I am kind of worried about that I have not heard much talk about in this thread is how will Knc do the Burn ins for us and it not cause a bottleneck?   Now if they REALLY get my BTC address and Burn in using my address then I wont care if it takes them another month to ship my unit, as long as it is running and paying me..  BUT this is a pretty major thing to pull off IMO and I hope it dont slow them down overall.    Talk over at BFL is this is one theory of why BFL slowed so much as the Burn in was taking up a lot more time/space/people then they had the planned for..


I hope Knc is on top of this and has a plan..

[Loredo]

One more thing - this is why moving from say a 55nm node to a 28nm node for building your chips is SO important.

  [...snip]

Going to be an interesting 12-24 months for sure.


I am amazed that if a company like Intel wanted to quickly design, build, and host in-house their own setup, the could literally capture > 75% of bitcoin production in a very short time.  It all comes down to CPU design AND manufacturing process.  Both of which Intel is king of the entire world in.

This is, IMO, a real good succinct explanation of the development landscape.  Thanks for it.

Also IMO, the reasons Intel hasn't and won't do anything with bitcoins are two:

First, they are too mainstream and too involved to venture outside the confines of Establishment,

and

Second, all-in, risk adjusted, there just aren't enough zeros on the numbers.

[DPoS]

I don't think many of us expect some cute iMiner like BFL wanted..  This is more like a trainset that they just keep growing and growing.  

It is another reason why I ordered two Saturns because these might be pretty big and I rather heat two rooms than one.  

[Phoenix1969]

BKPDUKE
28nm die size, wrapped in a 55mm package, with a 2048 ball count for thermal characteristics.
Wtf is so hard to understand? If you don't believe them, then don't buy.

[dropt]

Good information, still sad that you compare BFL (A company that has NEVER created an ASIC before) with OrSoC (A company that has been doing it for 10 years) and suggest they will have similar issues.

So we know KnC didn't design their ASIC, ORSoC did.  Want to know another neat fact? BFL didn't design their ASIC,  Chronicle Tech. did.  Guess how long Chronicle has been in business?  

[Phoenix1969]

Good information, still sad that you compare BFL (A company that has NEVER created an ASIC before) with OrSoC (A company that has been doing it for 10 years) and suggest they will have similar issues.

So we know KnC didn't design their ASIC, ORSoC did.  Want to know another neat fact? BFL didn't design their ASIC,  Chronicle Tech. did.  Guess how long Chronicle has been in business?  

Did you know that Orsoc, Kennmar & Cole, and KncMiner all share directors?, are partners? All this is in the knc threads....post your proof please. I don't think it's beneficial anymore to even read this thread anymore, since so much misinformation is flying around.
BTW, Chronicle Tech is a software company, not an ASIC designer.

[bkpduke]

BKPDUKE
28nm die size, wrapped in a 55mm package, with a 2048 ball count for thermal characteristics.
Wtf is so hard to understand? If you don't believe them, then don't buy.

Do you even realize what you said?  You just said you are going to have the equivalent of a FOOTBALL FIELD to mount a CPU the size of a lunchbox.

WTF is so hard to understand is 28nm is the LINE WIDTH not the AREA.  Please don't comment when it is clear you have @#$% for brains.