Nope the FIFO / BRAM doesn't meet timing specs. The Fmax for K7 speed grade -2 FIFO is 543.77MHz. But my FPGA still runs fine at 600MHz.
Whats your target temperature ? I've load now the bitstream from your project and the temp is grown to >76 °C which is to near to 80° C(?) limit of the commercial chips which are used I mean on KC705. I've put an old cpu 8cm fan so little air flow is from the pdc side to the kintex. Better I will clock to 550 MHz so temp of pdcs and kintex will not override. Cheers... Does your k7 have a heatsink + fan? Something like this. http://sls.smugmug.com/Professional/Platform-Blue/5440422_d6JQGF/1530805068_bv3hrdM#!i=1530805068&k=bv3hrdM |
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Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.
Is that a single hash core reporting 600MHz operation in the static timing analysis using a -2 speed device? It's the KC705 experimental design from github which used DSP48E blocks on the K7. The reported speed is actual hashing speed. Does the static timing analysis show that all paths are below 1.6ns? Or did you just check that your particular device runs at 600MHz? Nope the FIFO / BRAM doesn't meet timing specs. The Fmax for K7 speed grade -2 FIFO is 543.77MHz. But my FPGA still runs fine at 600MHz. I guess it's stretching the limits. Also it could vary chip to chip, since -3 speed grade has a Fmax of 601.32MHz. http://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf, Pg 32, Table 31 |
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Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.
Is that a single hash core reporting 600MHz operation in the static timing analysis using a -2 speed device? It's the KC705 experimental design from github which used DSP48E blocks on the K7. The reported speed is actual hashing speed. |
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Link pmed. I have requested a pull for the open-source fpga project on github. once approved i will upload the project there as well. Power on chip according to vivado is 12.5W. |
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Just re-implemented the DSP design by fpgaminer for 600MHz operation. Nothing major. It needs -2 or -3 speed grade chips for that speed.
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Hey I got the KC705 board working at 600MH/s. Anybody interested in the 600MH/s bitstream? I can share it for download.
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BTW, can the Minimodule plus work without the baseboard or is the baseboard required to make the MMP work?
It needs some sort of baseboard to supply it with the 8 different power supply voltages it wants - Avnet seem to want $500 for the baseboard and $300 for the PSU board, so it might be worth the effort of designing your own, especially as the MMP FPGA board seems to sell below the cost of a 7k325 FPGA, and seems to come with a license file to unlock the 7k325 device in the Xilinx tools! The MMP board does look interesting, but it seems to only have 10A 1.0v core supply - can someone please tell me what the current KC705 design is using at 400MH/s? Xilinx vivado estimates the power draw of the 7K325 Chip is ~11W. It's infact hashing at 500MH/s right now with minor modification to the code. The VCCInt power module is getting a bit hot for my liking at 500MH/s. IMO the voltage reg chips on that module need heatsinks. Thanks for that - according to the manual the MMP power board only has 6A of VCCINT - which at 1.0v is just 6W  - have you got a fan you can point at the regulator chips? So I am using the KC705 board, it's got a 1.0V @ 20A Vccint regulator. The chips are so small (smaller than my smallest thumbnails  ) , that it's very difficult to affix a heatsink w/o shorting something. Any ideas would be appreciated. Right now I have placed the board next to the airconditioner. |
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BTW, can the Minimodule plus work without the baseboard or is the baseboard required to make the MMP work?
It needs some sort of baseboard to supply it with the 8 different power supply voltages it wants - Avnet seem to want $500 for the baseboard and $300 for the PSU board, so it might be worth the effort of designing your own, especially as the MMP FPGA board seems to sell below the cost of a 7k325 FPGA, and seems to come with a license file to unlock the 7k325 device in the Xilinx tools! The MMP board does look interesting, but it seems to only have 10A 1.0v core supply - can someone please tell me what the current KC705 design is using at 400MH/s? Xilinx vivado estimates the power draw of the 7K325 Chip is ~11W. It's infact hashing at 500MH/s right now with minor modification to the code. The VCCInt power module is getting a bit hot for my liking at 500MH/s. IMO the voltage reg chips on that module need heatsinks. |
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BTW, can the Minimodule plus work without the baseboard or is the baseboard required to make the MMP work?
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Hi, I've used the KC705 design for the AVNet MMP KC7T325 to get an running bitstream today. I've both, the KC705 and the AVNet MMP http://www.em.avnet.com/en-us/design/drc/Pages/Mini-Module-Plus-Development-Kit-Supporting-the-Kintex-7-FPGA-Family.aspx. I've bougth to of the modules for only 600 € per board which is an good price, but it is not so fast as the KC705. It will produce after a couple of time much more invalid shares although the temp is nearby the same as by the KC705. The code itself looks like mostly compatible but only the kc705_pins.xdc has been changed to: set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_p}]
set_property IOSTANDARD LVDS [get_ports {sys_clk_p}]
set_property LOC AA10 [get_ports {sys_clk_p}]
set_property VCCAUX_IO DONTCARE [get_ports {sys_clk_n}]
set_property IOSTANDARD LVDS [get_ports {sys_clk_n}]
set_property LOC AB10 [get_ports {sys_clk_n}]
set_property IOSTANDARD LVCMOS25 [get_ports {uart_rx}]
set_property LOC U22 [get_ports {uart_rx}]
set_property IOSTANDARD LVCMOS25 [get_ports {uart_tx}]
set_property LOC V22 [get_ports {uart_tx}]
I couldn't find an design for that modules for vivado so I used as target design simple xc7k325tffg676-1 which I guessed is soldered. Generally also the code is working on cheap AVNet MMP, too, but not with the effency at 400 MHz. I think it should been decrease by a small value but I've not the experience to do that at the moment with the given hashing clock multiplier. My last question: I saw that there is already an design finished wich use only less than the half of DSPs so two of the rings could been implemented instead of one, so the mining is doubled? Cheers... I think the problem is that Avnet MMP uses -1 speed grade FPGA while KC705 uses -2 speed grade. Try to configure the clock generator for lower clock speeds for hash_clock down from 400MH to 375MHz, 350MHz, etc. |
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users, please update Batch#2 orders received successfully.
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I've been asked a few times about a mining script for the current KC705 firmware. I wrote a plugin for Modular Python Bitcoin Miner. Here's the message I sent to someone about it: I uploaded the custom MBPM module, which is compatible with the current KC705 mining code, here: https://mega.co.nz/#!Oh5HTDRB!C0RLYW4yZN8gbg38FfgLpzmKFcseOql3Xx1i_gXTfdMYou'll want to download a copy of MPBM's testing branch. Then extract the above archive into Code: modules/fpgamining such that you end up with: Code: modules/fpgamining/kc705_uart/__init__.py modules/fpgamining/kc705_uart/kc705uartworker.py Once you start MPBM, you can now add a KC705 Worker by openning up the MPBM web-interface ( http://127.0.0.1:8832) and clicking the "Workers" button on the left. On Windows, I ran MPBM under Cygwin, and the "Port" ended up being /dev/com2 for me. The Baudrate is 115200. ~fpgaminer I haven't had a chance to clean it up and put it on the repo yet. +1 Okay here are the steps for Windows environment that I followed a) Compile / Implement / Generate bitstream for KC705 board using Xilinx Vivado tool. b) use iMpact to download the bitstream to 7k325 c) Install cygwin d) Install python using cygwin installer (setup.exe) e) download pyserial and install pyserial with python running inside Cygwin e.1) make sure your kc705 serial port is COM1 f) download MPBM, and add the kc705 uart source in the recommended directories g) run MPBM h) create new Kc705 uart worker i) mine! |
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Black = sexy! Thanks for the video. |
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@Bitsyncom, Please show other batch #2 ers some love!!! When do you think other Batch#2 orders will ship? Any updates would be awesome.  |
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So yesterday i want to cash out all my found in mtgox and gues what. Mtgox cancel my withdraw because they said they have some bank limits right now. I have lvl2 verification account with higest ammount of cash withdraw and still cant get my cash out of mtgox so i guess the only way to get out of here is to buy bitcoins... thats pathetic... Now i understand why theres a such a rally.
wrong board, post here https://bitcointalk.org/index.php?board=85.0 |
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I have 2 confirmation, 4 units. Updated
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Looks like forum member fpgaminer received his avalon(s)
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