In the current Xilinx Xcell Journal: Issue 84 is an article about "Efficient Bitcoin Miner System Implemented on Zynq SoC" which is also mentioning this project.

The magazin can be downloaded here:
http://www.xilinx.com/publications/archives/xcell/Xcell84.pdf

At the time, Intel just launched their Itanium CPUs. So a month later, I got 2 brand new Itanium machines, and one with 128gigs of RAM and another with 64gigs. This had to be 12 years ago. At the time, I had more RAM, than most people’s hard drives. It was awesome.   

Just a quick update. I did finally get the OpenCL Kernel done and compiling. But I had problems running it, and one of my power supplies went bad. I have two power supplies for my computer, since I have two 5970 cards. I don’t know if the two where related or not. I believe the power supply is under warranty, so I will have to send it in. I do have a spare, plus I can always run one power supply with one card plugged in.

But I am going to skip the OpenCL. I have gotten my second pre-design done, and it has better space savings then the first. I will not report the space savings, since I don’t want people trying to figure out what I am doing. However it is another good space savings jump, but not as good as the last one. Also, I can continue to pipeline the data too. The design is very performance driven. It should be easy to meet timing with this design. I don’t think I am going to get any better than this design, so I am going to start writing the Verilog code starting tomorrow, while my wife and daughter are out. I drew out the first few stages, so I have a guide to follow.

Jasinlee has a project running at http://ltcfpga.com/ which seems fairly advanced (but NOT opensource)

I'm currently working on an opensource implementation (just for the LOLs), using the on-chip FPGA ram (it needs 1Mbit per hasher core). I've got the simulation running fine using a register array for ram. Unfortunately I'm only estimating around 1khash/sec performance per hasher core. The next step is to port it to my DE0-Nano board (it can only fit half the scratchpad, so its going to interpolate which is even slower). I'll post it on my github once its in a presentable state.

I had a great night last night for the Evil Genius project. I got my first pre-design partially working in software. The size of the SHA-256 circuit was reduced by 0.52 to 0.37 (not giving out the exact size reduction). The next step is I am going to build a full software implementation in an OpenCL Kernel. I don’t believe the performance of the Kernel will be better than anything out there, because I cannot increase the GPUs hardware and GPUs are not specifically built for SHA-256. It is more of a proof of concept thing. Also, I will still be able to pipeline the work with the smaller design. So every clock cycle, you will get data. After the full implementation, I will see if I can patent the design method. The circuit has 64 stages for one hash, so 128 stages for the double hash.

This is just the first pre-design. I still have some other things I want to try out. But this is very promising. I was very excited last night. I cannot wait to start trying some other things out to see how far I can push the SHA-256 circuit.  

Edit: It should be reduce ‘to’ 0.52-0.37, instead of ‘by’. I am cutting myself short  . So now the circuit is basically half the size or smaller, so the performance increase will be 2x or more.

Yes, this feature is built-in on chip. We are currently testing this feature.

Maybe a good idea will also be implenmentig salted SHA1 algo for Nokia SL3 unlocking by bruteforce method.

I will use this thread to update my progress. I will update every once in a while to let people know my progress and how well the circuits are preforming. 

I will be creating custom digital circuits of a SHA2-256 Double Hashers for Bitcoin mining. I have already started on the first stage. The project will be written in Verilog. I chose Verilog, because it has better controls at the gate level than VHDL. I will not be using any C code for the hashing circuits. However I might use C code for the registers and connections to the computer, IE USB plug, and set-up data.

Looking at the Open Source FPGA code, I believe I can make a really good improvement over the Open Source code, which is converted C. I have vast experience in digital design and I have worked on many ASIC projects. However, I have not worked on a FPGA before, but I have worked alongside FPGA programmers to know the major problems that affect FPGAs.

To get more info on my background, go here:
http://www.cryptoextractor.com/crypto/author.html

Depending on the results, three things will happen. If I get really great results, then I would probably make some boards and sell them. If I get good results, I will probably buy old FPGA boards and reprogram them, and mine with them. I might sell some of the re-programmed boards. The last would be if I got OK results. Then I would just release the code as Open Source.

berlin is awful. Be careful there

 Each avalons is performing at >80ghash and you say its beaten?

I live in Beijing one of the most polluted cities in the world. I bet my lungs are also dusty.

Look what showed up today  

These are not for August product - of course that goes directly to pcb fab.  Tytus sent me this.