Looking at this thread, and also at the protocol discussion going on over on BFL forums, I sense the need for a single standard open protocol that can be used for all communication between host-side miner software, and external miner devices (FPGAs, ASICs, etc).

Once hashed out (pun intended), a standard set of libraries could be made and maintained that implemented the protocol in popular languages (C, Java, Python, Ruby, what-have-you), with proper unit tests and all.

There could even be a standards body formed, that would issue certifications of conformity to specific devices running specific firmwares, for those vendors who desired such a thing, and issue cute holographic stickers displaying the certified product's name and firmware hash.

https://forums.butterflylabs.com/announcements/597-bitforce-sc-communication-protocol-draft.html

If only someone who wasn't me would head up the effort...

Well, there may be ways to make it work like that, but 115,200 bps is really incredibly slow, and would not likely be fast enough to be useful for Scrypt-based mining.

A more proper approach would be to use a memory controller, with a high speed interface of some kind back to the FPGA.  Have a look at these links:

http://www.avnet-israel.co.il/download/downloadPresentations/Presentations/xfest07_GD_memory.pdf
http://www.xilinx.com/products/technology/memory-interfacing/index.htm
http://www.xilinx.com/products/intellectual-property/MIG.htm

I would really recommend writing your own CPU miner first, to get a better idea of how mining works.

Shouldn't be more'n a few dozen lines in a decently high-level language.

I'm just saying that the technology is already out there.  I was talking about subsequent generations, not implying that we should expect anything better than 65nm in the first-gen chips.

BFL themselves have hinted at a move to 45nm chips for the next generation in the Bitcoin Magazine interview.

More chips means more PCB area, and more traces to route.  How many pins do you suppose are used on those QFN-40 packages, and how many of them need a dedicated connection to the MCU per chip rather than being able to be chained together bus style?

Also consider that a 30GH/s device based on 130nm technology may consume as much as 200 watts.  Depending on what voltage the chips run at, that can add up to quite a few amps that the power-bearing PCB traces will need to be capable of carrying every step of the way.

Cooling complexity will also increase with the chip count, more decoupling caps will be needed, etc.


So they're going to need 38,000 chips to reach their "first batch" hashrate of 12TH/s.  Yowza.

I have a few TL-WR703Ns around already, with their 4MB of flash.  I suppose I could add USB storage if more is needed.

I guess it's possible to solo mine without having to download and store the entire blockchain somewhere.  I've just never seen it done.  I imagine Avalon will just hook up to a pool server or a regular bitcoind node, and not by itself be capable of solo mining, correct?

95 chips.  That'd be 315.789473684211MH/s per.

There are already smaller process sizes in use today, for those with deep enough pockets.  Intel's Ivy Bridge chips use a 22nm process, vs BFL's 65nm.  Remember that the size advantage saves space in two dimensions, such that halving the process size results in a quartering of the die area.

Another redesign possibility is on the logic level, designing the hashing engines to fit into a smaller die area, to scale to higher clock speeds, and most importantly, to consume less energy.

There are probably also other areas where the design can be improved upon, such as improved thermal coupling of the chip die to the chip package.  Using a flip-chip design for instance.

Wasn't there to be a demo of some sort also?

Can't wait for it.

Can you elaborate on this?  What is different about a "traditional" car engine to cause the large difference in efficiency that you describe, when used to generate electricity?

For me, it would be when someone ships a competing product, and is taking new orders.

I see the website has a countdown to shipping time now.

http://www.avalon-asics.com/

A die picture, you say?  It even shows the purdy rainbow diffraction effect.

You would seem to imply that the described die has already been produced.

Surely our collective leg is being pulled...

It's nice to see the possibility of needing a respin being mentioned up front, as well as a timeline given for when this will be known.  That's in contrast to a couple other vendors I can think of.

I think if you catch the golden nonce, it's worth 150 points and the match is over.

This all raises an interesting question.

Ostensibly BFL is working hard on making their ASIC products, and they have produced a very real looking PCB.

But what if Nasser is pulling a fast one on the rest of the company, and instead of developing an ASIC, he's been pocketing the dev funds and stringing them along.  He's probably pretty insulated half a world away in France.  Clock buffers, anyone?

Same.  I want something I can tweak, pwn, and make my bitch.  Having it sit off in some data center and never even seeing it takes all the fun out of it.  I also want a conversation piece.

Similarly, I would never buy a gold or silver ETN.  I would only buy physical metal that I take possession of.  9/10ths of the law blah blah.

FTFY

These chips crunch near a billion hashes per second.  Losing a small handful of those each second is miniscule.

Mine along on your CPU if you wanna make up the difference and then some.

The contest is for an FPGA single.  There was some question a while back whether the winners had received their hardware, to which Josh stated "they have all been shipped".  I imaging there would have been more said about it if ppl had not actually received it.

I don't really like the contest either.  Unfortunately if called out, BFL can truthfully say "but our competition does it too!"