2 students + 2 professor to port already available code
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Guys you do realise he is trying to improve FPGA efficiency, and patent the results? This is a hell of a long way from open source.
OMG he's been outed as a Capitalist! Someone kill him before he gets away! ![Shocked](https://bitcointalk.org/Smileys/default/shocked.gif) Improving on stuff and making a profit from his efforts! This cannot be endured... ![Roll Eyes](https://bitcointalk.org/Smileys/default/rolleyes.gif) At the time, Intel just launched their Itanium CPUs. So a month later, I got 2 brand new Itanium machines, and one with 128gigs of RAM and another with 64gigs. This had to be 12 years ago. At the time, I had more RAM, than most people’s hard drives. It was awesome. Itaniums had $hitty performance for all our X86 code, even recompiled with icc. Personal experience on SGI ALtix Itanium2 based servers. I think it was an EPIC sic. fail ![Wink](https://bitcointalk.org/Smileys/default/wink.gif)
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Just a quick update. I did finally get the OpenCL Kernel done and compiling. But I had problems running it, and one of my power supplies went bad. I have two power supplies for my computer, since I have two 5970 cards. I don’t know if the two where related or not. I believe the power supply is under warranty, so I will have to send it in. I do have a spare, plus I can always run one power supply with one card plugged in.
But I am going to skip the OpenCL. I have gotten my second pre-design done, and it has better space savings then the first. I will not report the space savings, since I don’t want people trying to figure out what I am doing. However it is another good space savings jump, but not as good as the last one. Also, I can continue to pipeline the data too. The design is very performance driven. It should be easy to meet timing with this design. I don’t think I am going to get any better than this design, so I am going to start writing the Verilog code starting tomorrow, while my wife and daughter are out. I drew out the first few stages, so I have a guide to follow.
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why don't you try developing scrypt mining for LTC for opensource community. There's avery high demand for it IMO.
Jasinlee has a project running at http://ltcfpga.com/ which seems fairly advanced (but NOT opensource) I'm currently working on an opensource implementation (just for the LOLs), using the on-chip FPGA ram (it needs 1Mbit per hasher core). I've got the simulation running fine using a register array for ram. Unfortunately I'm only estimating around 1khash/sec performance per hasher core. The next step is to port it to my DE0-Nano board (it can only fit half the scratchpad, so its going to interpolate which is even slower). I'll post it on my github once its in a presentable state. That's awesome ![Smiley](https://bitcointalk.org/Smileys/default/smiley.gif) kudos to you. Would it be possible to load it on github so others can also try to use your scrypt miner?
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The cup warmer will be a reality finally
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Okay got it. Sometimes the synthesis software can also do logic optimization, which could reduce the size of hardware, though it's very rarely succesful in substantiial reduction of hand optimized designs.
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I had a great night last night for the Evil Genius project. I got my first pre-design partially working in software. The size of the SHA-256 circuit was reduced by 0.52 to 0.37 (not giving out the exact size reduction). The next step is I am going to build a full software implementation in an OpenCL Kernel. I don’t believe the performance of the Kernel will be better than anything out there, because I cannot increase the GPUs hardware and GPUs are not specifically built for SHA-256. It is more of a proof of concept thing. Also, I will still be able to pipeline the work with the smaller design. So every clock cycle, you will get data. After the full implementation, I will see if I can patent the design method. The circuit has 64 stages for one hash, so 128 stages for the double hash. This is just the first pre-design. I still have some other things I want to try out. But this is very promising. I was very excited last night. I cannot wait to start trying some other things out to see how far I can push the SHA-256 circuit. Edit: It should be reduce ‘to’ 0.52-0.37, instead of ‘by’. I am cutting myself short ![Smiley](https://bitcointalk.org/Smileys/default/smiley.gif) . So now the circuit is basically half the size or smaller, so the performance increase will be 2x or more. May I ask did you obtain the size reduction on a HDL module or was it something else?
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Sorry ![Smiley](https://bitcointalk.org/Smileys/default/smiley.gif) lol ![Smiley](https://bitcointalk.org/Smileys/default/smiley.gif) I mean chips that will be soldered onto the August boards ![Wink](https://bitcointalk.org/Smileys/default/wink.gif) Having been bitten by another ASIC vendor, I wanted to exercise caution. BTW is this feature still present in the chip? 1) the chips have a build in power management / leveling system that we want to use (to save on power and additional pcb components: to power the boards and a string/series of chips with let's say 7.2V directly) ... this is a crazy idea and we have to check if this works (we must avoid resonance buildup and power voltage osculations) before ordering many boards [[ comments here are very welcome !!! :-) ]] Yes, this feature is built-in on chip. We are currently testing this feature. Okay if it works, even lower BOM ![Smiley](https://bitcointalk.org/Smileys/default/smiley.gif) Maybe it can be implemented on rev 2 H-boards for October delivery.
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Maybe a good idea will also be implenmentig salted SHA1 algo for Nokia SL3 unlocking by bruteforce method.
Any URL listing the problem? It looks interesting.
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BTW I had to login to google.com to access the charts. Why in heaven's name MR peak is in Nov 2012? Did they think it would arrive before reward halving?
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Sorry ![Smiley](https://bitcointalk.org/Smileys/default/smiley.gif) lol ![Smiley](https://bitcointalk.org/Smileys/default/smiley.gif) I mean chips that will be soldered onto the August boards ![Wink](https://bitcointalk.org/Smileys/default/wink.gif) Having been bitten by another ASIC vendor, I wanted to exercise caution. BTW is this feature still present in the chip? 1) the chips have a build in power management / leveling system that we want to use (to save on power and additional pcb components: to power the boards and a string/series of chips with let's say 7.2V directly) ... this is a crazy idea and we have to check if this works (we must avoid resonance buildup and power voltage osculations) before ordering many boards [[ comments here are very welcome !!! :-) ]]
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Are the bitfury chips ready? i mean packaged and all?
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I will use this thread to update my progress. I will update every once in a while to let people know my progress and how well the circuits are preforming. I will be creating custom digital circuits of a SHA2-256 Double Hashers for Bitcoin mining. I have already started on the first stage. The project will be written in Verilog. I chose Verilog, because it has better controls at the gate level than VHDL. I will not be using any C code for the hashing circuits. However I might use C code for the registers and connections to the computer, IE USB plug, and set-up data. Looking at the Open Source FPGA code, I believe I can make a really good improvement over the Open Source code, which is converted C. I have vast experience in digital design and I have worked on many ASIC projects. However, I have not worked on a FPGA before, but I have worked alongside FPGA programmers to know the major problems that affect FPGAs. To get more info on my background, go here: http://www.cryptoextractor.com/crypto/author.htmlDepending on the results, three things will happen. If I get really great results, then I would probably make some boards and sell them. If I get good results, I will probably buy old FPGA boards and reprogram them, and mine with them. I might sell some of the re-programmed boards. The last would be if I got OK results. Then I would just release the code as Open Source. why don't you try developing scrypt mining for LTC for opensource community. There's avery high demand for it IMO.
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There was once a wiki for such things, but now I'm having some trouble finding it.
berlin is awful. Be careful there Why do you say this?
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Free bump....why does that case/modules look so beaten and dusty already?
Each avalons is performing at >80ghash and you say its beaten? ![Smiley](https://bitcointalk.org/Smileys/default/smiley.gif) I live in Beijing one of the most polluted cities in the world. I bet my lungs are also dusty. Out of topic, but how would you compare living costs in Beijing to NYC?
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Guys, we need to get it > $1000, I am itching to use the mBTC feature embedded in the client ![Wink](https://bitcointalk.org/Smileys/default/wink.gif) It will help with liquidity a bit as well ![Wink](https://bitcointalk.org/Smileys/default/wink.gif)
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btw, did you try to connect it to a raspberry PI or any pc if ur Avalon's router is broken. If the controller card is broken then it's a gone case.
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70BTC Possible to Please post a pic as well with your login name? Also who is escrow?
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Look what showed up today ![Shocked](https://bitcointalk.org/Smileys/default/shocked.gif) These are not for August product - of course that goes directly to pcb fab. Tytus sent me this. ![](https://ip.bitcointalk.org/?u=https%3A%2F%2Fmegabigpower.com%2Fshop%2Fimage%2Fcache%2Fdata%2Fbitfury_reel-500x500.jpg&t=663&c=7kt3E31MDR6u1A) Great, I am guessing these are 3000 chips ![Smiley](https://bitcointalk.org/Smileys/default/smiley.gif) Things are moving fast! Keep up the good work!
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