Swedish ASIC miner company kncminer.com

[Bitcoinorama]

With a 59% or more rise in difficulty next increase (https://blockchain.info/charts/hash-rate) I wonder whether I should cancel my Saturn order?

All manufacturers seem to have large orders due to be shipped before KnCMiner ships so Jumps of 110,000GH/s per fortnight may continue several more times if not each difficulty change.

Current jump is more than total capacity beginning of June!

I had been thinking of upgrading Saturn to Jupiter. Now it's unlikely. More likely I cancel during next few weeks while I still can!

Hopefully their planned March 2014 offering will make a good investment & ROI.

Your estimates are highly exaggerated. You'll see tonight

Yip, your right.

Have since learned difficulty changes based on speed last 2016 blocks solved. Current set was due 25^th so completed way to quickly.

If 297TH/s figure I saw becomes average over future 2016 blocks they'll be solved very quickly. Then my estimate will apply. Only off by a week or so

You may be interested in taking a look here if you want to get your hands dirty, it's the code within the protocol limiting hashrate increase;

https://github.com/bitcoin/bitcoin/blob/d62a1947be5350ed60066ccacc7aba43bbdf48fb/src/main.cpp#L875

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[Otago]

With a 59% or more rise in difficulty next increase (https://blockchain.info/charts/hash-rate) I wonder whether I should cancel my Saturn order?

All manufacturers seem to have large orders due to be shipped before KnCMiner ships so Jumps of 110,000GH/s per fortnight may continue several more times if not each difficulty change.

Current jump is more than total capacity beginning of June!

I had been thinking of upgrading Saturn to Jupiter. Now it's unlikely. More likely I cancel during next few weeks while I still can!

Hopefully their planned March 2014 offering will make a good investment & ROI.

Based on this, the game is over. No point in anyone buying any ASICs anymore as they will never return anything worthwhile, so not much point in anyone thinking about building a next gen machine never mind selling one as they are always going to be fighting a losing battle?

IF a KnC machine that's not even built yet can't profit, why would the next gen be any different?

Same thing as when CPU, GPU, FPGA & ASIC gen1. Will be reduction in pricing & increase in performance.

BFL offered 4.5GH to start raising this to 1,500Gh/s (when they thought they could build it into one machine). Gen2 will probably start close to 1Th/s maybe around Mercury pricing if the growth continues. And we only have to wait till March!

BTW my difficulty projection is off by one cycle. Will be following set of 2106 block hit by recent days huge increase if maintained.

[erk]

With a 59% or more rise in difficulty next increase (https://blockchain.info/charts/hash-rate) I wonder whether I should cancel my

How did you come up with 59%?  The next difficulty increase is predicted at 20% in a few hours time.

[Otago]

With a 59% or more rise in difficulty next increase (https://blockchain.info/charts/hash-rate) I wonder whether I should cancel my

How did you come up with 59%?  The next difficulty increase is predicted at 20% in a few hours time.

Difficulty change is based on speed of last 2016 blocks solved. Current set was due for completion on 25^th.

If 297TH/s figure I saw becomes average over next 2016 blocks they'll be solved very quickly. Then my estimate would apply for the following set of 2106 blocks.

BTW: hash rate has dropped back to 256TH/s. Someone was testing a lot of capacity.

[titomane]

Now that there is new data on die size, I updated the GH/wafer table:

Code:

wafer(mm)   chip         process(nm)  die(mm^2)   GH/s(per die)      DpW   GH/s(per wafer)
300         KnC              28        441,00          25         128          3200,00
300         bitfury          55         14,44           2           4717          9434,00
300         bfl              65         56,25           4           1167          4668,00
300         asciminer(?)    130         17,50           0,333       3877          1291,04
300         avalon          110         16,13           0,282       4214          1188,35
300         asciminer(?)    130         21,7            0,333       3112          1036,30
(DpW, die per wafer; yield percentage not taken into account)

Die size is less than 336mm2.
I think 18x18mm

Another detail for a better table. As far as I know, 130nm(110nm) are still manufactured based on 200mm wafers. 65nm(55nm) nodes were the first built with 300mm.

Ummmm. KnC is doing a 28nm process and getting only a third of the GH/s per wafer that bitfury is getting at 55nm?

What's more concerning is the 25GH/s per die. Where is the data that says they are using 4 dies per package?

HERE

The slides says that it's only one die, containing 4 self-contained cores (quads).
A more correct table looks like that:
-> KnC die size estimated based on technology scaling
-> Source for Bitfury die size? Seems to be wrong. And chips are specified for 5GH/s per chip (not 2 GH/s)

Code:

wafer(mm)   chip         process(nm)  die(mm^2)   GH/s(per die)      DpW   GH/s(per wafer)
300         KnC              28        120,00           100         589          58904,00
300         bitfury          55         14,44           2           4847          9694,00
300         bfl              65         56,25           4           1244          4976,00
200         asciminer(?)    130         17,50           0,333       1795          597,74
200         avalon          110         16,13           0,282       1947          549,05
200         asciminer(?)    130         21,7            0,333       1447          477,51
(DpW, die per wafer; yield percentage not taken into account)

That is the real 28nm world!

It is more likely that each chip is 4 DIE.
If die has 4cores with total size is 120mm^2 . 20 wafers are more than 1PHs. Why go to work on the second gen?

[HyperMega]

Now that there is new data on die size, I updated the GH/wafer table:

Code:

wafer(mm)   chip         process(nm)  die(mm^2)   GH/s(per die)      DpW   GH/s(per wafer)
300         KnC              28        441,00          25         128          3200,00
300         bitfury          55         14,44           2           4717          9434,00
300         bfl              65         56,25           4           1167          4668,00
300         asciminer(?)    130         17,50           0,333       3877          1291,04
300         avalon          110         16,13           0,282       4214          1188,35
300         asciminer(?)    130         21,7            0,333       3112          1036,30
(DpW, die per wafer; yield percentage not taken into account)

Die size is less than 336mm2.
I think 18x18mm

Another detail for a better table. As far as I know, 130nm(110nm) are still manufactured based on 200mm wafers. 65nm(55nm) nodes were the first built with 300mm.

Ummmm. KnC is doing a 28nm process and getting only a third of the GH/s per wafer that bitfury is getting at 55nm?

What's more concerning is the 25GH/s per die. Where is the data that says they are using 4 dies per package?

HERE

The slides says that it's only one die, containing 4 self-contained cores (quads).
A more correct table looks like that:
-> KnC die size estimated based on technology scaling
-> Source for Bitfury die size? Seems to be wrong. And chips are specified for 5GH/s per chip (not 2 GH/s)

Code:

wafer(mm)   chip         process(nm)  die(mm^2)   GH/s(per die)      DpW   GH/s(per wafer)
300         KnC              28        120,00           100         589          58904,00
300         bitfury          55         14,44           2           4847          9694,00
300         bfl              65         56,25           4           1244          4976,00
200         asciminer(?)    130         17,50           0,333       1795          597,74
200         avalon          110         16,13           0,282       1947          549,05
200         asciminer(?)    130         21,7            0,333       1447          477,51
(DpW, die per wafer; yield percentage not taken into account)

That is the real 28nm world!

It is more likely that each chip is 4 DIE.
If die has 4cores with total size is 120mm^2 . 20 wafers are more than 1PHs. Why go to work on the second gen?

No offence here! Finally is just a question how they dice the wafers. Maybe it would be even wise, to have 4 dies 25 GH/s each in Multi-Chip-Package. But as you said, in sum they probably will have 100 GH/s per 120mm2.

Funny detail, the minimum count of wafers one can order at a foundry is 25 (1 lot)!

It's really a good question, why invest another $1.5M - $2M for a new 28nm full mask set for gen 2 ASIC if you dominate the market with gen 1?

[Bitcoinorama]

No offence here! Finally is just a question how they dice the wafers. Maybe it would be even wise, to have 4 dies 25 GH/s each in Multi-Chip-Package. But as you said, in sum they probably will have 100 GH/s per 120mm2.

Funny detail, the minimum count of wafers one can order at a foundry is 25 (1 lot)!

It's really a good question, why invest another $1.5M - $2M for a new 28nm full mask set for gen 2 ASIC if you dominate the market with gen 1?

Because Gen 1 is purely a rough draft to reach an ASIC race goal.

The chips will do their job, albeit be crude and unrefined.

This chip design is all about minimising risk and playing safe whilst delivering in a timeframe that meets ROI for their crowd sourced investors.

It's literally a prototype that future revisions will expand upon, of which there is a lot of room for improvement.

They couldn't achieve this without pre-orders, and what customers want are ASICs and quickly. So that dictates the design priorities.  Likewise the window for opportunities for requesting pre-orders by start-up ASIC manufacturers and resellers closes after this has been achieved, much the same as competition from non-professional engineering firms like Butterfly Labs, as the benchmark will have been set if KnC realises their ambition and will require genuine specialists to compete successfully, therefore securing a more competent and professional mining landscape for all involved in Bitcoin mining hardware...

Also because as Johan and Sam have both said at the Openday Marcus and team are perfectionists which is why they had to be so hard on them with respect to timeframe. September is the priority. Marcus is not happy with his design, it will work, but not optimally as he would like. So after this first run is out the way, they get to let him of his leash...

[erk]

No offence here! Finally is just a question how they dice the wafers. Maybe it would be even wise, to have 4 dies 25 GH/s each in Multi-Chip-Package. But as you said, in sum they probably will have 100 GH/s per 120mm2.

Funny detail, the minimum count of wafers one can order at a foundry is 25 (1 lot)!

It's really a good question, why invest another $1.5M - $2M for a new 28nm full mask set for gen 2 ASIC if you dominate the market with gen 1?

It may not require new wafers, it might be just an updated product line. eg. 2000watt with 8 chips.

[HyperMega]

Also because as Johan and Sam have both said at the Openday Marcus and team are perfectionists which is why they had to be so hard on them with respect to timeframe. September is the priority. Marcus is not happy with his design, it will work, but not optimally as he would like. So after this first run is out the way, they get to let him of his leash...

Sorry, but my reality looks different. Engineers can't go to their CFOs and say:

"Gen 1 ASIC is working as specified. No major bugs, we can put them into the miners and sell them. But the design is not perfect, please let me do a Gen 2 ASIC."
"Ok, how much would it be?"
"Just another $2M."
"No way! Are you crazy, that are 10 Ferraris!".

Just kidding. But would you invest so much for an gen 2 ASIC without any major technical reason? With respect to efficiency Gen 2 (assuming still in 28nm) will probably have something like 25% more performance while having less power consumption and silicon area (due to design optimization and less margins). Not much compared to the steps in difficulty. Is that another $2M NRE worth?

Developing Gen2 Miners based on Gen1 ASICs (extended product line) would of course make sense commercially and technically.

[titomane]

No offence here! Finally is just a question how they dice the wafers. Maybe it would be even wise, to have 4 dies 25 GH/s each in Multi-Chip-Package. But as you said, in sum they probably will have 100 GH/s per 120mm2.

Funny detail, the minimum count of wafers one can order at a foundry is 25 (1 lot)!

It's really a good question, why invest another $1.5M - $2M for a new 28nm full mask set for gen 2 ASIC if you dominate the market with gen 1?

The hypothesis does not offend ever. Also if you are well explained, like yours so appreciated.

It is important to know ETA chips. It seems that the request was not made ​​in June.

I rely on package change after the 26th June.
https://www.kncminer.com/news/news-22



They say 2046 Balls & now say 2797 Balls
Why and when they decided to change the number of pads?

[Ytterbium]

Because Gen 1 is purely a rough draft to reach an ASIC race goal.

The chips will do their job, albeit be crude and unrefined.

This chip design is all about minimising risk and playing safe whilst delivering in a timeframe that meets ROI for their crowd sourced investors.

It's literally a prototype that future revisions will expand upon, of which there is a lot of room for improvement.

That doesn't really make a lot of sense, once the fixed cost is taken care of, what's the per-chip cost of running another set of wafers?  The first run had to be priced in order to cover the (expensive) R&D costs.  Sure, they could tweak the design but they'd need to run another set of masks, pretty expensive.

The other thing to keep in mind is that their design is probably pretty close to optimal.  Outside of die shrink the amount of improvement per chip by tweaks probably isn't that great.

On the other hand, now that R&D is paid for, they can go ahead and lower the cost of their chips.  Their Gen-2 could simply be 2x as many chips, running at a 75% slower clock, which should reduce power demand and thermal issues per chip - remember, the cooler silicon is, the lower the resistance, which means you get increasing returns on power and temperature if you can reduce power (lower energy from lower clock, means lower temperatures, which means even lower energy due to reduced resistance)  

[Mota]

No offence here! Finally is just a question how they dice the wafers. Maybe it would be even wise, to have 4 dies 25 GH/s each in Multi-Chip-Package. But as you said, in sum they probably will have 100 GH/s per 120mm2.

Funny detail, the minimum count of wafers one can order at a foundry is 25 (1 lot)!

It's really a good question, why invest another $1.5M - $2M for a new 28nm full mask set for gen 2 ASIC if you dominate the market with gen 1?

The hypothesis does not offend ever. Also if you are well explained, like yours so appreciated.

It is important to know ETA chips. It seems that the request was not made ​​in June.

I rely on package change after the 26th June.
https://www.kncminer.com/news/news-22



They say 2046 Balls & now say 2797 Balls
Why and when they decided to change the number of pads?

And why do you assume they HAVE to tell you anything? They told us from the beginning that the specs are not written in stone. They were very forthcoming with information up until now, but some people just can't get enough.

[titomane]

And why do you assume they HAVE to tell you anything? They told us from the beginning that the specs are not written in stone. They were very forthcoming with information up until now, but some people just can't get enough.

Fanboy answer.


I do not assume anything.
Just saying it's a major change in 2046-2797.

[Bitcoinorama]

Personally I'd rather they keep schtum about any design details from now until the chips are in hand.

This gives away wayy too much competitive advantage. I think they've said too much as is.

The money's been raised and spent, there is no doubt they are real and actually undertaking this. All these assumptions and demands for clarification serve no purpose for onlookers aside competitng entities.

I'm happy to switch off and watch from the sidelines for all of 4-6 weeks...

[HyperMega]

No offence here! Finally is just a question how they dice the wafers. Maybe it would be even wise, to have 4 dies 25 GH/s each in Multi-Chip-Package. But as you said, in sum they probably will have 100 GH/s per 120mm2.

Funny detail, the minimum count of wafers one can order at a foundry is 25 (1 lot)!

It's really a good question, why invest another $1.5M - $2M for a new 28nm full mask set for gen 2 ASIC if you dominate the market with gen 1?

The hypothesis does not offend ever. Also if you are well explained, like yours so appreciated.

It is important to know ETA chips. It seems that the request was not made ​​in June.

I rely on package change after the 26th June.
https://www.kncminer.com/news/news-22



They say 2046 Balls & now say 2797 Balls
Why and when they decided to change the number of pads?

I fully agree with you.

The tape-out date (sending the final layout to the fab, ordering the masks and wafers) is the major milestone of any ASIC design project. Every customer/investor should be informed about when this is planned and when it was finally executed (this is at least the case in the "normal" ASIC business world). Because after that the "train has left the station" and the time until wafers leave the fab is somehow predictable.

The layout was probably not final in June, otherwise it would not be possible to change the package later on.

If there is no tape-out in July it is impossible that KnC will have packaged dies in their hands end of September (not talking about delivering fully debugged miners to end customers).

[Ytterbium]

Changing the package doesn't mean they changed the chip itself. If you look at the pin-outs on major chips you'll see a lot of them are redundant, extra power lines and stuff like that. I think they use a lot of lines because the connecting lines are so thin - I would imagine putting a high load on an individual line would damage the chip, so they have a bunch of lines to spread out the power load.

The package they're using has space for extra pins, that doesn't mean they're actually going to be connected to anything, or aren't just going to be used as extra power lines.

[pixl8tr]

Wow! Thats a lot of solder balls per chip.  Is this amount of connections normally soldered reliably in manufacturing?

[titomane]

Changing the package doesn't mean they changed the chip itself. If you look at the pin-outs on major chips you'll see a lot of them are redundant, extra power lines and stuff like that. I think they use a lot of lines because the connecting lines are so thin - I would imagine putting a high load on an individual line would damage the chip, so they have a bunch of lines to spread out the power load.

The package they're using has space for extra pins, that doesn't mean they're actually going to be connected to anything, or aren't just going to be used as extra power lines.

What? If they change pad-balls they change chip, or have had a design error. Prefer to be a chip change that an error.
Not to sound a troll, I am buyer KNC.

[GandalfG]

Wow! Thats a lot of solder balls per chip.  Is this amount of connections normally soldered reliably in manufacturing?

Like the GPU most of that are power lines. About soldering - comes to mind  Xbox CPU reflow

[HyperMega]

Changing the package doesn't mean they changed the chip itself. If you look at the pin-outs on major chips you'll see a lot of them are redundant, extra power lines and stuff like that. I think they use a lot of lines because the connecting lines are so thin - I would imagine putting a high load on an individual line would damage the chip, so they have a bunch of lines to spread out the power load.

The package they're using has space for extra pins, that doesn't mean they're actually going to be connected to anything, or aren't just going to be used as extra power lines.

Could be.

But it's a flip chip design. Therefore normally no real standard packages exists. The internal package substrat has to be designed too and the bump positions have to fit to top metal openings of the chip layout. This process is called package co-design.

If they have a package design from a previous project for reuse, they maybe able to adapt the chip layout to fit to the existing package substrate, which would ease this process a bit. Maybe the orignal 2046 balls were an mistake and they allways meant 2797.

Not that important. A KnC statement like "Tape-out was executed at 22nd July." would clarify all these speculations.