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Author Topic: [ActiveMining] The Official Active Mining Discussion Thread  (Read 479990 times)
Vbs
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September 04, 2013, 11:25:41 PM
 #5341

Most of the trades right now are just short-term flippers buying/selling to other short-term flippers, as there's been no significant time for the news to spread and gather interest of long-term shareholders.
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September 04, 2013, 11:25:47 PM
 #5342

Back to 0.004x. Maybe shareholders need more than a ... pdf ?

That'd be the first time ever.

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September 04, 2013, 11:36:05 PM
 #5343

Back to 0.004x. Maybe shareholders need more than a ... pdf ?

Try http://www.easic.com

Think it hits the press tomorrow.

At the mo there's flippers making a nice profit I expect (and they're on this very thread I'm sure!)

http://www.easic.com/vmc-uses-easic-to-achieve-24-756-ths-bitcoin-miner/
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September 04, 2013, 11:37:44 PM
 #5344

What we really need to know is the die size.

It's possible Labcoin's 65nm chip may take up less space, making their chips potentially more profitable.

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September 04, 2013, 11:43:27 PM
 #5345

What we really need to know is the die size.

It's possible Labcoin's 65nm chip may take up less space, making their chips potentially more profitable.

Labcoin has yet to prove that they developed the 130nm chip (or give any indication that they aren't running a total scam for that matter).  Why don't you worry about that when their "65nm chip" is not a figment of your imagination. 
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September 04, 2013, 11:45:02 PM
 #5346

ffssixtynine, thank you for posting this right away, and for all of the pressure you and the rest applied to get this deal confirmed.

I'm very happy that ActM is no longer the only company with a semiconductor vendor that won't take her to the prom. Smiley

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September 04, 2013, 11:45:21 PM
 #5347

What we really need to know is the die size.

It's possible Labcoin's 65nm chip may take up less space, making their chips potentially more profitable.

If we're talking about futurology, we can also talk about VMC going for standard-cell 28nm, using eAsic's easicopy process and getting chips at pitiful costs (price is y-axis below). Then it's game over. Smiley

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September 04, 2013, 11:58:25 PM
 #5348

What we really need to know is the die size.

It's possible Labcoin's 65nm chip may take up less space, making their chips potentially more profitable.

If we're talking about futurology, we can also talk about VMC going for standard-cell 28nm, using eAsic's easicopy process and getting chips at pitiful costs (price is y-axis below). Then it's game over. Smiley



As you can see on the chart, the cutoff for 'profitability' of using the easicopy instead of nextreme is 300-900 thousand units.  At 25Gh/s, that comes out to:

7.5-22.5 petahash.  

That's the threshold for for it to be profitable for ActM to switch to easicopy.

Assuming he can get 10 chips per board, that's 30-90k boards. At $25/board, that comes out to $750k-$2.2 million for enough boards to put 300-900k chips on.

That means in order for it to be profitable for ActiveMining to go to the easicopy rout to get standard cell asics, he would need to be making an so large he'd have to spend $750-2 million just on the blank PCBs to put them on.

Not impossible. But it's a long way off from what I can tell.

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September 04, 2013, 11:58:41 PM
 #5349

To the MoooN Cheesy



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September 04, 2013, 11:58:47 PM
 #5350

What we really need to know is the die size.

It's possible Labcoin's 65nm chip may take up less space, making their chips potentially more profitable.

If we're talking about futurology, we can also talk about VMC going for standard-cell 28nm, using eAsic's easicopy process and getting chips at pitiful costs (price is y-axis below). Then it's game over. Smiley



Would the ELI5 on this chart basically be that at some point the chips are going to cost next to nothing to produce, therefore any difficulty increases will easily be met via the production of more chips?

Was I helpful or insightful?  Feel free to say thanks! 1PuoasR1dYtNq9yYNJj9NreDAfLEzc3Vpe
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September 05, 2013, 12:00:34 AM
 #5351

To the MoooN Cheesy

Oh come off it. It went to the moon....but just popped in for a bite and then decided it had enough.
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September 05, 2013, 12:03:09 AM
 #5352

To the MoooN Cheesy

Oh come off it. It went to the moon....but just popped in for a bite, ya know?

See that little "Ignore" button under his username?  Click it. Smiley

Was I helpful or insightful?  Feel free to say thanks! 1PuoasR1dYtNq9yYNJj9NreDAfLEzc3Vpe
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September 05, 2013, 12:09:54 AM
 #5353

See that little "Ignore" button under his username?  Click it. Smiley

Oh you mean that box that looks like the color of my piss after heavy kidney damage?
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September 05, 2013, 12:10:00 AM
 #5354

To the MoooN Cheesy

Oh come off it. It went to the moon....but just popped in for a bite and then decided it had enough.

And it will again, but this was so sad...  An ideal opportunity to prove the doubters wrong.  All people had to do was *hold*.  There was no market on burnside's gameserver.  The price would have went through the roof -- but no.  
People started tripping all over each other for a chance to get out Sad  
Confidence inspiring.  
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September 05, 2013, 12:11:13 AM
 #5355

What we really need to know is the die size.

It's possible Labcoin's 65nm chip may take up less space, making their chips potentially more profitable.

If we're talking about futurology, we can also talk about VMC going for standard-cell 28nm, using eAsic's easicopy process and getting chips at pitiful costs (price is y-axis below). Then it's game over. Smiley



As you can see on the chart, the cutoff for 'profitability' of using the easicopy instead of nextreme is 300-900 thousand units.  At 25Gh/s, that comes out to:

7.5-22.5 petahash.  

That's the threshold for for it to be profitable for ActM to switch to easicopy.

Assuming he can get 10 chips per board, that's 30-90k boards. At $25/board, that comes out to $750k-$2.2 million for enough boards to put 300-900k chips on.

That means in order for it to be profitable for ActiveMining to go to the easicopy rout to get standard cell asics, he would need to be making an so large he'd have to spend $750-2 million just on the blank PCBs to put them on.

Not impossible. But it's a long way off from what I can tell.

Your overall analysis is wrong. You are analyzing it as if the transition should only be based on volume to lower unit price. It won't be. The point where it's profitable to go for easicpy is not just based on unit cost, but on whatever possible gains in either hashrate or power consumption from using a standard-cell ASIC. The bigger the gains, the quicker the transition will be done.

Least of all, let's not forget VMC also sells chips in bulk, so there's no money to spend on "blank PCBs" there.
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September 05, 2013, 12:18:57 AM
 #5356

Least of all, let's not forget VMC also sells chips in bulk, so there's no money to spend on "blank PCBs" there.

Someone has to spend the money on those PCBs.  And the point of the chart is that, overall, it will be cheaper to stick with the regular ASICs until you get up to 300k units (per whatever time period they're estimating), it would just be a waste of money otherwise. Obviously, if the power/wattage is better then that will be an additional consideration.

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September 05, 2013, 12:25:15 AM
 #5357

Least of all, let's not forget VMC also sells chips in bulk, so there's no money to spend on "blank PCBs" there.

Someone has to spend the money on those PCBs.  And the point of the chart is that, overall, it will be cheaper to stick with the regular ASICs until you get up to 300k units (per whatever time period they're estimating), it would just be a waste of money otherwise. Obviously, if the power/wattage is better then that will be an additional consideration.

The point of the chart is to compare chip unit price with sales volume, meaning that VMC can/will have access to chip prices that can be competitive with anyone else. This was the original issue you raised, unit price.
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September 05, 2013, 12:31:01 AM
 #5358

Least of all, let's not forget VMC also sells chips in bulk, so there's no money to spend on "blank PCBs" there.

Someone has to spend the money on those PCBs.  And the point of the chart is that, overall, it will be cheaper to stick with the regular ASICs until you get up to 300k units (per whatever time period they're estimating), it would just be a waste of money otherwise. Obviously, if the power/wattage is better then that will be an additional consideration.

The point of the chart is to compare chip unit price with sales volume, meaning that VMC can/will have access to chip prices that can be competitive with anyone else. This was the original issue you raised, unit price.

Not exactly, You won't be able to sell, say, 900k easicopy chips the day after your nextreme chips come out of the fab.  there will be a whole other development process, possibly taking months, before you can sell orders.  Companies like Cointerra/HashFast/ and KnC will be able to sell chips/modules with a much shorter turnaround time, which is pretty critical in the bitcoin space.

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September 05, 2013, 12:36:30 AM
 #5359

Not exactly, You won't be able to sell, say, 900k easicopy chips the day after your nextreme chips come out of the fab.  there will be a whole other development process, possibly taking months, before you can sell orders.  Companies like Cointerra/HashFast/ and KnC will be able to sell chips/modules with a much shorter turnaround time, which is pretty critical in the bitcoin space.

eAsic takes a different and very efficient approach to minimize design time on Nextreme to standard-cell conversion.
Quote
http://www.easic.com/migration-to-cell-based-asic/migration-to-cell-based-asic-simple-design-flow/
The starting point for most easicopy designs is a eASIC Nextreme or Nextreme-2 design. This enables eASIC engineers to leverage much of the work that has already been done from a design that is already successfully in production. In addition, this helps to reduce the overall time to production for the easicopy design.

The easicopy design flow is shown below. At the front end it requires a eASIC Nextreme or Nextreme-2 synthesized netlist and an SDC timing constraints file. After initial synthesis, the design is taken through a traditional cell-based ASIC flow by eASIC engineers. This includes Design For Test (DFT) insertion and synthesis, and then back-end physical implemention which includes floorplanning, I/O ring design, power mesh design, timing driven place and route, timing closure, parasitic extraction, final STA, and tapeout readiness.



eASIC engineers have extensive experience in converting FPGA designs to via-programmable eASIC Nextreme or Nextreme-2 NEW ASIC, and then eASIC Nextreme or Nextreme-2 NEW ASIC designs to cell-based, easicopy ASIC.

Quote
http://www.easic.com/migration-to-cell-based-asic/migration-to-cell-based-asic-risk-mitigation/

Design Risk Mitigation - having successfully converted an FPGA prototype design to eASIC Nextreme or Nextreme-2, eASIC engineers have already made a number of changes that will make the conversion to an easicopy ASIC simpler. In addition your designers will work with the same eASIC engineers that have already helped you to successfully take your eASIC Nextreme or Nextreme-2 design to production.

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September 05, 2013, 12:38:02 AM
 #5360

Not exactly, You won't be able to sell, say, 900k easicopy chips the day after your nextreme chips come out of the fab.  there will be a whole other development process, possibly taking months, before you can sell orders.  Companies like Cointerra/HashFast/ and KnC will be able to sell chips/modules with a much shorter turnaround time, which is pretty critical in the bitcoin space.

eAsic takes a different and very efficient approach to minimize design time on Nextreme to standard-cell conversion.

That's nice.  Unfortunately "minimized" is not a very concrete amount of time.

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