Swedish ASIC miner company kncminer.com

[FeedbackLoop]

Wow!

Thanks for the speedy detailed estimate HyperMega!

Even if some numbers are off we get an idea of how things scale in this type of business.

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[KS]

I doubt that KnC or OrSOC is seen as a big customer for this project, because they probably will not order more than 50 wafers in the first year (which would be already about 3 PH).

3 PetaHash/s ? That's a very interesting number. Could you expand the calculation for us? If I am seeing correctly that would be 10 times the present total network hashing power.

Is 50 wafers some sort of bulk discount number or some sort of standard order? Maybe there;s some minimum amount of wafers?

Thanks!

KnC ASIC will have about 100 GH/s realised with 192 engine IPs (see KnC R&D news from 7/19/2013).

I assume that an engine IP is equivalent to a pipelined hash core. To realise 100 GH/s they must run at a little bit more than 500 MHz, what is feasible in 28nm.

Based on technology scaling (2x more logic on same area form technology node to next technology node) we get based on BFL hash core size (estimated based on BFL die including 16 cores removing spare area and pad frame overhead) from 65(55)nm -> 45(40)nm -> 32(28)nm an estimated area per hash core of 0.6 mm2 in 28nm.

This results in an overall KnC die area of about 115 mm2 (0.6mm2 x 192).
Adding some area for supporting logic, I would say max 120 mm2 would be a good target.

An 28nm 300mm wafer has an area of about 70000 mm2. So we get 583 dies per wafer (assuming 100% yield, not realistic I know, but you can scale it yourself to your yield assumptions).

For 50 wafer:

583 dies/wafer -> 58.3 TH/wafer
50 wafer -> 2915 TH

Minimum ordering at foundries is normally one lot (25 wafer). Maybe also half lots are possible. But keep in mind, additional wafers costs nothing compared to the initial mask costs.

+3000TH. That sounds very scary for anyone wanting to meet ROI. Anyway...

Would they need a 55mmx55mm package for a 11mmx11mm chip??

[timmmers]

Looks like a real Motley Jet-lag crew.

Left to Right;

Sam (KNC), Josh (BFL), ??, Yifu (AVALON)

Who's the guy in the checkered shirt?

That's The Devil, he came to collect on that soul deal because they hadn't delivered as promised.

[Gyrsur]

Looks like a real Motley Jet-lag crew.

Left to Right;

Sam (KNC), Josh (BFL), ??, Yifu (AVALON)

Who's the guy in the checkered shirt?

That's The Devil, he came to collect on that soul deal because they hadn't delivered as promised.

LOOOLLL!!!

Right, therefore his hands are only on BFL and Avalon so far. Means "You belongs to me from now on!" 

[sickpig]

...

I hope this is no information you got from KnC because it can't be correct.

Some semiconductor industry facts:
1) at the moment there is no 28nm fab at all in People's Rep. of China (they are of course working at building ten )
2) TSMC stands for "Taiwan Semiconductor Manufacturing Company", all there fabs including 28nm are in Taiwan
3) The only 28nm GLOBALFOUNDRIES fab (former AMD production side) is fab1 located in Dresden, Germany

Sorry, yes, my bad about GF, although Taiwan is a long disputed province of the People's Republic of China.

I clearly remember someone posting a wild guess about what will be the KnC fab. it costs me quite a few to find it but eventuallly I got it:

https://bitcointalk.org/index.php?topic=232852.msg2584946#msg2584946

it was buried into the 'orama openday report thread. it should be helpful hopefully

[HyperMega]

I doubt that KnC or OrSOC is seen as a big customer for this project, because they probably will not order more than 50 wafers in the first year (which would be already about 3 PH).

3 PetaHash/s ? That's a very interesting number. Could you expand the calculation for us? If I am seeing correctly that would be 10 times the present total network hashing power.

Is 50 wafers some sort of bulk discount number or some sort of standard order? Maybe there;s some minimum amount of wafers?

Thanks!

KnC ASIC will have about 100 GH/s realised with 192 engine IPs (see KnC R&D news from 7/19/2013).

I assume that an engine IP is equivalent to a pipelined hash core. To realise 100 GH/s they must run at a little bit more than 500 MHz, what is feasible in 28nm.

Based on technology scaling (2x more logic on same area form technology node to next technology node) we get based on BFL hash core size (estimated based on BFL die including 16 cores removing spare area and pad frame overhead) from 65(55)nm -> 45(40)nm -> 32(28)nm an estimated area per hash core of 0.6 mm2 in 28nm.

This results in an overall KnC die area of about 115 mm2 (0.6mm2 x 192).
Adding some area for supporting logic, I would say max 120 mm2 would be a good target.

An 28nm 300mm wafer has an area of about 70000 mm2. So we get 583 dies per wafer (assuming 100% yield, not realistic I know, but you can scale it yourself to your yield assumptions).

For 50 wafer:

583 dies/wafer -> 58.3 TH/wafer
50 wafer -> 2915 TH

Minimum ordering at foundries is normally one lot (25 wafer). Maybe also half lots are possible. But keep in mind, additional wafers costs nothing compared to the initial mask costs.

+3000TH. That sounds very scary for anyone wanting to meet ROI. Anyway...

Would they need a 55mmx55mm package for a 11mmx11mm chip??

They choose the package size to handle thermal and power requirements (ir-drop and so on). It's a flip-chip design with a custom package substrat (to be designed to fit to KnC die). In principle there is no problem to put a 11x11mm2 die flip-chip on a 55x55mm2 package substrat.

Wire-bond would be a different story. It would not be possible to bond a tiny die in a huge package, because the bond wires would get to long. But KnC is NOT doing a wire bond design like e.g. Avalon/ASICMiner or Bitfury.

[KS]

...

I hope this is no information you got from KnC because it can't be correct.

Some semiconductor industry facts:
1) at the moment there is no 28nm fab at all in People's Rep. of China (they are of course working at building ten )
2) TSMC stands for "Taiwan Semiconductor Manufacturing Company", all there fabs including 28nm are in Taiwan
3) The only 28nm GLOBALFOUNDRIES fab (former AMD production side) is fab1 located in Dresden, Germany

Sorry, yes, my bad about GF, although Taiwan is a long disputed province of the People's Republic of China.

I clearly remember someone posting a wild guess about what will be the KnC fab. it costs me quite a few to find it but eventuallly I got it:

https://bitcointalk.org/index.php?topic=232852.msg2584946#msg2584946

it was buried into the 'orama openday report thread. it should be helpful hopefully

I think you dug up the packaging company, not the fab.

[sickpig]

...

I hope this is no information you got from KnC because it can't be correct.

Some semiconductor industry facts:
1) at the moment there is no 28nm fab at all in People's Rep. of China (they are of course working at building ten )
2) TSMC stands for "Taiwan Semiconductor Manufacturing Company", all there fabs including 28nm are in Taiwan
3) The only 28nm GLOBALFOUNDRIES fab (former AMD production side) is fab1 located in Dresden, Germany

Sorry, yes, my bad about GF, although Taiwan is a long disputed province of the People's Republic of China.

I clearly remember someone posting a wild guess about what will be the KnC fab. it costs me quite a few to find it but eventuallly I got it:

https://bitcointalk.org/index.php?topic=232852.msg2584946#msg2584946

it was buried into the 'orama openday report thread. it should be helpful hopefully

I think you dug up the packaging company, not the fab.

yep, you're probably right.

I don't know why but I've taken for granted that they would use ASE Inc facility to produce the chip.


edit 1: fix grammar error

[HyperMega]

...

I hope this is no information you got from KnC because it can't be correct.

Some semiconductor industry facts:
1) at the moment there is no 28nm fab at all in People's Rep. of China (they are of course working at building ten )
2) TSMC stands for "Taiwan Semiconductor Manufacturing Company", all there fabs including 28nm are in Taiwan
3) The only 28nm GLOBALFOUNDRIES fab (former AMD production side) is fab1 located in Dresden, Germany

Sorry, yes, my bad about GF, although Taiwan is a long disputed province of the People's Republic of China.

I clearly remember someone posting a wild guess about what will be the KnC fab. it costs me quite a few to find it but eventuallly I got it:

https://bitcointalk.org/index.php?topic=232852.msg2584946#msg2584946

it was buried into the 'orama openday report thread. it should be helpful hopefully

I read all this open day report stuff.

There are some weird statements in this report e.g. "we sent the RTL to the fab".
Sorry, but every fab I know would say: "Thanks, but what should we do with your RTL, we need an GDS-file!", which is the file format of the final layout of the chip.

What they did is a so called "RTL hand-off" to a design enablement partner of the foundry, who does or did the layout generation and sign-off for them and uploads the GDS-File to the foundry. It is not known who this partner is, could be e.g. GUC or eSilicon.

The only statement at the open day which hints to the foundry is "chip will be manufactured in Asia". The only pure play foundry with 28nm fabs in Asia is TSMC. Samsung doesn't count, it's an IDM (integrated device manufacturer), which does not offer its manufacturing capacitance to everybody.

But they also said at the open day (mid of June), that they are still about selecting the foundry, so maybe something changed here later on.

[KS]

...

I hope this is no information you got from KnC because it can't be correct.

Some semiconductor industry facts:
1) at the moment there is no 28nm fab at all in People's Rep. of China (they are of course working at building ten )
2) TSMC stands for "Taiwan Semiconductor Manufacturing Company", all there fabs including 28nm are in Taiwan
3) The only 28nm GLOBALFOUNDRIES fab (former AMD production side) is fab1 located in Dresden, Germany

Sorry, yes, my bad about GF, although Taiwan is a long disputed province of the People's Republic of China.

I clearly remember someone posting a wild guess about what will be the KnC fab. it costs me quite a few to find it but eventuallly I got it:

https://bitcointalk.org/index.php?topic=232852.msg2584946#msg2584946

it was buried into the 'orama openday report thread. it should be helpful hopefully

I think you dug up the packaging company, not the fab.

yep, you're probably right.

I don't know why but I've taken for granted that they would ASE Inc facility to produce the chip.

That's marketing: they're a "leader", "full featured", "turnkey solutions" and whatnot THEN you realize they do not actually fabricate the silicon.

I think they'll be using Altera (who's using TSMC) for the fab. They were working on a special deal for the Mars, using Altera FPGA, and Altera can turn their FPGA code (RTL? forgot the exact TLA) into an ASIC.

[KS]

I doubt that KnC or OrSOC is seen as a big customer for this project, because they probably will not order more than 50 wafers in the first year (which would be already about 3 PH).

3 PetaHash/s ? That's a very interesting number. Could you expand the calculation for us? If I am seeing correctly that would be 10 times the present total network hashing power.

Is 50 wafers some sort of bulk discount number or some sort of standard order? Maybe there;s some minimum amount of wafers?

Thanks!

KnC ASIC will have about 100 GH/s realised with 192 engine IPs (see KnC R&D news from 7/19/2013).

I assume that an engine IP is equivalent to a pipelined hash core. To realise 100 GH/s they must run at a little bit more than 500 MHz, what is feasible in 28nm.

Based on technology scaling (2x more logic on same area form technology node to next technology node) we get based on BFL hash core size (estimated based on BFL die including 16 cores removing spare area and pad frame overhead) from 65(55)nm -> 45(40)nm -> 32(28)nm an estimated area per hash core of 0.6 mm2 in 28nm.

This results in an overall KnC die area of about 115 mm2 (0.6mm2 x 192).
Adding some area for supporting logic, I would say max 120 mm2 would be a good target.

An 28nm 300mm wafer has an area of about 70000 mm2. So we get 583 dies per wafer (assuming 100% yield, not realistic I know, but you can scale it yourself to your yield assumptions).

For 50 wafer:

583 dies/wafer -> 58.3 TH/wafer
50 wafer -> 2915 TH

Minimum ordering at foundries is normally one lot (25 wafer). Maybe also half lots are possible. But keep in mind, additional wafers costs nothing compared to the initial mask costs.

+3000TH. That sounds very scary for anyone wanting to meet ROI. Anyway...

Would they need a 55mmx55mm package for a 11mmx11mm chip??

They choose the package size to handle thermal and power requirements (ir-drop and so on). It's a flip-chip design with a custom package substrat (to be designed to fit to KnC die). In principle there is no problem to put a 11x11mm2 die flip-chip on a 55x55mm2 package substrat.

Wire-bond would be a different story. It would not be possible to bond a tiny die in a huge package, because the bond wires would get to long. But KnC is NOT doing a wire bond design like e.g. Avalon/ASICMiner or Bitfury.

Thx for pointing out the flip chip/wire-bond difference. How optimistic are you about the die size? Is that fairly accurate or "fingers on screen" accurate?

[HyperMega]

...

I hope this is no information you got from KnC because it can't be correct.

Some semiconductor industry facts:
1) at the moment there is no 28nm fab at all in People's Rep. of China (they are of course working at building ten )
2) TSMC stands for "Taiwan Semiconductor Manufacturing Company", all there fabs including 28nm are in Taiwan
3) The only 28nm GLOBALFOUNDRIES fab (former AMD production side) is fab1 located in Dresden, Germany

Sorry, yes, my bad about GF, although Taiwan is a long disputed province of the People's Republic of China.

I clearly remember someone posting a wild guess about what will be the KnC fab. it costs me quite a few to find it but eventuallly I got it:

https://bitcointalk.org/index.php?topic=232852.msg2584946#msg2584946

it was buried into the 'orama openday report thread. it should be helpful hopefully

I think you dug up the packaging company, not the fab.

yep, you're probably right.

I don't know why but I've taken for granted that they would ASE Inc facility to produce the chip.

That's marketing: they're a "leader", "full featured", "turnkey solutions" and whatnot THEN you realize they do not actually fabricate the silicon.

I think they'll be using Altera (who's using TSMC) for the fab. They were working on a special deal for the Mars, using Altera FPGA, and Altera can turn their FPGA code (RTL? forgot the exact TLA) into an ASIC.

Please don't mind me, but all companies offering RTL2GDS (standard cell ASIC synthesis and place&route) or FPGA-hardcopy/structured ASIC implementations are in this case just service providers, no foundries with fabs.
 
There is only a handful "pure play" foundries offering advanced nodes (< 65nm) in principle open for every customer. There are only 2 currently offering 28nm their own fabs: TSMC and GLOBALFOUNDRIES.

All other 28nm (and below) players (like Intel, Samsung, IBM, STM) are so called IDMs, offering their production capacity to some interessting high volume customers from time to time too to get a better workload in their fabs.

[Bitcoinorama]

...

I hope this is no information you got from KnC because it can't be correct.

Some semiconductor industry facts:
1) at the moment there is no 28nm fab at all in People's Rep. of China (they are of course working at building ten )
2) TSMC stands for "Taiwan Semiconductor Manufacturing Company", all there fabs including 28nm are in Taiwan
3) The only 28nm GLOBALFOUNDRIES fab (former AMD production side) is fab1 located in Dresden, Germany

Sorry, yes, my bad about GF, although Taiwan is a long disputed province of the People's Republic of China.

I clearly remember someone posting a wild guess about what will be the KnC fab. it costs me quite a few to find it but eventuallly I got it:

https://bitcointalk.org/index.php?topic=232852.msg2584946#msg2584946

it was buried into the 'orama openday report thread. it should be helpful hopefully

I think you dug up the packaging company, not the fab.

yep, you're probably right.

I don't know why but I've taken for granted that they would ASE Inc facility to produce the chip.

That's marketing: they're a "leader", "full featured", "turnkey solutions" and whatnot THEN you realize they do not actually fabricate the silicon.

I think they'll be using Altera (who's using TSMC) for the fab. They were working on a special deal for the Mars, using Altera FPGA, and Altera can turn their FPGA code (RTL? forgot the exact TLA) into an ASIC.

Please don't mind me, but all companies offering RTL2GDS (standard cell ASIC synthesis and place&route) or FPGA-hardcopy/structured ASIC implementations are in this case just service providers, no foundries with fabs.
 
There is only a handful "pure play" foundries offering advanced nodes (< 65nm) in principle open for every customer. There are only 2 currently offering 28nm their own fabs: TSMC and GLOBALFOUNDRIES.

All other 28nm (and below) players (like Intel, Samsung, IBM, STM) are so called IDMs, offering their production capacity to some interessting high volume customers from time to time too to get a better workload in their fabs.

Logistically it's probably easier to deal with someone in Europe, but this is a time play, so I guess whoever they have the most previous experience with. That said they mentioned they were courting both, so time and expense is the more crucial determinant, especially time...

[KS]

...

I hope this is no information you got from KnC because it can't be correct.

Some semiconductor industry facts:
1) at the moment there is no 28nm fab at all in People's Rep. of China (they are of course working at building ten )
2) TSMC stands for "Taiwan Semiconductor Manufacturing Company", all there fabs including 28nm are in Taiwan
3) The only 28nm GLOBALFOUNDRIES fab (former AMD production side) is fab1 located in Dresden, Germany

Sorry, yes, my bad about GF, although Taiwan is a long disputed province of the People's Republic of China.

I clearly remember someone posting a wild guess about what will be the KnC fab. it costs me quite a few to find it but eventuallly I got it:

https://bitcointalk.org/index.php?topic=232852.msg2584946#msg2584946

it was buried into the 'orama openday report thread. it should be helpful hopefully

I think you dug up the packaging company, not the fab.

yep, you're probably right.

I don't know why but I've taken for granted that they would ASE Inc facility to produce the chip.

That's marketing: they're a "leader", "full featured", "turnkey solutions" and whatnot THEN you realize they do not actually fabricate the silicon.

I think they'll be using Altera (who's using TSMC) for the fab. They were working on a special deal for the Mars, using Altera FPGA, and Altera can turn their FPGA code (RTL? forgot the exact TLA) into an ASIC.

Please don't mind me, but all companies offering RTL2GDS (standard cell ASIC synthesis and place&route) or FPGA-hardcopy/structured ASIC implementations are in this case just service providers, no foundries with fabs.
 
There is only a handful "pure play" foundries offering advanced nodes (< 65nm) in principle open for every customer. There are only 2 currently offering 28nm their own fabs: TSMC and GLOBALFOUNDRIES.

All other 28nm (and below) players (like Intel, Samsung, IBM, STM) are so called IDMs, offering their production capacity to some interessting high volume customers from time to time too to get a better workload in their fabs.

Yeah, I did not mean Altera is a fab. They were probably just trying to decide between Altera and eASIC (unless you know of a 3rd company they have a contract with for 28nm?).

[sickpig]

...
Yeah, I did not mean Altera is a fab. They were probably just trying to decide between Altera and eASIC (unless you know of a 3rd company they have a contract with for 28nm?).

...
There is only a handful "pure play" foundries offering advanced nodes (< 65nm) in principle open for every customer. There are only 2 currently offering 28nm their own fabs: TSMC and GLOBALFOUNDRIES.

All other 28nm (and below) players (like Intel, Samsung, IBM, STM) are so called IDMs, offering their production capacity to some interessting high volume customers from time to time too to get a better workload in their fabs.

sorry for bothering but let me try to understand, do you mean that Altera usual partner is TSMC while eASIC's is GF ?

[HyperMega]

I doubt that KnC or OrSOC is seen as a big customer for this project, because they probably will not order more than 50 wafers in the first year (which would be already about 3 PH).

3 PetaHash/s ? That's a very interesting number. Could you expand the calculation for us? If I am seeing correctly that would be 10 times the present total network hashing power.

Is 50 wafers some sort of bulk discount number or some sort of standard order? Maybe there;s some minimum amount of wafers?

Thanks!

KnC ASIC will have about 100 GH/s realised with 192 engine IPs (see KnC R&D news from 7/19/2013).

I assume that an engine IP is equivalent to a pipelined hash core. To realise 100 GH/s they must run at a little bit more than 500 MHz, what is feasible in 28nm.

Based on technology scaling (2x more logic on same area form technology node to next technology node) we get based on BFL hash core size (estimated based on BFL die including 16 cores removing spare area and pad frame overhead) from 65(55)nm -> 45(40)nm -> 32(28)nm an estimated area per hash core of 0.6 mm2 in 28nm.

This results in an overall KnC die area of about 115 mm2 (0.6mm2 x 192).
Adding some area for supporting logic, I would say max 120 mm2 would be a good target.

An 28nm 300mm wafer has an area of about 70000 mm2. So we get 583 dies per wafer (assuming 100% yield, not realistic I know, but you can scale it yourself to your yield assumptions).

For 50 wafer:

583 dies/wafer -> 58.3 TH/wafer
50 wafer -> 2915 TH

Minimum ordering at foundries is normally one lot (25 wafer). Maybe also half lots are possible. But keep in mind, additional wafers costs nothing compared to the initial mask costs.

+3000TH. That sounds very scary for anyone wanting to meet ROI. Anyway...

Would they need a 55mmx55mm package for a 11mmx11mm chip??

They choose the package size to handle thermal and power requirements (ir-drop and so on). It's a flip-chip design with a custom package substrat (to be designed to fit to KnC die). In principle there is no problem to put a 11x11mm2 die flip-chip on a 55x55mm2 package substrat.

Wire-bond would be a different story. It would not be possible to bond a tiny die in a huge package, because the bond wires would get to long. But KnC is NOT doing a wire bond design like e.g. Avalon/ASICMiner or Bitfury.

Thx for pointing out the flip chip/wire-bond difference. How optimistic are you about the die size? Is that fairly accurate or "fingers on screen" accurate?

120 mm2 in 28nm is really really huge, but can be produced. Approximately 4 dies per reticle. A nightmare were for sure the toplevel layout implementation and power sign-off.

They will have for sure yield issues, but if they integrated suitable redundancy features it should be handleable.

With respect to design complexity the related BIST (built in self test) and redundancy logic, will be as complex as the pure miner logic . I hope they verified that right, because this was probably not part of their FPGA prototype.

EDITED: To your original question. I'm pretty sure, that if the KNC die is bigger than 120 mm2 they did not a good layout implementation job. This is the minimum target that they must reach to take full advantage of 28nm (better smaller).

[HyperMega]

...
Yeah, I did not mean Altera is a fab. They were probably just trying to decide between Altera and eASIC (unless you know of a 3rd company they have a contract with for 28nm?).

...
There is only a handful "pure play" foundries offering advanced nodes (< 65nm) in principle open for every customer. There are only 2 currently offering 28nm their own fabs: TSMC and GLOBALFOUNDRIES.

All other 28nm (and below) players (like Intel, Samsung, IBM, STM) are so called IDMs, offering their production capacity to some interessting high volume customers from time to time too to get a better workload in their fabs.

sorry for bothering but let me try to understand, do you mean that Altera usual partner is TSMC while eASIC's is GF ?

Correct.

[KS]

I doubt that KnC or OrSOC is seen as a big customer for this project, because they probably will not order more than 50 wafers in the first year (which would be already about 3 PH).

3 PetaHash/s ? That's a very interesting number. Could you expand the calculation for us? If I am seeing correctly that would be 10 times the present total network hashing power.

Is 50 wafers some sort of bulk discount number or some sort of standard order? Maybe there;s some minimum amount of wafers?

Thanks!

KnC ASIC will have about 100 GH/s realised with 192 engine IPs (see KnC R&D news from 7/19/2013).

I assume that an engine IP is equivalent to a pipelined hash core. To realise 100 GH/s they must run at a little bit more than 500 MHz, what is feasible in 28nm.

Based on technology scaling (2x more logic on same area form technology node to next technology node) we get based on BFL hash core size (estimated based on BFL die including 16 cores removing spare area and pad frame overhead) from 65(55)nm -> 45(40)nm -> 32(28)nm an estimated area per hash core of 0.6 mm2 in 28nm.

This results in an overall KnC die area of about 115 mm2 (0.6mm2 x 192).
Adding some area for supporting logic, I would say max 120 mm2 would be a good target.

An 28nm 300mm wafer has an area of about 70000 mm2. So we get 583 dies per wafer (assuming 100% yield, not realistic I know, but you can scale it yourself to your yield assumptions).

For 50 wafer:

583 dies/wafer -> 58.3 TH/wafer
50 wafer -> 2915 TH

Minimum ordering at foundries is normally one lot (25 wafer). Maybe also half lots are possible. But keep in mind, additional wafers costs nothing compared to the initial mask costs.

+3000TH. That sounds very scary for anyone wanting to meet ROI. Anyway...

Would they need a 55mmx55mm package for a 11mmx11mm chip??

They choose the package size to handle thermal and power requirements (ir-drop and so on). It's a flip-chip design with a custom package substrat (to be designed to fit to KnC die). In principle there is no problem to put a 11x11mm2 die flip-chip on a 55x55mm2 package substrat.

Wire-bond would be a different story. It would not be possible to bond a tiny die in a huge package, because the bond wires would get to long. But KnC is NOT doing a wire bond design like e.g. Avalon/ASICMiner or Bitfury.

Thx for pointing out the flip chip/wire-bond difference. How optimistic are you about the die size? Is that fairly accurate or "fingers on screen" accurate?

120 mm2 in 28nm is really really huge, but can be produced. Approximately 4 dies per reticle. A nightmare were for sure the toplevel layout implementation and power sign-off.

They will have for sure yield issues, but if they integrated suitable redundancy features it should be handleable.

With respect to design complexity the related BIST (built and self test) and redundancy logic, will be as complex as the pure miner logic . I hope they verified that right, because this was probably not part of their FPGA prototype.

EDITED: To your original question. I'm pretty sure, that if the KNC die is bigger than 120 mm2 they did not a good layout implementation job. This is the minimum target that they must reach to take full advantage of 28nm (better smaller).

Aren't they already in problem land wrt the heat issue for such a small die? Won't having it smaller be worse actually? (wrt heat dissipation)

[HyperMega]

I doubt that KnC or OrSOC is seen as a big customer for this project, because they probably will not order more than 50 wafers in the first year (which would be already about 3 PH).

3 PetaHash/s ? That's a very interesting number. Could you expand the calculation for us? If I am seeing correctly that would be 10 times the present total network hashing power.

Is 50 wafers some sort of bulk discount number or some sort of standard order? Maybe there;s some minimum amount of wafers?

Thanks!

KnC ASIC will have about 100 GH/s realised with 192 engine IPs (see KnC R&D news from 7/19/2013).

I assume that an engine IP is equivalent to a pipelined hash core. To realise 100 GH/s they must run at a little bit more than 500 MHz, what is feasible in 28nm.

Based on technology scaling (2x more logic on same area form technology node to next technology node) we get based on BFL hash core size (estimated based on BFL die including 16 cores removing spare area and pad frame overhead) from 65(55)nm -> 45(40)nm -> 32(28)nm an estimated area per hash core of 0.6 mm2 in 28nm.

This results in an overall KnC die area of about 115 mm2 (0.6mm2 x 192).
Adding some area for supporting logic, I would say max 120 mm2 would be a good target.

An 28nm 300mm wafer has an area of about 70000 mm2. So we get 583 dies per wafer (assuming 100% yield, not realistic I know, but you can scale it yourself to your yield assumptions).

For 50 wafer:

583 dies/wafer -> 58.3 TH/wafer
50 wafer -> 2915 TH

Minimum ordering at foundries is normally one lot (25 wafer). Maybe also half lots are possible. But keep in mind, additional wafers costs nothing compared to the initial mask costs.

+3000TH. That sounds very scary for anyone wanting to meet ROI. Anyway...

Would they need a 55mmx55mm package for a 11mmx11mm chip??

They choose the package size to handle thermal and power requirements (ir-drop and so on). It's a flip-chip design with a custom package substrat (to be designed to fit to KnC die). In principle there is no problem to put a 11x11mm2 die flip-chip on a 55x55mm2 package substrat.

Wire-bond would be a different story. It would not be possible to bond a tiny die in a huge package, because the bond wires would get to long. But KnC is NOT doing a wire bond design like e.g. Avalon/ASICMiner or Bitfury.

Thx for pointing out the flip chip/wire-bond difference. How optimistic are you about the die size? Is that fairly accurate or "fingers on screen" accurate?

120 mm2 in 28nm is really really huge, but can be produced. Approximately 4 dies per reticle. A nightmare were for sure the toplevel layout implementation and power sign-off.

They will have for sure yield issues, but if they integrated suitable redundancy features it should be handleable.

With respect to design complexity the related BIST (built and self test) and redundancy logic, will be as complex as the pure miner logic . I hope they verified that right, because this was probably not part of their FPGA prototype.

EDITED: To your original question. I'm pretty sure, that if the KNC die is bigger than 120 mm2 they did not a good layout implementation job. This is the minimum target that they must reach to take full advantage of 28nm (better smaller).

Aren't they already in problem land wrt the heat issue for such a small die? Won't having it smaller be worse actually? (wrt heat dissipation)

In principle you are right, but why waste all this expensive 28nm area? If you want to take full advantage of the technology scaling, you have to get as small as possible to be cost competitive. Otherwise you could also go for a 40nm implementation which would have half of the NRE costs of 28nm.

Forgot to mention, the nice effect is that power consumption scales with area, because you will have on-die shorter wires to connect the logic cells, which means less capacitance load in case of switching.

[Minor Miner]

$800k for a 28nm full-mask set? This is an amazing offer, at which foundry will I get it that cheap?

Get an itemized quote, do you think you pay the full $2MM up front?  If you do, let me know I will gladly negotiate for you next time for 10%.    that is the payment you will be making PRIOR to your mask.   There are other payments, but you seem to have an inkling of what you are talking about so you know that, don't you?
That I do not believe KnC is producing a fully designed asic should be obvious by now.

That only works if the foundry is convinced that you are worthy of credit. Normally this is not the case for start-ups and SMEs in this price category. For them it is cash in advance or no tape-out. Yes, I know what I'm talking about, it's hard to deal directly with companies like GF or TSMC if your are only a small customer.

I doubt that KnC or OrSOC is seen as a big customer for this project, because they probably will not order more than 50 wafers in the first year (which would be already about 3 PH). 1000 wafers a year would be a big customer. Why should a foundry take any risk for a bitcoin mining ASIC?
So I think they most likely have to pay the complete $1.5M to $2M in advance of the tape-out. And because they said tape-out done "some time ago", they probably paid it also some time ago.

From the commercial point of view I see no reason why KnC should not be able to produce a fully designed 28nm ASIC. They collected enough money by pre-orders to pay the complete 3rd party NREs in advance. But it should be clear, that if they are on track as they claimed, a great deal of the pre-order money isn't in their hands any more.

You are very close to the same point I am making but design is probably 300-400k of the foundry's quote and they say they did all the design themselves (another reason to be skeptical given their foundry did not make them join a shuttle run).    1.  Why go to 28nm as no one will give you space unless they see a long term relationship and believe in your market?  We believe in this market, I am not sure a salesman would want to pitch it with enthusiasm to his boss though.   2.  This company just started doing this 3 months ago.   You really think in three months they are taping out a 28nm?   Add to this, they just raised the money a month ago.  3.  They do background checks before you even get anywhere near this point and 3 months ago, KnC was an idea to "make lots of money".   It does not make sense they have taped at 28nm.
4.   My guess, which people have posted that it is not true, is they are going with eAsic.