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Author Topic: Swedish ASIC miner company kncminer.com  (Read 3046303 times)
2112
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August 16, 2013, 06:04:55 PM
Last edit: August 16, 2013, 06:42:46 PM by 2112
 #6181

That's insane. If something is wrong they will not know if it's a problem with the ASIC or not. They can't complain to the ASIC vendor either and they will not have a clue in terms of yield. Did they do this to save time so they would not have to learn and run ATPG tools?
What are you talking about? What would be an example defect that would completely disable a chip with 4 non-overlapping/non-intersecting clock trees?

Please go back to your ATPG tools and obtain the probabilities. Then report back here and re-state who is insane.

Also: use your best design-for-test methodology to create a test pattern. Then compare the coverage with just any 10 random 80-byte test patterns. Then come back here and report who is a CAD-monkey in this thread.

Edit: I'll add this explanation for the readers unfamiliar with logic design. SHA-256 is essentially self testing: there's no internal state that is either not controllable or not observable. Same with all the interconnects. It is possible to construct a very-low-probability faults that will go undetected in the unrolled design. But their probability is way lower than the acceptable hardware error nonce rate in a Bitcoin miner (single percentage points).

For the readers unfamiliar with logic design but capable of compiling a program: take an example working SHA-256 code and make a single character change somewhere in the code, e.g. '0' to '1'. Then recompile and compare the results of hashing a test file with 1000 randomly choosen 80-byte strings. You'll immediately understand what it means "high toggle rate" and "self-testing logic".

This self-testing property has been discussed on this forum multiple times, in English and in other languages.

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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August 16, 2013, 06:10:00 PM
 #6182


Sadly the biggest worry on shipment would be customs if anyone has been following the Avalon chip hostage crisis...

I would be driving to the customs office pronto on first hint of any delays

Feels so good to be in the EU right now and so close to Sweden. I would expect to have a 1 day delivery straight to my door Smiley

Well that's exactly what I just had happen a few weeks ago. Unless the size makes a big difference. I lost a gold card and reader for Entropia and it took a day to replace by courier from Sweden. Smiley

I'm never going to believe that all rigs will be hashing with an hour of completion however..especially the first ones. How many a day are they producing? Got to be 100 or more which will need to be transported (and packed and unpacked for that), be wired up and have miner and pool details sorted (accurately). Granted they won't just have one guy doing it ...but I doubt they have Ooompahloompahs either.

"Here you go boys, the 1st batch of 100 is ready to set up, see you in an hour when the next batch is ready" lol

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Phoenix1969
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August 16, 2013, 06:31:40 PM
 #6183


What are those mysterious dark shadows  inside the case on the right?...
Is that possibly a pcb I see hiding in there?

Just to "Stirr the Pot" a bit...


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August 16, 2013, 06:33:53 PM
 #6184


What are those mysterious dark shadows  inside the case on the right?...
Is that possibly a pcb I see hiding in there?

Just to "Stirr the Pot" a bit...

No that's just scratched metal surface.  The case on the right is assembled.

Make my day! Say thanks if you found me helpful Smiley BTC Address --->
1487ThaKjezGA6SiE8fvGcxbgJJu6XWtZp
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August 16, 2013, 06:33:58 PM
 #6185


What are those mysterious dark shadows  inside the case on the right?...
Is that possibly a pcb I see hiding in there?

Just to "Stirr the Pot" a bit...

lol, get your eyes checked old man! hahahaha

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August 16, 2013, 06:35:34 PM
 #6186

Hehehehe, Hook, line, & sinker  Tongue


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August 16, 2013, 06:42:30 PM
 #6187

That's insane. If something is wrong they will not know if it's a problem with the ASIC or not. They can't complain to the ASIC vendor either and they will not have a clue in terms of yield. Did they do this to save time so they would not have to learn and run ATPG tools?
What are you talking about? What would be an example defect that would completely disable a chip with 4 non-overlapping/non-intersecting clock trees?

A stuck at fault in the control logic or in the IO interface.
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August 16, 2013, 06:46:32 PM
 #6188


A stuck at fault in the control logic or in the IO interface.

A single "stuck at" fault that would disable a whole chip that is completely 4-way redundand?

You are incompetent.

The above is the proof.

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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August 16, 2013, 07:24:38 PM
 #6189


A stuck at fault in the control logic or in the IO interface.

A single "stuck at" fault that would disable a whole chip that is completely 4-way redundand?

You are incompetent.

The above is the proof.


There is probably some logic selecting which core(s) to use and some common IO interface. A single fault here could render the device useless depending upon the design. Give me the netlist and I'll show you where the possible faults are.
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August 16, 2013, 07:31:11 PM
 #6190


A stuck at fault in the control logic or in the IO interface.

A single "stuck at" fault that would disable a whole chip that is completely 4-way redundand?

You are incompetent.

The above is the proof.

Mind making a thread comparing KnC, HF, BF, Avalon, Labcoin, BTCGarden, Cointerra, xCrowd etc?
To have your comments somewhere concentrated, you seem very knowledgable..
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August 16, 2013, 07:39:38 PM
 #6191

With regards to tracking an idea comes to mind.  I was planning on putting a gprs modem in the router for the racks of machines to act as a backup internet connection.  $40 USD for prepaid sim card that charges $2 USD a day when active and $60 for the modem.  But the modem also has GPS.  One could easily have it not only fail over to the GPRS but also beacon the GPS location.

Again, I'm not worried about theft from a data center.
That's a good idea. Are you suggesting something like this? http://www.ebay.com/itm/Sprint-Compass-High-Speed-597U-597-USB-3G-GPS-Mobile-Modem-AirCard-FAST-SHIPPING-/221217870969
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August 16, 2013, 07:40:05 PM
 #6192


A stuck at fault in the control logic or in the IO interface.

A single "stuck at" fault that would disable a whole chip that is completely 4-way redundand?

You are incompetent.

The above is the proof.


Hey hey, no reason to get rude here!

You should have a look at their R&D slides again. Their die contains of 4 fully self contained "quads" , 48 unrolled hash cores each. Each core must run at about 520 MHz to realize in sum 100 GH/s.

The complete die will have a size of at least 100 mm2. It's 28nm, not 130nm, there will be yield issue for sure for such a huge die. Most likely this will be stuck-at faults in some of the hash cores (which could be easily detected by a BIST or ATPG tests). If these permanent production failures cause permanent non-working hash cores, the remaining cores have to run at a higher frequency to still have 100 GH/s per chip. Because this is what they have to sell.

If 3 of the 4 quads have stuck-at faults in the interface logic, it would be impossible to realize 100 GH/s with the remaining one quad, because in this case it has to run at about 2 GHz.
Of course one could try to implement each quad to be able to run at 2 GHz speed too, but this kind of "margin" will probably double the area you need for one hash core. I doubt that they have added enough margin to compensate even one complete non-working quad to still have 100 GH/s.

The skipped traditional production tests will force them to realize all this compensation on-line in the final miner by firmware procedures. This it not impossible, but the development of that feature is not that straight forward, because they currently do not know how a higher number of chips will behave in terms of yield and how these procedures have to look in detail.
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August 16, 2013, 08:05:23 PM
Last edit: August 16, 2013, 08:19:15 PM by 2112
 #6193

Mind making a thread comparing KnC, HF, BF, Avalon, Labcoin, BTCGarden, Cointerra, xCrowd etc?
To have your comments somewhere concentrated, you seem very knowledgable..
Thanks for the compliment.

Unfortunately, there isn't sufficient technical information available to do a meaningful engineering comparison.

The only meaningfull contribution I can make is to shot down impostors who use the correct English grammar and technical vocabulary, but have no actual understanding of the underlying technology, e.g. kingcoin.

KnC had published some general technical information couple of days ago: https://www.kncminer.com/news/news-25 . I can't access it now, but it clearly showed that the package has over 1000 pins and that the single chip is comprised of 4 disconnected sub-regions, with absolutely every feature symmetrically quadrupled. Each of the quad in turn contains 24 identical copies of the hashing engine. When you can access it take a look at the floorplan and make a guess: what would be the probability of randomly distributed defects to hit every of the 4 copies of "control logic". What would be a minimum required size of a "single defect" that would kill all 4 regions? Even if you aren't rocket surgeon or brain scientist your honest guess will be better than the kingcoin's assesment of "insanity" of the KnC designers.

Here is a fragment of the Wikipedia definition of a code monkey: a derogatory term for an unskilled programmer who is only able to perform trivial or repetitive computer programming tasks or a reference to a job that treats even experienced computer programmers in a way that trivializes their problem solving abilities.

CAD-monkey is the hardware equivalent of the above term, because most of the hardware engineer's work involves not writing/editing "code", but operating some "CAD" or "EDA" tool/program.

Edit: CAD-monkey is derogatory if the person claims to be a qualified engineer. It may be a very friendly, or self-depreciating, reference to a skilled/trained salesperson of the CAD tools. Working in sales could really require skill and patience at repeatedly explaining/presenting "how to import a netlist" or "how to export to an ATPG (Automated Test-Pattern Generation) tool".

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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August 16, 2013, 08:08:51 PM
 #6194

Seems I have to stalk your profile for latest posts then Wink
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August 16, 2013, 08:18:34 PM
 #6195


What are those mysterious dark shadows  inside the case on the right?...
Is that possibly a pcb I see hiding in there?

Just to "Stirr the Pot" a bit...

lol, get your eyes checked old man! hahahaha



I just realized the front of the KNC box looks kind of like a goofy robot face - fans as eyes and the power/io slot as a mouth.

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August 16, 2013, 08:42:53 PM
Last edit: August 16, 2013, 08:53:35 PM by 2112
 #6196

Most likely this will be stuck-at faults in some of the hash cores (which could be easily detected by a BIST or ATPG tests).
Go ahead, make my day. Take the challenge. Run your ATPG toolset and come up with a "stuck-at" fault vector that will not be detected by the HW-error code in the cgminer. What are you trying to show?

The "yield issue" for "a large 28nm" chip is a bullshit concern from people who don't understand that one can't take data from chips implementing single, hyper-complex circuit like CPU or GPU and apply it to a repetitive chip that doesn't even have a JTAG chain. I discussed it already a couple of days ago.

Edit: It was in this very thread: https://bitcointalk.org/index.php?topic=170332.msg2723643#msg2723643 . End of edit.

Rest your post about what is the real available "margin upon margins" is definitely a valid concern, but it is too early to really quantify that. Bitfury disclosed how he had dealt with it: hashing cores are 55nm but the unique control logic is drawn much wider (150nm?), all using the same 65nm nominal process. I'm going to give KnC designers benefit of the doubt and assume that they were skilled enough to use similar design methodology in their 28nm-nominal design.

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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August 16, 2013, 09:13:34 PM
 #6197


What are those mysterious dark shadows  inside the case on the right?...
Is that possibly a pcb I see hiding in there?

Just to "Stirr the Pot" a bit...

lol, get your eyes checked old man! hahahaha



I just realized the front of the KNC box looks kind of like a goofy robot face - fans as eyes and the power/io slot as a mouth.
Well spotted. Bender is a bitcoin miner! VVVVVVVVVVVVV
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August 16, 2013, 09:19:03 PM
 #6198

What would be a minimum required size of a "single defect" that would kill all 4 regions?

The top part of the figure has some control logic connecting the FPGA to the hashing cores to exchange data/midstace/nonce or whatever. Without access to the netlist it's not possible to analyze the probability of a single point of failure. I've seen cases of redundant logic which turned out to share some gates. Test tools can analyse your netlist and detect such potential failures. There are four different clock domains so there might be some synchronization logic in there, unless there are four separate channels with separate clock outputs, or an embedded clock. Again without access to the design one can only speculate. I can't see why KnC chose to skip this common design practice, even though a hasher itself is similar in nature to many BIST implementations even tough the signature checker will be on the device itself so I can be checked on the tester. It would have been better to do the testing on the chip tester and not struggle to figure out if the cause  of the reduced hashing capacity is due to the ASIC chip itself or some other part of the miner. And you don't need to kill all four regions to reduce the capacity of the miner. If the yield is low it will be hard to prove to the vendor that this is due to the ASIC's and not something else.
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August 16, 2013, 09:23:57 PM
 #6199


What are those mysterious dark shadows  inside the case on the right?...
Is that possibly a pcb I see hiding in there?

Just to "Stirr the Pot" a bit...

lol, get your eyes checked old man! hahahaha



I just realized the front of the KNC box looks kind of like a goofy robot face - fans as eyes and the power/io slot as a mouth.
Well spotted. Bender is a bitcoin miner! VVVVVVVVVVVVV


I'm totally calling my new miner bender Smiley

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August 16, 2013, 09:41:53 PM
 #6200

£120 (Good quality PSU for example Corsair HX850)

That won't be enough. For Jupiter you would need to have at least HX1050 PSU (or better) to be on the safe side. ($240, £155)

Also, you forgot import taxes. Wink At least for Norway, that's 25% of the unit cost. Don't know about Sweden->UK

Everyone please ignore this post. If you were to buy a HX1050 for a 1000W Jupiter, you would essentially be running at near 95% load.
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