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Author Topic: Swedish ASIC miner company kncminer.com  (Read 3049421 times)
Vycid
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August 18, 2013, 06:55:51 AM
 #6301

Hi Apple, Hi Microsoft can we hold hands and kiss? Hey get Linux in here we love eachother so much.

Huh, you mean like this?


People competing with eachother are friendly all the time.

those are smiles of hatred lol

Yeah, the body language is off the charts. Look at how they're leaning away from each other, and the smiles look sorta forced (pulled down at the bottom, too toothy).

Jobs has got the "ha ha I'm going to stab you in your sleep" look going on.

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August 18, 2013, 08:11:53 AM
 #6302

Jobs has got the "ha ha I'm going to stab you in your sleep" look going on.

Heh, maybe so.  But the point is competitors are photographed together and at least pretending to get along. Josh talked a lot of smack about KnC, I doubt they actually like him.

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August 18, 2013, 08:31:26 AM
 #6303

Hi Apple, Hi Microsoft can we hold hands and kiss? Hey get Linux in here we love eachother so much.

Huh, you mean like this?


People competing with eachother are friendly all the time.

those are smiles of hatred lol

Yup ...i actually saw that interview....Jobs more or less screwed gates ....it was funny ...
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August 18, 2013, 08:37:34 AM
 #6304

Yup ...i actually saw that interview....Jobs more or less screwed gates ....it was funny ...

Yeah... well who's laughing now Tongue

(oh, also: http://www.youtube.com/watch?v=njos57IJf-0)

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August 18, 2013, 09:03:54 AM
 #6305

Yup ...i actually saw that interview....Jobs more or less screwed gates ....it was funny ...

Yeah... well who's laughing now Tongue

(oh, also: http://www.youtube.com/watch?v=njos57IJf-0)

I think still jobs is laughing Smiley as what he achieved, gates will not be able to achieve in his life time...current apple market cap 456 billion , Microsoft 264 billion....Microsoft neither have that finesse nor vision that Apple had......    

In any case lets start another thread for this as this is suppose to be a KNC thread ..lol
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August 18, 2013, 09:10:51 AM
 #6306

And, it would be much simpler to test the PCB then to test the chip.  The chip itself has a 1mm ball pitch and thousands of balls.  Aligning it might take time, and it will generate a lot of heat in the tester (I guess you could test one engine at a time, though)
(although I'm sure the low chip yeild would suck)

You do realise that the very same foundries making KNC's chips make other chips too? This is not rocket science (actually its far more high tech than that, but...), the industry is what 50 years old now? These problems were solved years ago (if BGA was untestable, it would never have made mainstream).

Just stop it please. The problem does not exist, people are doing this every day.

What people are doing every day is this: The chips are tested on the wafer. Bad chips are marked with dye. If enough chips are bad even the whole wafer is thrown away to save time/money on further processing. Bad chips are not packaged in order not to waste time/money on the package/packaging. The good chips are packaged. A final test is run on the packaged chip. In the old days wire bonding could fail. Today the majority uses flip chip which is not that sensitive as the thin bonding wires, but packaging could change the characteristic of the device. Only good chips are shipped to the customer. The fab has advanced and expensive fixtures to attach to both the die and the BGA package and run the given test vectors. This is standard procedure in the semiconductor industry.

It's not common to skip this chip level test (like it's claimed that KnC does) and let the customer or some 3rd party test the chip using some expensive fixture or run tests on actual PCB for the purpose of testing the chip (of course you run a lot of test on the PCB to detect bad solder joints and other assembly problems).

By not creating test vectors and skipping chip level testing you're potentially paying for a wafer and packages for chips which might even have been thrown away under normal circumstances. Not only that, you are also throwing away PCB's and other components unless you spend even more money on unmounting/reballing the good devices on the PCB.
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August 18, 2013, 09:16:39 AM
 #6307

By not creating test vectors and skipping chip level testing you're potentially paying for a wafer and packages for chips which might even have been thrown away under normal circumstances. Not only that, you are also throwing away PCB's and other components unless you spend even more money on unmounting/reballing the good devices on the PCB.

Yes, but do the math: You have a bitcoin hashing chip that can do 100Gh/s.  Today that's about $110 a day. $780 a week. Even if you had a 50% yeild, why would it matter if you had to throw away a PCB for every single working chip if it meant getting your chips a week earlier?

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August 18, 2013, 09:20:54 AM
 #6308

Shame you didn't ask how long to get it hashing if hosted. That's got to take some time, they arent hosted at the factory and need setting up when they get to the hosting facility. Hard to compare without knowing that.

I asked knc support and they said it will start hashing 24 hours max after it left the factory.
Maybe they are not hosted in sweden?
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August 18, 2013, 09:37:06 AM
 #6309

It's not common to skip this chip level test (like it's claimed that KnC does) and let the customer or some 3rd party test the chip using some expensive fixture or run tests on actual PCB for the purpose of testing the chip (of course you run a lot of test on the PCB to detect bad solder joints and other assembly problems).

Give it a rest. You're blowing this up completely out of proportion from a throwaway remark made at an open day months ago. As I said earlier, testing is what the semiconductor industry does.  Yes, this can be skipped for the very first samples off the production line, but its not the norm for production parts and won't be the norm with KNC either. Not sure what your point about customer or 3rd party testing is about ... chip packaging and final test is subcontracted, the test equipment is already there. You may need a custom socket/interface card built, but there are also standard fixtures for all the common packages, which will be perfectly adequate for the majority of devices.

1Jest66T6Jw1gSVpvYpYLXR6qgnch6QYU1 NumberOfTheBeast ... go on, give it a try Grin
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August 18, 2013, 10:03:05 AM
 #6310



By not creating test vectors and skipping chip level testing you're potentially paying for a wafer and packages for chips which might even have been thrown away under normal circumstances. Not only that, you are also throwing away PCB's and other components unless you spend even more money on unmounting/reballing the good devices on the PCB.

Yes, but do the math: You have a bitcoin hashing chip that can do 100Gh/s.  Today that's about $110 a day. $780 a week. Even if you had a 50% yeild, why would it matter if you had to throw away a PCB for every single working chip if it meant getting your chips a week earlier?

Chip level testing takes seconds (in some cases even less), not weeks. At 50% yield the fab would have been concerned and started investigation and tuning their process and tooling. Without any vectors they will not know and just continue to ship fully packaged defective chips to KnC at full price. But hopefully the problem would be detected by some other fab customer. But it might be that they don't care about throwing away money and are happy with whatever they are making.
kingcoin
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August 18, 2013, 10:17:54 AM
 #6311

It's not common to skip this chip level test (like it's claimed that KnC does) and let the customer or some 3rd party test the chip using some expensive fixture or run tests on actual PCB for the purpose of testing the chip (of course you run a lot of test on the PCB to detect bad solder joints and other assembly problems).

Give it a rest. You're blowing this up completely out of proportion from a throwaway remark made at an open day months ago. As I said earlier, testing is what the semiconductor industry does.  Yes, this can be skipped for the very first samples off the production line, but its not the norm for production parts and won't be the norm with KNC either. Not sure what your point about customer or 3rd party testing is about ... chip packaging and final test is subcontracted, the test equipment is already there. You may need a custom socket/interface card built, but there are also standard fixtures for all the common packages, which will be perfectly adequate for the majority of devices.

That's what I've been saying the whole time. Chips are tested in the fab during production using supplied test vectors. I've described the procedure above.  The standard procedure is also to include scan insertion and generate test vectors for the tester.

But now you are providing some new information: That KnC will do testing when they scale up the production? This contradict with information given earlier.

But I don't understand why they would want to skip testing on this in the first batch? (unless they just want devices for a photograph)

When they assemble their first set of miners and it does not work they will not know if it's a problem with the fabrication of the particular chip and will have to spend more time debugging trying to figure out where the problem is (device production, functional errors, software problems, power issues, FPGA logic, etc). If the device passed the chip level test you have one less unknown factor.



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August 18, 2013, 10:35:55 AM
 #6312

But I don't understand why they would want to skip testing on this in the first batch? (unless they just want devices for a photograph)

What do you mean "unless they just want devices for a photograph"?  You said testing only takes seconds, so how would it make a difference in terms of their being able to photograph them?

As far as the PCB is concerned, I don't even understand why you care. If a PCB costs $20 per module then it is literally like 1% of the cost. a 50% yeild would only increase costs by 1%.   A 91% yield would only increase costs by 0.1%.   The PCB is essentially just more packaging.

It's also possible they meant testing before packaging, or something like that.

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August 18, 2013, 10:49:54 AM
 #6313

But I don't understand why they would want to skip testing on this in the first batch? (unless they just want devices for a photograph)

What do you mean "unless they just want devices for a photograph"?  You said testing only takes seconds, so how would it make a difference in terms of their being able to photograph them?

I should have put a smiley there. Since they might be defective and only suitable for a photo.


As far as the PCB is concerned, I don't even understand why you care. If a PCB costs $20 per module then it is literally like 1% of the cost. a 50% yeild would only increase costs by 1%.   A 91% yield would only increase costs by 0.1%.   The PCB is essentially just more packaging.

It's also possible they meant testing before packaging, or something like that.

In the case of a miner the wasted PCB is marginal, but packaged defective chips would be more of a concern as well as the time it takes to produce the defective board. However, the redundancy might give them the revenue they want even if they are wasting money on faulty devices.

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August 18, 2013, 11:05:33 AM
 #6314

In the case of a miner the wasted PCB is marginal, but packaged defective chips would be more of a concern as well as the time it takes to produce the defective board. However, the redundancy might give them the revenue they want even if they are wasting money on faulty devices.

Keep in mind the vast majority of their costs are NRE costs, not the cost of the physical chips once produced.  A low yeild won't be a problem so long as they have enough to ship to their first customers.

Also, if the testing actually doesn't add delays they may still have it done. They don't need to do anything special in the chip design in order to test it if they have test sockets for it.  All they have to do is feed it some work and see if the hashes come out right. That's it.

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August 18, 2013, 02:40:31 PM
 #6315

In the case of a miner the wasted PCB is marginal, but packaged defective chips would be more of a concern as well as the time it takes to produce the defective board. However, the redundancy might give them the revenue they want even if they are wasting money on faulty devices.

Keep in mind the vast majority of their costs are NRE costs, not the cost of the physical chips once produced.  A low yeild won't be a problem so long as they have enough to ship to their first customers.


If the NRE is $1M and each chip is $200 (just guessing some numbers, add real numbers if you have them), and you get a couple thousand defective/reduced capacity devices this part is significant. But what is the reason for wasting this money by not providing test patterns and do testing in the fab?


Also, if the testing actually doesn't add delays they may still have it done. They don't need to do anything special in the chip design in order to test it if they have test sockets for it.  All they have to do is feed it some work and see if the hashes come out right. That's it.

That's my point and what I have argued the whole time. All they have to do is provide some  test vectors and run them on the chip tester. This is common practice and quick and pretty cheap (even though you pay for tester time). And then why not do it properly and do scan insertion and ATPG to cover the other parts which is pretty much standard procedure in the industry these days.

Is the word may in your sentence above an indication of that you think this is something they should do, or that you have heard somewhere that they might supply vectors and run test on the tester?
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August 18, 2013, 03:32:02 PM
 #6316

In the case of a miner the wasted PCB is marginal, but packaged defective chips would be more of a concern as well as the time it takes to produce the defective board. However, the redundancy might give them the revenue they want even if they are wasting money on faulty devices.

Keep in mind the vast majority of their costs are NRE costs, not the cost of the physical chips once produced.  A low yeild won't be a problem so long as they have enough to ship to their first customers.


If the NRE is $1M and each chip is $200 (just guessing some numbers, add real numbers if you have them), and you get a couple thousand defective/reduced capacity devices this part is significant. But what is the reason for wasting this money by not providing test patterns and do testing in the fab?


Also, if the testing actually doesn't add delays they may still have it done. They don't need to do anything special in the chip design in order to test it if they have test sockets for it.  All they have to do is feed it some work and see if the hashes come out right. That's it.

That's my point and what I have argued the whole time. All they have to do is provide some  test vectors and run them on the chip tester. This is common practice and quick and pretty cheap (even though you pay for tester time). And then why not do it properly and do scan insertion and ATPG to cover the other parts which is pretty much standard procedure in the industry these days.

Is the word may in your sentence above an indication of that you think this is something they should do, or that you have heard somewhere that they might supply vectors and run test on the tester?

I can't believe you are still talking about this. The whole reason they did this is time to market, and they said so several times Roll Eyes. Also, each system will be tested before being delivered to the customers. So, let's fill a couple more pages with guesses and useless banter.
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August 18, 2013, 04:05:00 PM
 #6317

That's my point and what I have argued the whole time. All they have to do is provide some  test vectors and run them on the chip tester. This is common practice and quick and pretty cheap (even though you pay for tester time). And then why not do it properly and do scan insertion and ATPG to cover the other parts which is pretty much standard procedure in the industry these days.
Well, as I thought: Office Space 2 will have a character named Milton the test collator who will constantly mumble "scan insertion", "ATPG", etc.

But here's the usefull information for the future. Yield in semiconductor industry is defined as a percentage of the dies that are "good" as opposed to "faulty". The decision between good/bad is binary only when the die contains a single circuit. It obviously applies to a CPU or a similar chip, because such a device contains a JTAG chain that is essentially threading through the every flip/flop on the chip. So if a defect breaks the JTAG chain the die becomes untestable and it isn't even worth to package it.

In the Bitcoin mining ASIC realm currently only ASICminer and Avalon have a single-engine dies. So those are the only two vendors that could conceivably use "yield" as a single percentage value.

Every other Bitcoin mining vendor have multi-engine dies: BFL has 16, bitfury has 756. To make such a chip "fail" you'll have to either kill their control logic or kill all the engines. In all other cases the chip is neither "good" nor "bad", but has some "inbetween" value that is neither 0% nor 100%.

KnC went one step ahead and their die consists of 48 engines and 4 completely independent "control logic" and "power supply" circuits. To make such a chip "fail" you'll have to e.g. kill all 4 contol logic cicuits or 3 control circuts and all 12 engines in the quadrant with the working control logic. If you kill only 11 engines in the "good" quadrant your resulting chip is 2.08% "good" and still has more performace than the 100% "good" Avalon chip.

Semiconductor manufacturing plants are prepared to deal with both types of "yield": the binary "pass/fail" type and the contiguous "quality curve" type. The problem is that the "quality curve" testing is complex and expensive, and therefore used only for the analog or mixed-signal devices. The "pass/fail" test is indeed cheap and quick and it is used for the vast majority of digital devices. But the Bitcoin mining ASIC is a completely atypical digital device therefore applying even a very cheap pass/fail test to it is economically pointless.

I've typed all this because I hope this will be usefull for the readers not well-versed in the electroinic engineering. I don't hope to sway Milton the tester's kingcoin's opinion, but I presume that the concern trolls will like him will keep poping up on this forum for many months, until the ways to characterize yield and test Bitcoin ASIC will become a common knowledge and will move from this subforum to the mining software subforum.

Please comment, critique, criticize or ridicule BIP 2112: https://bitcointalk.org/index.php?topic=54382.0
Long-term mining prognosis: https://bitcointalk.org/index.php?topic=91101.0
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August 18, 2013, 07:22:55 PM
 #6318

The whole reason they did this is time to market, and they said so several times Roll Eyes


They could be generating SVF files now while waiting for the masks to be produced. A second on the tester will not increase the time to market. The time it takes an experienced DFT engineer to run the test tools and formal checkers is in the area of hours. I would even do this for the single purpose of having a higher confidence in the chip which is mounted on the board for the initial bring-up. One valid time to marked argument could be that the process is so new that the tool and library support would have to be developed first.
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August 18, 2013, 07:27:17 PM
 #6319

I've typed all this because I hope this will be usefull for the readers not well-versed in the electroinic engineering. I don't hope to sway Milton the tester's kingcoin's opinion, but I presume that the concern trolls will like him will keep poping up on this forum for many months, until the ways to characterize yield and test Bitcoin ASIC will become a common knowledge and will move from this subforum to the mining software subforum.

Thank you. I love reading posts that inform!
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August 18, 2013, 07:30:05 PM
 #6320

Semiconductor manufacturing plants are prepared to deal with both types of "yield": the binary "pass/fail" type and the contiguous "quality curve" type. The problem is that the "quality curve" testing is complex and expensive, and therefore used only for the analog or mixed-signal devices. The "pass/fail" test is indeed cheap and quick and it is used for the vast majority of digital devices. But the Bitcoin mining ASIC is a completely atypical digital device therefore applying even a very cheap pass/fail test to it is economically pointless.

It's not very different from a multicore CPU or FPGA in this respect. AMD did sell N-1 core CPU's at a reduced price. FPGA's are one of the most complex devices in therms of transistor count and low yield is a likely problem. Xilinx will sell defective devices to their customers at a discount (AKA EasyPath). All this due to running test vectors on the chip tester. In the Xilinx case the logistics is more complex as they have to match their customer design databases against the defect list to figure which customer can use it.

Chip testing in the fab and analysis of the output would allow binning and KnC would have the flexibility of either only paying for 100% functional devices, or get a discount on the on partially defective devices. Without fab based testing they would pay the same price for fully functional and defective devices. Offering a second on each device using this procedure is not economically pointless.

Also without fab based testing is difficult to prove that a problem is related to the the ASIC and not some problem in the other areas of the miner. It's kind of like checking the rental car for damage at the time of checkout rather than arguing at return time that the dent is not your fault.

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